1/* 2 * max98927.h -- MAX98927 ALSA Soc Audio driver 3 * 4 * Copyright 2013-15 Maxim Integrated Products 5 * Author: Ryan Lee <ryans.lee@maximintegrated.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 */ 13#ifndef _MAX98927_H 14#define _MAX98927_H 15 16/* Register Values */ 17#define MAX98927_R0001_INT_RAW1 0x0001 18#define MAX98927_R0002_INT_RAW2 0x0002 19#define MAX98927_R0003_INT_RAW3 0x0003 20#define MAX98927_R0004_INT_STATE1 0x0004 21#define MAX98927_R0005_INT_STATE2 0x0005 22#define MAX98927_R0006_INT_STATE3 0x0006 23#define MAX98927_R0007_INT_FLAG1 0x0007 24#define MAX98927_R0008_INT_FLAG2 0x0008 25#define MAX98927_R0009_INT_FLAG3 0x0009 26#define MAX98927_R000A_INT_EN1 0x000A 27#define MAX98927_R000B_INT_EN2 0x000B 28#define MAX98927_R000C_INT_EN3 0x000C 29#define MAX98927_R000D_INT_FLAG_CLR1 0x000D 30#define MAX98927_R000E_INT_FLAG_CLR2 0x000E 31#define MAX98927_R000F_INT_FLAG_CLR3 0x000F 32#define MAX98927_R0010_IRQ_CTRL 0x0010 33#define MAX98927_R0011_CLK_MON 0x0011 34#define MAX98927_R0012_WDOG_CTRL 0x0012 35#define MAX98927_R0013_WDOG_RST 0x0013 36#define MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH 0x0014 37#define MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH 0x0015 38#define MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS 0x0016 39#define MAX98927_R0017_PIN_CFG 0x0017 40#define MAX98927_R0018_PCM_RX_EN_A 0x0018 41#define MAX98927_R0019_PCM_RX_EN_B 0x0019 42#define MAX98927_R001A_PCM_TX_EN_A 0x001A 43#define MAX98927_R001B_PCM_TX_EN_B 0x001B 44#define MAX98927_R001C_PCM_TX_HIZ_CTRL_A 0x001C 45#define MAX98927_R001D_PCM_TX_HIZ_CTRL_B 0x001D 46#define MAX98927_R001E_PCM_TX_CH_SRC_A 0x001E 47#define MAX98927_R001F_PCM_TX_CH_SRC_B 0x001F 48#define MAX98927_R0020_PCM_MODE_CFG 0x0020 49#define MAX98927_R0021_PCM_MASTER_MODE 0x0021 50#define MAX98927_R0022_PCM_CLK_SETUP 0x0022 51#define MAX98927_R0023_PCM_SR_SETUP1 0x0023 52#define MAX98927_R0024_PCM_SR_SETUP2 0x0024 53#define MAX98927_R0025_PCM_TO_SPK_MONOMIX_A 0x0025 54#define MAX98927_R0026_PCM_TO_SPK_MONOMIX_B 0x0026 55#define MAX98927_R0027_ICC_RX_EN_A 0x0027 56#define MAX98927_R0028_ICC_RX_EN_B 0x0028 57#define MAX98927_R002B_ICC_TX_EN_A 0x002B 58#define MAX98927_R002C_ICC_TX_EN_B 0x002C 59#define MAX98927_R002E_ICC_HIZ_MANUAL_MODE 0x002E 60#define MAX98927_R002F_ICC_TX_HIZ_EN_A 0x002F 61#define MAX98927_R0030_ICC_TX_HIZ_EN_B 0x0030 62#define MAX98927_R0031_ICC_LNK_EN 0x0031 63#define MAX98927_R0032_PDM_TX_EN 0x0032 64#define MAX98927_R0033_PDM_TX_HIZ_CTRL 0x0033 65#define MAX98927_R0034_PDM_TX_CTRL 0x0034 66#define MAX98927_R0035_PDM_RX_CTRL 0x0035 67#define MAX98927_R0036_AMP_VOL_CTRL 0x0036 68#define MAX98927_R0037_AMP_DSP_CFG 0x0037 69#define MAX98927_R0038_TONE_GEN_DC_CFG 0x0038 70#define MAX98927_R0039_DRE_CTRL 0x0039 71#define MAX98927_R003A_AMP_EN 0x003A 72#define MAX98927_R003B_SPK_SRC_SEL 0x003B 73#define MAX98927_R003C_SPK_GAIN 0x003C 74#define MAX98927_R003D_SSM_CFG 0x003D 75#define MAX98927_R003E_MEAS_EN 0x003E 76#define MAX98927_R003F_MEAS_DSP_CFG 0x003F 77#define MAX98927_R0040_BOOST_CTRL0 0x0040 78#define MAX98927_R0041_BOOST_CTRL3 0x0041 79#define MAX98927_R0042_BOOST_CTRL1 0x0042 80#define MAX98927_R0043_MEAS_ADC_CFG 0x0043 81#define MAX98927_R0044_MEAS_ADC_BASE_MSB 0x0044 82#define MAX98927_R0045_MEAS_ADC_BASE_LSB 0x0045 83#define MAX98927_R0046_ADC_CH0_DIVIDE 0x0046 84#define MAX98927_R0047_ADC_CH1_DIVIDE 0x0047 85#define MAX98927_R0048_ADC_CH2_DIVIDE 0x0048 86#define MAX98927_R0049_ADC_CH0_FILT_CFG 0x0049 87#define MAX98927_R004A_ADC_CH1_FILT_CFG 0x004A 88#define MAX98927_R004B_ADC_CH2_FILT_CFG 0x004B 89#define MAX98927_R004C_MEAS_ADC_CH0_READ 0x004C 90#define MAX98927_R004D_MEAS_ADC_CH1_READ 0x004D 91#define MAX98927_R004E_MEAS_ADC_CH2_READ 0x004E 92#define MAX98927_R0051_BROWNOUT_STATUS 0x0051 93#define MAX98927_R0052_BROWNOUT_EN 0x0052 94#define MAX98927_R0053_BROWNOUT_INFINITE_HOLD 0x0053 95#define MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR 0x0054 96#define MAX98927_R0055_BROWNOUT_LVL_HOLD 0x0055 97#define MAX98927_R005A_BROWNOUT_LVL1_THRESH 0x005A 98#define MAX98927_R005B_BROWNOUT_LVL2_THRESH 0x005B 99#define MAX98927_R005C_BROWNOUT_LVL3_THRESH 0x005C 100#define MAX98927_R005D_BROWNOUT_LVL4_THRESH 0x005D 101#define MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS 0x005E 102#define MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL 0x005F 103#define MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL 0x0060 104#define MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE 0x0061 105#define MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT 0x0072 106#define MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1 0x0073 107#define MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2 0x0074 108#define MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3 0x0075 109#define MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT 0x0076 110#define MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1 0x0077 111#define MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2 0x0078 112#define MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3 0x0079 113#define MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT 0x007A 114#define MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1 0x007B 115#define MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2 0x007C 116#define MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3 0x007D 117#define MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT 0x007E 118#define MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1 0x007F 119#define MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2 0x0080 120#define MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3 0x0081 121#define MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM 0x0082 122#define MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY 0x0083 123#define MAX98927_R0084_ENV_TRACK_REL_RATE 0x0084 124#define MAX98927_R0085_ENV_TRACK_HOLD_RATE 0x0085 125#define MAX98927_R0086_ENV_TRACK_CTRL 0x0086 126#define MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ 0x0087 127#define MAX98927_R00FF_GLOBAL_SHDN 0x00FF 128#define MAX98927_R0100_SOFT_RESET 0x0100 129#define MAX98927_R01FF_REV_ID 0x01FF 130 131/* MAX98927_R0018_PCM_RX_EN_A */ 132#define MAX98927_PCM_RX_CH0_EN (0x1 << 0) 133#define MAX98927_PCM_RX_CH1_EN (0x1 << 1) 134#define MAX98927_PCM_RX_CH2_EN (0x1 << 2) 135#define MAX98927_PCM_RX_CH3_EN (0x1 << 3) 136#define MAX98927_PCM_RX_CH4_EN (0x1 << 4) 137#define MAX98927_PCM_RX_CH5_EN (0x1 << 5) 138#define MAX98927_PCM_RX_CH6_EN (0x1 << 6) 139#define MAX98927_PCM_RX_CH7_EN (0x1 << 7) 140 141/* MAX98927_R001A_PCM_TX_EN_A */ 142#define MAX98927_PCM_TX_CH0_EN (0x1 << 0) 143#define MAX98927_PCM_TX_CH1_EN (0x1 << 1) 144#define MAX98927_PCM_TX_CH2_EN (0x1 << 2) 145#define MAX98927_PCM_TX_CH3_EN (0x1 << 3) 146#define MAX98927_PCM_TX_CH4_EN (0x1 << 4) 147#define MAX98927_PCM_TX_CH5_EN (0x1 << 5) 148#define MAX98927_PCM_TX_CH6_EN (0x1 << 6) 149#define MAX98927_PCM_TX_CH7_EN (0x1 << 7) 150 151/* MAX98927_R001E_PCM_TX_CH_SRC_A */ 152#define MAX98927_PCM_TX_CH_SRC_A_V_SHIFT (0) 153#define MAX98927_PCM_TX_CH_SRC_A_I_SHIFT (4) 154 155/* MAX98927_R001F_PCM_TX_CH_SRC_B */ 156#define MAX98927_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 5) 157 158/* MAX98927_R0020_PCM_MODE_CFG */ 159#define MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 2) 160#define MAX98927_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3) 161#define MAX98927_PCM_MODE_CFG_FORMAT_SHIFT (3) 162#define MAX98927_PCM_FORMAT_I2S (0x0 << 0) 163#define MAX98927_PCM_FORMAT_LJ (0x1 << 0) 164 165#define MAX98927_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6) 166#define MAX98927_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6) 167#define MAX98927_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6) 168#define MAX98927_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6) 169 170/* MAX98927_R0021_PCM_MASTER_MODE */ 171#define MAX98927_PCM_MASTER_MODE_MASK (0x3 << 0) 172#define MAX98927_PCM_MASTER_MODE_SLAVE (0x0 << 0) 173#define MAX98927_PCM_MASTER_MODE_MASTER (0x3 << 0) 174 175#define MAX98927_PCM_MASTER_MODE_MCLK_MASK (0xF << 2) 176#define MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT (2) 177 178/* MAX98927_R0022_PCM_CLK_SETUP */ 179#define MAX98927_PCM_CLK_SETUP_BSEL_MASK (0xF << 0) 180 181/* MAX98927_R0023_PCM_SR_SETUP1 */ 182#define MAX98927_PCM_SR_SET1_SR_MASK (0xF << 0) 183 184#define MAX98927_PCM_SR_SET1_SR_8000 (0x0 << 0) 185#define MAX98927_PCM_SR_SET1_SR_11025 (0x1 << 0) 186#define MAX98927_PCM_SR_SET1_SR_12000 (0x2 << 0) 187#define MAX98927_PCM_SR_SET1_SR_16000 (0x3 << 0) 188#define MAX98927_PCM_SR_SET1_SR_22050 (0x4 << 0) 189#define MAX98927_PCM_SR_SET1_SR_24000 (0x5 << 0) 190#define MAX98927_PCM_SR_SET1_SR_32000 (0x6 << 0) 191#define MAX98927_PCM_SR_SET1_SR_44100 (0x7 << 0) 192#define MAX98927_PCM_SR_SET1_SR_48000 (0x8 << 0) 193 194/* MAX98927_R0024_PCM_SR_SETUP2 */ 195#define MAX98927_PCM_SR_SET2_SR_MASK (0xF << 4) 196#define MAX98927_PCM_SR_SET2_SR_SHIFT (4) 197#define MAX98927_PCM_SR_SET2_IVADC_SR_MASK (0xf << 0) 198 199/* MAX98927_R0025_PCM_TO_SPK_MONOMIX_A */ 200#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6) 201#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6) 202 203/* MAX98927_R0035_PDM_RX_CTRL */ 204#define MAX98927_PDM_RX_EN_MASK (0x1 << 0) 205 206/* MAX98927_R0036_AMP_VOL_CTRL */ 207#define MAX98927_AMP_VOL_SEL (0x1 << 7) 208#define MAX98927_AMP_VOL_SEL_WIDTH (1) 209#define MAX98927_AMP_VOL_SEL_SHIFT (7) 210#define MAX98927_AMP_VOL_MASK (0x7f << 0) 211#define MAX98927_AMP_VOL_WIDTH (7) 212#define MAX98927_AMP_VOL_SHIFT (0) 213 214/* MAX98927_R0037_AMP_DSP_CFG */ 215#define MAX98927_AMP_DSP_CFG_DCBLK_EN (0x1 << 0) 216#define MAX98927_AMP_DSP_CFG_DITH_EN (0x1 << 1) 217#define MAX98927_AMP_DSP_CFG_RMP_BYPASS (0x1 << 4) 218#define MAX98927_AMP_DSP_CFG_DAC_INV (0x1 << 5) 219#define MAX98927_AMP_DSP_CFG_RMP_SHIFT (4) 220 221/* MAX98927_R0039_DRE_CTRL */ 222#define MAX98927_DRE_CTRL_DRE_EN (0x1 << 0) 223#define MAX98927_DRE_EN_SHIFT 0x1 224 225/* MAX98927_R003A_AMP_EN */ 226#define MAX98927_AMP_EN_MASK (0x1 << 0) 227 228/* MAX98927_R003B_SPK_SRC_SEL */ 229#define MAX98927_SPK_SRC_MASK (0x3 << 0) 230 231/* MAX98927_R003C_SPK_GAIN */ 232#define MAX98927_SPK_PCM_GAIN_MASK (0x7 << 0) 233#define MAX98927_SPK_PDM_GAIN_MASK (0x7 << 4) 234#define MAX98927_SPK_GAIN_WIDTH (3) 235 236/* MAX98927_R003E_MEAS_EN */ 237#define MAX98927_MEAS_V_EN (0x1 << 0) 238#define MAX98927_MEAS_I_EN (0x1 << 1) 239 240/* MAX98927_R0040_BOOST_CTRL0 */ 241#define MAX98927_BOOST_CTRL0_VOUT_MASK (0x1f << 0) 242#define MAX98927_BOOST_CTRL0_PVDD_MASK (0x1 << 7) 243#define MAX98927_BOOST_CTRL0_PVDD_EN_SHIFT (7) 244 245/* MAX98927_R0052_BROWNOUT_EN */ 246#define MAX98927_BROWNOUT_BDE_EN (0x1 << 0) 247#define MAX98927_BROWNOUT_AMP_EN (0x1 << 1) 248#define MAX98927_BROWNOUT_DSP_EN (0x1 << 2) 249#define MAX98927_BROWNOUT_DSP_SHIFT (2) 250 251/* MAX98927_R0100_SOFT_RESET */ 252#define MAX98927_SOFT_RESET (0x1 << 0) 253 254/* MAX98927_R00FF_GLOBAL_SHDN */ 255#define MAX98927_GLOBAL_EN_MASK (0x1 << 0) 256 257struct max98927_priv { 258 struct regmap *regmap; 259 struct snd_soc_codec *codec; 260 struct max98927_pdata *pdata; 261 unsigned int spk_gain; 262 unsigned int sysclk; 263 unsigned int v_l_slot; 264 unsigned int i_l_slot; 265 bool interleave_mode; 266 unsigned int ch_size; 267 unsigned int rate; 268 unsigned int iface; 269 unsigned int master; 270 unsigned int digital_gain; 271}; 272#endif 273