1/* 2 * NAU85L40 ALSA SoC audio driver 3 * 4 * Copyright 2016 Nuvoton Technology Corp. 5 * Author: John Hsu <KCHSU0@nuvoton.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#ifndef __NAU8540_H__ 13#define __NAU8540_H__ 14 15#define NAU8540_REG_SW_RESET 0x00 16#define NAU8540_REG_POWER_MANAGEMENT 0x01 17#define NAU8540_REG_CLOCK_CTRL 0x02 18#define NAU8540_REG_CLOCK_SRC 0x03 19#define NAU8540_REG_FLL1 0x04 20#define NAU8540_REG_FLL2 0x05 21#define NAU8540_REG_FLL3 0x06 22#define NAU8540_REG_FLL4 0x07 23#define NAU8540_REG_FLL5 0x08 24#define NAU8540_REG_FLL6 0x09 25#define NAU8540_REG_FLL_VCO_RSV 0x0A 26#define NAU8540_REG_PCM_CTRL0 0x10 27#define NAU8540_REG_PCM_CTRL1 0x11 28#define NAU8540_REG_PCM_CTRL2 0x12 29#define NAU8540_REG_PCM_CTRL3 0x13 30#define NAU8540_REG_PCM_CTRL4 0x14 31#define NAU8540_REG_ALC_CONTROL_1 0x20 32#define NAU8540_REG_ALC_CONTROL_2 0x21 33#define NAU8540_REG_ALC_CONTROL_3 0x22 34#define NAU8540_REG_ALC_CONTROL_4 0x23 35#define NAU8540_REG_ALC_CONTROL_5 0x24 36#define NAU8540_REG_ALC_GAIN_CH12 0x2D 37#define NAU8540_REG_ALC_GAIN_CH34 0x2E 38#define NAU8540_REG_ALC_STATUS 0x2F 39#define NAU8540_REG_NOTCH_FIL1_CH1 0x30 40#define NAU8540_REG_NOTCH_FIL2_CH1 0x31 41#define NAU8540_REG_NOTCH_FIL1_CH2 0x32 42#define NAU8540_REG_NOTCH_FIL2_CH2 0x33 43#define NAU8540_REG_NOTCH_FIL1_CH3 0x34 44#define NAU8540_REG_NOTCH_FIL2_CH3 0x35 45#define NAU8540_REG_NOTCH_FIL1_CH4 0x36 46#define NAU8540_REG_NOTCH_FIL2_CH4 0x37 47#define NAU8540_REG_HPF_FILTER_CH12 0x38 48#define NAU8540_REG_HPF_FILTER_CH34 0x39 49#define NAU8540_REG_ADC_SAMPLE_RATE 0x3A 50#define NAU8540_REG_DIGITAL_GAIN_CH1 0x40 51#define NAU8540_REG_DIGITAL_GAIN_CH2 0x41 52#define NAU8540_REG_DIGITAL_GAIN_CH3 0x42 53#define NAU8540_REG_DIGITAL_GAIN_CH4 0x43 54#define NAU8540_REG_DIGITAL_MUX 0x44 55#define NAU8540_REG_P2P_CH1 0x48 56#define NAU8540_REG_P2P_CH2 0x49 57#define NAU8540_REG_P2P_CH3 0x4A 58#define NAU8540_REG_P2P_CH4 0x4B 59#define NAU8540_REG_PEAK_CH1 0x4C 60#define NAU8540_REG_PEAK_CH2 0x4D 61#define NAU8540_REG_PEAK_CH3 0x4E 62#define NAU8540_REG_PEAK_CH4 0x4F 63#define NAU8540_REG_GPIO_CTRL 0x50 64#define NAU8540_REG_MISC_CTRL 0x51 65#define NAU8540_REG_I2C_CTRL 0x52 66#define NAU8540_REG_I2C_DEVICE_ID 0x58 67#define NAU8540_REG_RST 0x5A 68#define NAU8540_REG_VMID_CTRL 0x60 69#define NAU8540_REG_MUTE 0x61 70#define NAU8540_REG_ANALOG_ADC1 0x64 71#define NAU8540_REG_ANALOG_ADC2 0x65 72#define NAU8540_REG_ANALOG_PWR 0x66 73#define NAU8540_REG_MIC_BIAS 0x67 74#define NAU8540_REG_REFERENCE 0x68 75#define NAU8540_REG_FEPGA1 0x69 76#define NAU8540_REG_FEPGA2 0x6A 77#define NAU8540_REG_FEPGA3 0x6B 78#define NAU8540_REG_FEPGA4 0x6C 79#define NAU8540_REG_PWR 0x6D 80#define NAU8540_REG_MAX NAU8540_REG_PWR 81 82 83/* POWER_MANAGEMENT (0x01) */ 84#define NAU8540_ADC4_EN (0x1 << 3) 85#define NAU8540_ADC3_EN (0x1 << 2) 86#define NAU8540_ADC2_EN (0x1 << 1) 87#define NAU8540_ADC1_EN 0x1 88 89/* CLOCK_CTRL (0x02) */ 90#define NAU8540_CLK_ADC_EN (0x1 << 15) 91#define NAU8540_CLK_I2S_EN (0x1 << 1) 92 93/* CLOCK_SRC (0x03) */ 94#define NAU8540_CLK_SRC_SFT 15 95#define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT) 96#define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT) 97#define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT) 98#define NAU8540_CLK_ADC_SRC_SFT 6 99#define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT) 100#define NAU8540_CLK_MCLK_SRC_MASK 0xf 101 102/* FLL1 (0x04) */ 103#define NAU8540_FLL_RATIO_MASK 0x7f 104 105/* FLL3 (0x06) */ 106#define NAU8540_FLL_CLK_SRC_SFT 10 107#define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT) 108#define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT) 109#define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT) 110#define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT) 111#define NAU8540_FLL_INTEGER_MASK 0x3ff 112 113/* FLL4 (0x07) */ 114#define NAU8540_FLL_REF_DIV_SFT 10 115#define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT) 116 117/* FLL5 (0x08) */ 118#define NAU8540_FLL_PDB_DAC_EN (0x1 << 15) 119#define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14) 120#define NAU8540_FLL_CLK_SW_MASK (0x1 << 13) 121#define NAU8540_FLL_CLK_SW_N2 (0x1 << 13) 122#define NAU8540_FLL_CLK_SW_REF (0x0 << 13) 123#define NAU8540_FLL_FTR_SW_MASK (0x1 << 12) 124#define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12) 125#define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12) 126 127/* FLL6 (0x9) */ 128#define NAU8540_DCO_EN (0x1 << 15) 129#define NAU8540_SDM_EN (0x1 << 14) 130 131/* PCM_CTRL0 (0x10) */ 132#define NAU8540_I2S_BP_SFT 7 133#define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT) 134#define NAU8540_I2S_PCMB_SFT 6 135#define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT) 136#define NAU8540_I2S_DL_SFT 2 137#define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT) 138#define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT) 139#define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT) 140#define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT) 141#define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT) 142#define NAU8540_I2S_DF_MASK 0x3 143#define NAU8540_I2S_DF_RIGTH 0 144#define NAU8540_I2S_DF_LEFT 0x1 145#define NAU8540_I2S_DF_I2S 0x2 146#define NAU8540_I2S_DF_PCM_AB 0x3 147 148/* PCM_CTRL1 (0x11) */ 149#define NAU8540_I2S_LRC_DIV_SFT 12 150#define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT) 151#define NAU8540_I2S_DO12_OE (0x1 << 4) 152#define NAU8540_I2S_MS_SFT 3 153#define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT) 154#define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT) 155#define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT) 156#define NAU8540_I2S_BLK_DIV_MASK 0x7 157 158/* PCM_CTRL1 (0x12) */ 159#define NAU8540_I2S_DO34_OE (0x1 << 11) 160#define NAU8540_I2S_TSLOT_L_MASK 0x3ff 161 162/* PCM_CTRL4 (0x14) */ 163#define NAU8540_TDM_MODE (0x1 << 15) 164#define NAU8540_TDM_OFFSET_EN (0x1 << 14) 165#define NAU8540_TDM_TX_MASK 0xf 166 167/* ADC_SAMPLE_RATE (0x3A) */ 168#define NAU8540_ADC_OSR_MASK 0x3 169#define NAU8540_ADC_OSR_256 0x3 170#define NAU8540_ADC_OSR_128 0x2 171#define NAU8540_ADC_OSR_64 0x1 172#define NAU8540_ADC_OSR_32 0x0 173 174/* VMID_CTRL (0x60) */ 175#define NAU8540_VMID_EN (1 << 6) 176#define NAU8540_VMID_SEL_SFT 4 177#define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT) 178 179/* MIC_BIAS (0x67) */ 180#define NAU8540_PU_PRE (0x1 << 8) 181 182/* REFERENCE (0x68) */ 183#define NAU8540_PRECHARGE_DIS (0x1 << 13) 184#define NAU8540_GLOBAL_BIAS_EN (0x1 << 12) 185 186 187/* System Clock Source */ 188enum { 189 NAU8540_CLK_DIS, 190 NAU8540_CLK_MCLK, 191 NAU8540_CLK_INTERNAL, 192 NAU8540_CLK_FLL_MCLK, 193 NAU8540_CLK_FLL_BLK, 194 NAU8540_CLK_FLL_FS, 195}; 196 197struct nau8540 { 198 struct device *dev; 199 struct regmap *regmap; 200}; 201 202struct nau8540_fll { 203 int mclk_src; 204 int ratio; 205 int fll_frac; 206 int fll_int; 207 int clk_ref_div; 208}; 209 210struct nau8540_fll_attr { 211 unsigned int param; 212 unsigned int val; 213}; 214 215/* over sampling rate */ 216struct nau8540_osr_attr { 217 unsigned int osr; 218 unsigned int clk_src; 219}; 220 221 222#endif /* __NAU8540_H__ */ 223