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28#include <linux/clk.h>
29#include <linux/device.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/platform_device.h>
35#include <linux/pm_runtime.h>
36#include <linux/regmap.h>
37#include <linux/slab.h>
38#include <sound/core.h>
39#include <sound/pcm.h>
40#include <sound/pcm_params.h>
41#include <sound/soc.h>
42#include <sound/dmaengine_pcm.h>
43
44#include "tegra30_ahub.h"
45#include "tegra30_i2s.h"
46
47#define DRV_NAME "tegra30-i2s"
48
49static int tegra30_i2s_runtime_suspend(struct device *dev)
50{
51 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
52
53 regcache_cache_only(i2s->regmap, true);
54
55 clk_disable_unprepare(i2s->clk_i2s);
56
57 return 0;
58}
59
60static int tegra30_i2s_runtime_resume(struct device *dev)
61{
62 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
63 int ret;
64
65 ret = clk_prepare_enable(i2s->clk_i2s);
66 if (ret) {
67 dev_err(dev, "clk_enable failed: %d\n", ret);
68 return ret;
69 }
70
71 regcache_cache_only(i2s->regmap, false);
72
73 return 0;
74}
75
76static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
77 unsigned int fmt)
78{
79 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
80 unsigned int mask = 0, val = 0;
81
82 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
83 case SND_SOC_DAIFMT_NB_NF:
84 break;
85 default:
86 return -EINVAL;
87 }
88
89 mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
90 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
91 case SND_SOC_DAIFMT_CBS_CFS:
92 val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
93 break;
94 case SND_SOC_DAIFMT_CBM_CFM:
95 break;
96 default:
97 return -EINVAL;
98 }
99
100 mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
101 TEGRA30_I2S_CTRL_LRCK_MASK;
102 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
103 case SND_SOC_DAIFMT_DSP_A:
104 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
105 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
106 break;
107 case SND_SOC_DAIFMT_DSP_B:
108 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
109 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
110 break;
111 case SND_SOC_DAIFMT_I2S:
112 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
113 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
114 break;
115 case SND_SOC_DAIFMT_RIGHT_J:
116 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
117 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
118 break;
119 case SND_SOC_DAIFMT_LEFT_J:
120 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
121 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
122 break;
123 default:
124 return -EINVAL;
125 }
126
127 pm_runtime_get_sync(dai->dev);
128 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
129 pm_runtime_put(dai->dev);
130
131 return 0;
132}
133
134static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
135 struct snd_pcm_hw_params *params,
136 struct snd_soc_dai *dai)
137{
138 struct device *dev = dai->dev;
139 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
140 unsigned int mask, val, reg;
141 int ret, sample_size, srate, i2sclock, bitcnt;
142 struct tegra30_ahub_cif_conf cif_conf;
143
144 if (params_channels(params) != 2)
145 return -EINVAL;
146
147 mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
148 switch (params_format(params)) {
149 case SNDRV_PCM_FORMAT_S16_LE:
150 val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
151 sample_size = 16;
152 break;
153 default:
154 return -EINVAL;
155 }
156
157 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
158
159 srate = params_rate(params);
160
161
162 i2sclock = srate * params_channels(params) * sample_size * 2;
163
164 bitcnt = (i2sclock / (2 * srate)) - 1;
165 if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
166 return -EINVAL;
167
168 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
169 if (ret) {
170 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
171 return ret;
172 }
173
174 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
175
176 if (i2sclock % (2 * srate))
177 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
178
179 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
180
181 cif_conf.threshold = 0;
182 cif_conf.audio_channels = 2;
183 cif_conf.client_channels = 2;
184 cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
185 cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
186 cif_conf.expand = 0;
187 cif_conf.stereo_conv = 0;
188 cif_conf.replicate = 0;
189 cif_conf.truncate = 0;
190 cif_conf.mono_conv = 0;
191
192 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
193 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
194 reg = TEGRA30_I2S_CIF_RX_CTRL;
195 } else {
196 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
197 reg = TEGRA30_I2S_CIF_TX_CTRL;
198 }
199
200 i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
201
202 val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
203 (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
204 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
205
206 return 0;
207}
208
209static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
210{
211 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
212 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
213 TEGRA30_I2S_CTRL_XFER_EN_TX,
214 TEGRA30_I2S_CTRL_XFER_EN_TX);
215}
216
217static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
218{
219 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
220 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
221 TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
222}
223
224static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
225{
226 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
227 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
228 TEGRA30_I2S_CTRL_XFER_EN_RX,
229 TEGRA30_I2S_CTRL_XFER_EN_RX);
230}
231
232static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
233{
234 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
235 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
236 TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
237}
238
239static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
240 struct snd_soc_dai *dai)
241{
242 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
243
244 switch (cmd) {
245 case SNDRV_PCM_TRIGGER_START:
246 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
247 case SNDRV_PCM_TRIGGER_RESUME:
248 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
249 tegra30_i2s_start_playback(i2s);
250 else
251 tegra30_i2s_start_capture(i2s);
252 break;
253 case SNDRV_PCM_TRIGGER_STOP:
254 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
255 case SNDRV_PCM_TRIGGER_SUSPEND:
256 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
257 tegra30_i2s_stop_playback(i2s);
258 else
259 tegra30_i2s_stop_capture(i2s);
260 break;
261 default:
262 return -EINVAL;
263 }
264
265 return 0;
266}
267
268static int tegra30_i2s_probe(struct snd_soc_dai *dai)
269{
270 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
271
272 dai->capture_dma_data = &i2s->capture_dma_data;
273 dai->playback_dma_data = &i2s->playback_dma_data;
274
275 return 0;
276}
277
278static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
279 .set_fmt = tegra30_i2s_set_fmt,
280 .hw_params = tegra30_i2s_hw_params,
281 .trigger = tegra30_i2s_trigger,
282};
283
284static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
285 .probe = tegra30_i2s_probe,
286 .playback = {
287 .stream_name = "Playback",
288 .channels_min = 2,
289 .channels_max = 2,
290 .rates = SNDRV_PCM_RATE_8000_96000,
291 .formats = SNDRV_PCM_FMTBIT_S16_LE,
292 },
293 .capture = {
294 .stream_name = "Capture",
295 .channels_min = 2,
296 .channels_max = 2,
297 .rates = SNDRV_PCM_RATE_8000_96000,
298 .formats = SNDRV_PCM_FMTBIT_S16_LE,
299 },
300 .ops = &tegra30_i2s_dai_ops,
301 .symmetric_rates = 1,
302};
303
304static const struct snd_soc_component_driver tegra30_i2s_component = {
305 .name = DRV_NAME,
306};
307
308static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
309{
310 switch (reg) {
311 case TEGRA30_I2S_CTRL:
312 case TEGRA30_I2S_TIMING:
313 case TEGRA30_I2S_OFFSET:
314 case TEGRA30_I2S_CH_CTRL:
315 case TEGRA30_I2S_SLOT_CTRL:
316 case TEGRA30_I2S_CIF_RX_CTRL:
317 case TEGRA30_I2S_CIF_TX_CTRL:
318 case TEGRA30_I2S_FLOWCTL:
319 case TEGRA30_I2S_TX_STEP:
320 case TEGRA30_I2S_FLOW_STATUS:
321 case TEGRA30_I2S_FLOW_TOTAL:
322 case TEGRA30_I2S_FLOW_OVER:
323 case TEGRA30_I2S_FLOW_UNDER:
324 case TEGRA30_I2S_LCOEF_1_4_0:
325 case TEGRA30_I2S_LCOEF_1_4_1:
326 case TEGRA30_I2S_LCOEF_1_4_2:
327 case TEGRA30_I2S_LCOEF_1_4_3:
328 case TEGRA30_I2S_LCOEF_1_4_4:
329 case TEGRA30_I2S_LCOEF_1_4_5:
330 case TEGRA30_I2S_LCOEF_2_4_0:
331 case TEGRA30_I2S_LCOEF_2_4_1:
332 case TEGRA30_I2S_LCOEF_2_4_2:
333 return true;
334 default:
335 return false;
336 }
337}
338
339static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
340{
341 switch (reg) {
342 case TEGRA30_I2S_FLOW_STATUS:
343 case TEGRA30_I2S_FLOW_TOTAL:
344 case TEGRA30_I2S_FLOW_OVER:
345 case TEGRA30_I2S_FLOW_UNDER:
346 return true;
347 default:
348 return false;
349 }
350}
351
352static const struct regmap_config tegra30_i2s_regmap_config = {
353 .reg_bits = 32,
354 .reg_stride = 4,
355 .val_bits = 32,
356 .max_register = TEGRA30_I2S_LCOEF_2_4_2,
357 .writeable_reg = tegra30_i2s_wr_rd_reg,
358 .readable_reg = tegra30_i2s_wr_rd_reg,
359 .volatile_reg = tegra30_i2s_volatile_reg,
360 .cache_type = REGCACHE_FLAT,
361};
362
363static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
364 .set_audio_cif = tegra30_ahub_set_cif,
365};
366
367static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
368 .set_audio_cif = tegra124_ahub_set_cif,
369};
370
371static const struct of_device_id tegra30_i2s_of_match[] = {
372 { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
373 { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
374 {},
375};
376
377static int tegra30_i2s_platform_probe(struct platform_device *pdev)
378{
379 struct tegra30_i2s *i2s;
380 const struct of_device_id *match;
381 u32 cif_ids[2];
382 struct resource *mem;
383 void __iomem *regs;
384 int ret;
385
386 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
387 if (!i2s) {
388 ret = -ENOMEM;
389 goto err;
390 }
391 dev_set_drvdata(&pdev->dev, i2s);
392
393 match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
394 if (!match) {
395 dev_err(&pdev->dev, "Error: No device match found\n");
396 ret = -ENODEV;
397 goto err;
398 }
399 i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
400
401 i2s->dai = tegra30_i2s_dai_template;
402 i2s->dai.name = dev_name(&pdev->dev);
403
404 ret = of_property_read_u32_array(pdev->dev.of_node,
405 "nvidia,ahub-cif-ids", cif_ids,
406 ARRAY_SIZE(cif_ids));
407 if (ret < 0)
408 goto err;
409
410 i2s->playback_i2s_cif = cif_ids[0];
411 i2s->capture_i2s_cif = cif_ids[1];
412
413 i2s->clk_i2s = clk_get(&pdev->dev, NULL);
414 if (IS_ERR(i2s->clk_i2s)) {
415 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
416 ret = PTR_ERR(i2s->clk_i2s);
417 goto err;
418 }
419
420 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
421 regs = devm_ioremap_resource(&pdev->dev, mem);
422 if (IS_ERR(regs)) {
423 ret = PTR_ERR(regs);
424 goto err_clk_put;
425 }
426
427 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
428 &tegra30_i2s_regmap_config);
429 if (IS_ERR(i2s->regmap)) {
430 dev_err(&pdev->dev, "regmap init failed\n");
431 ret = PTR_ERR(i2s->regmap);
432 goto err_clk_put;
433 }
434 regcache_cache_only(i2s->regmap, true);
435
436 pm_runtime_enable(&pdev->dev);
437 if (!pm_runtime_enabled(&pdev->dev)) {
438 ret = tegra30_i2s_runtime_resume(&pdev->dev);
439 if (ret)
440 goto err_pm_disable;
441 }
442
443 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
444 i2s->playback_dma_data.maxburst = 4;
445 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
446 i2s->playback_dma_chan,
447 sizeof(i2s->playback_dma_chan),
448 &i2s->playback_dma_data.addr);
449 if (ret) {
450 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
451 goto err_suspend;
452 }
453 ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
454 i2s->playback_fifo_cif);
455 if (ret) {
456 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
457 goto err_free_tx_fifo;
458 }
459
460 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
461 i2s->capture_dma_data.maxburst = 4;
462 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
463 i2s->capture_dma_chan,
464 sizeof(i2s->capture_dma_chan),
465 &i2s->capture_dma_data.addr);
466 if (ret) {
467 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
468 goto err_unroute_tx_fifo;
469 }
470 ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
471 i2s->capture_i2s_cif);
472 if (ret) {
473 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
474 goto err_free_rx_fifo;
475 }
476
477 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
478 &i2s->dai, 1);
479 if (ret) {
480 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
481 ret = -ENOMEM;
482 goto err_unroute_rx_fifo;
483 }
484
485 ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
486 &i2s->dma_config, i2s->playback_dma_chan,
487 i2s->capture_dma_chan);
488 if (ret) {
489 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
490 goto err_unregister_component;
491 }
492
493 return 0;
494
495err_unregister_component:
496 snd_soc_unregister_component(&pdev->dev);
497err_unroute_rx_fifo:
498 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
499err_free_rx_fifo:
500 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
501err_unroute_tx_fifo:
502 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
503err_free_tx_fifo:
504 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
505err_suspend:
506 if (!pm_runtime_status_suspended(&pdev->dev))
507 tegra30_i2s_runtime_suspend(&pdev->dev);
508err_pm_disable:
509 pm_runtime_disable(&pdev->dev);
510err_clk_put:
511 clk_put(i2s->clk_i2s);
512err:
513 return ret;
514}
515
516static int tegra30_i2s_platform_remove(struct platform_device *pdev)
517{
518 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
519
520 pm_runtime_disable(&pdev->dev);
521 if (!pm_runtime_status_suspended(&pdev->dev))
522 tegra30_i2s_runtime_suspend(&pdev->dev);
523
524 tegra_pcm_platform_unregister(&pdev->dev);
525 snd_soc_unregister_component(&pdev->dev);
526
527 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
528 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
529
530 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
531 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
532
533 clk_put(i2s->clk_i2s);
534
535 return 0;
536}
537
538#ifdef CONFIG_PM_SLEEP
539static int tegra30_i2s_suspend(struct device *dev)
540{
541 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
542
543 regcache_mark_dirty(i2s->regmap);
544
545 return 0;
546}
547
548static int tegra30_i2s_resume(struct device *dev)
549{
550 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
551 int ret;
552
553 ret = pm_runtime_get_sync(dev);
554 if (ret < 0)
555 return ret;
556 ret = regcache_sync(i2s->regmap);
557 pm_runtime_put(dev);
558
559 return ret;
560}
561#endif
562
563static const struct dev_pm_ops tegra30_i2s_pm_ops = {
564 SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
565 tegra30_i2s_runtime_resume, NULL)
566 SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
567};
568
569static struct platform_driver tegra30_i2s_driver = {
570 .driver = {
571 .name = DRV_NAME,
572 .of_match_table = tegra30_i2s_of_match,
573 .pm = &tegra30_i2s_pm_ops,
574 },
575 .probe = tegra30_i2s_platform_probe,
576 .remove = tegra30_i2s_platform_remove,
577};
578module_platform_driver(tegra30_i2s_driver);
579
580MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
581MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
582MODULE_LICENSE("GPL");
583MODULE_ALIAS("platform:" DRV_NAME);
584MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
585
