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16#include <linux/gpio.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/io.h>
21
22#include <mach/board-ams-delta.h>
23
24#include <asm/fiq.h>
25
26#include <mach/ams-delta-fiq.h>
27
28static struct fiq_handler fh = {
29 .name = "ams-delta-fiq"
30};
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40unsigned int fiq_buffer[1024];
41EXPORT_SYMBOL(fiq_buffer);
42
43static unsigned int irq_counter[16];
44
45static irqreturn_t deferred_fiq(int irq, void *dev_id)
46{
47 int gpio, irq_num, fiq_count;
48 struct irq_chip *irq_chip;
49
50 irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
51
52
53
54
55
56 for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
57 gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
58 irq_num = gpio_to_irq(gpio);
59 fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
60
61 while (irq_counter[gpio] < fiq_count) {
62 if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
63 struct irq_data *d = irq_get_irq_data(irq_num);
64
65
66
67
68
69
70 if (irq_chip && irq_chip->irq_unmask)
71 irq_chip->irq_unmask(d);
72 }
73 generic_handle_irq(irq_num);
74
75 irq_counter[gpio]++;
76 }
77 }
78 return IRQ_HANDLED;
79}
80
81void __init ams_delta_init_fiq(void)
82{
83 void *fiqhandler_start;
84 unsigned int fiqhandler_length;
85 struct pt_regs FIQ_regs;
86 unsigned long val, offset;
87 int i, retval;
88
89 fiqhandler_start = &qwerty_fiqin_start;
90 fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
91 pr_info("Installing fiq handler from %p, length 0x%x\n",
92 fiqhandler_start, fiqhandler_length);
93
94 retval = claim_fiq(&fh);
95 if (retval) {
96 pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
97 retval);
98 return;
99 }
100
101 retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
102 IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
103 if (retval < 0) {
104 pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
105 release_fiq(&fh);
106 return;
107 }
108
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111
112 offset = IRQ_ILR0_REG_OFFSET +
113 ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
114 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
115 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
116
117 set_fiq_handler(fiqhandler_start, fiqhandler_length);
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122
123 fiq_buffer[FIQ_GPIO_INT_MASK] = 0;
124 fiq_buffer[FIQ_MASK] = 0;
125 fiq_buffer[FIQ_STATE] = 0;
126 fiq_buffer[FIQ_KEY] = 0;
127 fiq_buffer[FIQ_KEYS_CNT] = 0;
128 fiq_buffer[FIQ_KEYS_HICNT] = 0;
129 fiq_buffer[FIQ_TAIL_OFFSET] = 0;
130 fiq_buffer[FIQ_HEAD_OFFSET] = 0;
131 fiq_buffer[FIQ_BUF_LEN] = 256;
132 fiq_buffer[FIQ_MISSED_KEYS] = 0;
133 fiq_buffer[FIQ_BUFFER_START] =
134 (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
135
136 for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
137 fiq_buffer[i] = 0;
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145 FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
146 set_fiq_regs(&FIQ_regs);
147
148 pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
149
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152
153 offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
154 val = omap_readl(OMAP_IH1_BASE + offset) | 1;
155 omap_writel(val, OMAP_IH1_BASE + offset);
156}
157