LXR linux/arch/arm/mach-s3c24xx/common.c

   1/* linux/arch/arm/plat-s3c24xx/cpu.c
   2 *
   3 * Copyright (c) 2004-2005 Simtec Electronics
   4 *      http://www.simtec.co.uk/products/SWLINUX/
   5 *      Ben Dooks <ben@simtec.co.uk>
   6 *
   7 * Common code for S3C24XX machines
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22*/
  23
  24#include <linux/dma-mapping.h>
  25#include <linux/init.h>
  26#include <linux/module.h>
  27#include <linux/interrupt.h>
  28#include <linux/ioport.h>
  29#include <linux/serial_core.h>
  30#include <linux/serial_s3c.h>
  31#include <clocksource/samsung_pwm.h>
  32#include <linux/platform_device.h>
  33#include <linux/delay.h>
  34#include <linux/io.h>
  35#include <linux/platform_data/dma-s3c24xx.h>
  36#include <linux/dmaengine.h>
  37
  38#include <mach/hardware.h>
  39#include <mach/regs-clock.h>
  40#include <asm/irq.h>
  41#include <asm/cacheflush.h>
  42#include <asm/system_info.h>
  43#include <asm/system_misc.h>
  44
  45#include <asm/mach/arch.h>
  46#include <asm/mach/map.h>
  47
  48#include <mach/regs-gpio.h>
  49#include <mach/dma.h>
  50
  51#include <plat/cpu.h>
  52#include <plat/devs.h>
  53#include <plat/cpu-freq.h>
  54#include <plat/pwm-core.h>
  55
  56#include "common.h"
  57
  58/* table of supported CPUs */
  59
  60static const char name_s3c2410[]  = "S3C2410";
  61static const char name_s3c2412[]  = "S3C2412";
  62static const char name_s3c2416[]  = "S3C2416/S3C2450";
  63static const char name_s3c2440[]  = "S3C2440";
  64static const char name_s3c2442[]  = "S3C2442";
  65static const char name_s3c2442b[]  = "S3C2442B";
  66static const char name_s3c2443[]  = "S3C2443";
  67static const char name_s3c2410a[] = "S3C2410A";
  68static const char name_s3c2440a[] = "S3C2440A";
  69
  70static struct cpu_table cpu_ids[] __initdata = {
  71        {
  72                .idcode         = 0x32410000,
  73                .idmask         = 0xffffffff,
  74                .map_io         = s3c2410_map_io,
  75                .init_uarts     = s3c2410_init_uarts,
  76                .init           = s3c2410_init,
  77                .name           = name_s3c2410
  78        },
  79        {
  80                .idcode         = 0x32410002,
  81                .idmask         = 0xffffffff,
  82                .map_io         = s3c2410_map_io,
  83                .init_uarts     = s3c2410_init_uarts,
  84                .init           = s3c2410a_init,
  85                .name           = name_s3c2410a
  86        },
  87        {
  88                .idcode         = 0x32440000,
  89                .idmask         = 0xffffffff,
  90                .map_io         = s3c2440_map_io,
  91                .init_uarts     = s3c244x_init_uarts,
  92                .init           = s3c2440_init,
  93                .name           = name_s3c2440
  94        },
  95        {
  96                .idcode         = 0x32440001,
  97                .idmask         = 0xffffffff,
  98                .map_io         = s3c2440_map_io,
  99                .init_uarts     = s3c244x_init_uarts,
 100                .init           = s3c2440_init,
 101                .name           = name_s3c2440a
 102        },
 103        {
 104                .idcode         = 0x32440aaa,
 105                .idmask         = 0xffffffff,
 106                .map_io         = s3c2442_map_io,
 107                .init_uarts     = s3c244x_init_uarts,
 108                .init           = s3c2442_init,
 109                .name           = name_s3c2442
 110        },
 111        {
 112                .idcode         = 0x32440aab,
 113                .idmask         = 0xffffffff,
 114                .map_io         = s3c2442_map_io,
 115                .init_uarts     = s3c244x_init_uarts,
 116                .init           = s3c2442_init,
 117                .name           = name_s3c2442b
 118        },
 119        {
 120                .idcode         = 0x32412001,
 121                .idmask         = 0xffffffff,
 122                .map_io         = s3c2412_map_io,
 123                .init_uarts     = s3c2412_init_uarts,
 124                .init           = s3c2412_init,
 125                .name           = name_s3c2412,
 126        },
 127        {                       /* a newer version of the s3c2412 */
 128                .idcode         = 0x32412003,
 129                .idmask         = 0xffffffff,
 130                .map_io         = s3c2412_map_io,
 131                .init_uarts     = s3c2412_init_uarts,
 132                .init           = s3c2412_init,
 133                .name           = name_s3c2412,
 134        },
 135        {                       /* a strange version of the s3c2416 */
 136                .idcode         = 0x32450003,
 137                .idmask         = 0xffffffff,
 138                .map_io         = s3c2416_map_io,
 139                .init_uarts     = s3c2416_init_uarts,
 140                .init           = s3c2416_init,
 141                .name           = name_s3c2416,
 142        },
 143        {
 144                .idcode         = 0x32443001,
 145                .idmask         = 0xffffffff,
 146                .map_io         = s3c2443_map_io,
 147                .init_uarts     = s3c2443_init_uarts,
 148                .init           = s3c2443_init,
 149                .name           = name_s3c2443,
 150        },
 151};
 152
 153/* minimal IO mapping */
 154
 155static struct map_desc s3c_iodesc[] __initdata = {
 156        IODESC_ENT(GPIO),
 157        IODESC_ENT(IRQ),
 158        IODESC_ENT(MEMCTRL),
 159        IODESC_ENT(UART)
 160};
 161
 162/* read cpu identificaiton code */
 163
 164static unsigned long s3c24xx_read_idcode_v5(void)
 165{
 166#if defined(CONFIG_CPU_S3C2416)
 167        /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
 168
 169        u32 gs = __raw_readl(S3C24XX_GSTATUS1);
 170
 171        /* test for s3c2416 or similar device */
 172        if ((gs >> 16) == 0x3245)
 173                return gs;
 174#endif
 175
 176#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 177        return __raw_readl(S3C2412_GSTATUS1);
 178#else
 179        return 1UL;     /* don't look like an 2400 */
 180#endif
 181}
 182
 183static unsigned long s3c24xx_read_idcode_v4(void)
 184{
 185        return __raw_readl(S3C2410_GSTATUS1);
 186}
 187
 188static void s3c24xx_default_idle(void)
 189{
 190        unsigned long tmp = 0;
 191        int i;
 192
 193        /* idle the system by using the idle mode which will wait for an
 194         * interrupt to happen before restarting the system.
 195         */
 196
 197        /* Warning: going into idle state upsets jtag scanning */
 198
 199        __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
 200                     S3C2410_CLKCON);
 201
 202        /* the samsung port seems to do a loop and then unset idle.. */
 203        for (i = 0; i < 50; i++)
 204                tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
 205
 206        /* this bit is not cleared on re-start... */
 207
 208        __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
 209                     S3C2410_CLKCON);
 210}
 211
 212static struct samsung_pwm_variant s3c24xx_pwm_variant = {
 213        .bits           = 16,
 214        .div_base       = 1,
 215        .has_tint_cstat = false,
 216        .tclk_mask      = (1 << 4),
 217};
 218
 219void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 220{
 221        arm_pm_idle = s3c24xx_default_idle;
 222
 223        /* initialise the io descriptors we need for initialisation */
 224        iotable_init(mach_desc, size);
 225        iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 226
 227        if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 228                samsung_cpu_id = s3c24xx_read_idcode_v5();
 229        } else {
 230                samsung_cpu_id = s3c24xx_read_idcode_v4();
 231        }
 232
 233        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 234
 235        samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
 236}
 237
 238void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 239{
 240        s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 241        s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 242}
 243
 244void __init samsung_timer_init(void)
 245{
 246        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 247                IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
 248        };
 249
 250        samsung_pwm_clocksource_init(S3C_VA_TIMER,
 251                                        timer_irqs, &s3c24xx_pwm_variant);
 252}
 253
 254/* Serial port registrations */
 255
 256#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 257#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
 258#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
 259#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
 260
 261static struct resource s3c2410_uart0_resource[] = {
 262        [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
 263        [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
 264                        IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
 265                        NULL, IORESOURCE_IRQ)
 266};
 267
 268static struct resource s3c2410_uart1_resource[] = {
 269        [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
 270        [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
 271                        IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
 272                        NULL, IORESOURCE_IRQ)
 273};
 274
 275static struct resource s3c2410_uart2_resource[] = {
 276        [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
 277        [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
 278                        IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
 279                        NULL, IORESOURCE_IRQ)
 280};
 281
 282static struct resource s3c2410_uart3_resource[] = {
 283        [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
 284        [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
 285                        IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
 286                        NULL, IORESOURCE_IRQ)
 287};
 288
 289struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
 290        [0] = {
 291                .resources      = s3c2410_uart0_resource,
 292                .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
 293        },
 294        [1] = {
 295                .resources      = s3c2410_uart1_resource,
 296                .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
 297        },
 298        [2] = {
 299                .resources      = s3c2410_uart2_resource,
 300                .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
 301        },
 302        [3] = {
 303                .resources      = s3c2410_uart3_resource,
 304                .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
 305        },
 306};
 307
 308#define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
 309
 310#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
 311        defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 312static struct resource s3c2410_dma_resource[] = {
 313        [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 314        [1] = DEFINE_RES_IRQ(IRQ_DMA0),
 315        [2] = DEFINE_RES_IRQ(IRQ_DMA1),
 316        [3] = DEFINE_RES_IRQ(IRQ_DMA2),
 317        [4] = DEFINE_RES_IRQ(IRQ_DMA3),
 318};
 319#endif
 320
 321#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
 322static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
 323        [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 324        [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 325        [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 326                                                S3C24XX_DMA_CHANREQ(2, 2) |
 327                                                S3C24XX_DMA_CHANREQ(1, 3),
 328        },
 329        [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 330        [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 331        [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 332        [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 333        [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 334        [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 335                                                 S3C24XX_DMA_CHANREQ(3, 2) |
 336                                                 S3C24XX_DMA_CHANREQ(3, 3),
 337        },
 338        [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 339                                                  S3C24XX_DMA_CHANREQ(1, 2),
 340        },
 341        [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
 342        [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 343        [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 344        [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 345        [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 346};
 347
 348static const struct dma_slave_map s3c2410_dma_slave_map[] = {
 349        { "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI },
 350        { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX },
 351        { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX },
 352        { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX },
 353        { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX },
 354        /*
 355         * The DMA request source[1] (DMACH_UARTx_SRC2) are
 356         * not used in the UART driver.
 357         */
 358        { "s3c2410-uart.0", "rx", (void *)DMACH_UART0 },
 359        { "s3c2410-uart.0", "tx", (void *)DMACH_UART0 },
 360        { "s3c2410-uart.1", "rx", (void *)DMACH_UART1 },
 361        { "s3c2410-uart.1", "tx", (void *)DMACH_UART1 },
 362        { "s3c2410-uart.2", "rx", (void *)DMACH_UART2 },
 363        { "s3c2410-uart.2", "tx", (void *)DMACH_UART2 },
 364        { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
 365        { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
 366        { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
 367        { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
 368        { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
 369        { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
 370        { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
 371        { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
 372        { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
 373        { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
 374};
 375
 376static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
 377        .num_phy_channels = 4,
 378        .channels = s3c2410_dma_channels,
 379        .num_channels = DMACH_MAX,
 380        .slave_map = s3c2410_dma_slave_map,
 381        .slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map),
 382};
 383
 384struct platform_device s3c2410_device_dma = {
 385        .name           = "s3c2410-dma",
 386        .id             = 0,
 387        .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 388        .resource       = s3c2410_dma_resource,
 389        .dev    = {
 390                .dma_mask = &s3c24xx_device_dma_mask,
 391                .coherent_dma_mask = DMA_BIT_MASK(32),
 392                .platform_data = &s3c2410_dma_platdata,
 393        },
 394};
 395#endif
 396
 397#ifdef CONFIG_CPU_S3C2412
 398static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
 399        [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 400        [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 401        [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 402        [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 403        [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 404        [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 405        [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 406        [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 407        [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 408        [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 409        [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 410        [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 411        [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 412        [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 413        [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 414        [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 415        [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
 416        [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
 417        [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
 418        [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
 419};
 420
 421static const struct dma_slave_map s3c2412_dma_slave_map[] = {
 422        { "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI },
 423        { "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX },
 424        { "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX },
 425        { "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX },
 426        { "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX },
 427        { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
 428        { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
 429        { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
 430        { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
 431        { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
 432        { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
 433        { "s3c2412-iis", "rx", (void *)DMACH_I2S_IN },
 434        { "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT },
 435        { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
 436        { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
 437        { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
 438        { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
 439        { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
 440        { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
 441        { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
 442        { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
 443};
 444
 445static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
 446        .num_phy_channels = 4,
 447        .channels = s3c2412_dma_channels,
 448        .num_channels = DMACH_MAX,
 449        .slave_map = s3c2412_dma_slave_map,
 450        .slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map),
 451};
 452
 453struct platform_device s3c2412_device_dma = {
 454        .name           = "s3c2412-dma",
 455        .id             = 0,
 456        .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 457        .resource       = s3c2410_dma_resource,
 458        .dev    = {
 459                .dma_mask = &s3c24xx_device_dma_mask,
 460                .coherent_dma_mask = DMA_BIT_MASK(32),
 461                .platform_data = &s3c2412_dma_platdata,
 462        },
 463};
 464#endif
 465
 466#if defined(CONFIG_CPU_S3C2440)
 467static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
 468        [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 469        [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 470        [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 471                                                S3C24XX_DMA_CHANREQ(6, 1) |
 472                                                S3C24XX_DMA_CHANREQ(2, 2) |
 473                                                S3C24XX_DMA_CHANREQ(1, 3),
 474        },
 475        [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 476        [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 477        [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 478        [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 479        [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 480        [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 481                                                 S3C24XX_DMA_CHANREQ(3, 2) |
 482                                                 S3C24XX_DMA_CHANREQ(3, 3),
 483        },
 484        [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 485                                                  S3C24XX_DMA_CHANREQ(1, 2),
 486        },
 487        [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
 488                                                   S3C24XX_DMA_CHANREQ(0, 2),
 489        },
 490        [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
 491                                                  S3C24XX_DMA_CHANREQ(5, 2),
 492        },
 493        [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
 494                                                  S3C24XX_DMA_CHANREQ(6, 3),
 495        },
 496        [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
 497                                                  S3C24XX_DMA_CHANREQ(5, 3),
 498        },
 499        [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 500        [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 501        [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 502        [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 503};
 504
 505static const struct dma_slave_map s3c2440_dma_slave_map[] = {
 506        /* TODO: DMACH_XD0 */
 507        /* TODO: DMACH_XD1 */
 508        { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
 509        { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
 510        { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
 511        { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
 512        { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
 513        { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
 514        { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
 515        { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
 516        { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
 517        { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
 518        { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
 519        { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
 520        { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
 521        /* TODO: DMACH_TIMER */
 522        { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
 523        { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
 524        { "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
 525        { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
 526        { "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
 527        { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
 528        { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
 529        { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
 530        { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
 531        { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
 532        { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
 533        { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
 534        { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
 535};
 536
 537static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
 538        .num_phy_channels = 4,
 539        .channels = s3c2440_dma_channels,
 540        .num_channels = DMACH_MAX,
 541        .slave_map = s3c2440_dma_slave_map,
 542        .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
 543};
 544
 545struct platform_device s3c2440_device_dma = {
 546        .name           = "s3c2410-dma",
 547        .id             = 0,
 548        .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 549        .resource       = s3c2410_dma_resource,
 550        .dev    = {
 551                .dma_mask = &s3c24xx_device_dma_mask,
 552                .coherent_dma_mask = DMA_BIT_MASK(32),
 553                .platform_data = &s3c2440_dma_platdata,
 554        },
 555};
 556#endif
 557
 558#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 559static struct resource s3c2443_dma_resource[] = {
 560        [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 561        [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
 562        [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
 563        [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
 564        [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
 565        [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
 566        [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
 567};
 568
 569static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
 570        [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 571        [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 572        [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 573        [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 574        [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 575        [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 576        [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 577        [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 578        [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 579        [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 580        [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
 581        [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 582        [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 583        [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 584        [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
 585        [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 586        [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 587        [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 588        [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
 589        [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
 590        [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
 591};
 592
 593static const struct dma_slave_map s3c2443_dma_slave_map[] = {
 594        { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
 595        { "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX },
 596        { "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX },
 597        { "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX },
 598        { "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX },
 599        { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
 600        { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
 601        { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
 602        { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
 603        { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
 604        { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
 605        { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
 606        { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
 607        { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
 608        { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
 609};
 610
 611static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
 612        .num_phy_channels = 6,
 613        .channels = s3c2443_dma_channels,
 614        .num_channels = DMACH_MAX,
 615        .slave_map = s3c2443_dma_slave_map,
 616        .slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map),
 617};
 618
 619struct platform_device s3c2443_device_dma = {
 620        .name           = "s3c2443-dma",
 621        .id             = 0,
 622        .num_resources  = ARRAY_SIZE(s3c2443_dma_resource),
 623        .resource       = s3c2443_dma_resource,
 624        .dev    = {
 625                .dma_mask = &s3c24xx_device_dma_mask,
 626                .coherent_dma_mask = DMA_BIT_MASK(32),
 627                .platform_data = &s3c2443_dma_platdata,
 628        },
 629};
 630#endif
 631
 632#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
 633void __init s3c2410_init_clocks(int xtal)
 634{
 635        s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 636}
 637#endif
 638
 639#ifdef CONFIG_CPU_S3C2412
 640void __init s3c2412_init_clocks(int xtal)
 641{
 642        s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 643}
 644#endif
 645
 646#ifdef CONFIG_CPU_S3C2416
 647void __init s3c2416_init_clocks(int xtal)
 648{
 649        s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 650}
 651#endif
 652
 653#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
 654void __init s3c2440_init_clocks(int xtal)
 655{
 656        s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 657}
 658#endif
 659
 660#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
 661void __init s3c2442_init_clocks(int xtal)
 662{
 663        s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
 664}
 665#endif
 666
 667#ifdef CONFIG_CPU_S3C2443
 668void __init s3c2443_init_clocks(int xtal)
 669{
 670        s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 671}
 672#endif
 673
 674#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
 675        defined(CONFIG_CPU_S3C2442)
 676static struct resource s3c2410_dclk_resource[] = {
 677        [0] = DEFINE_RES_MEM(0x56000084, 0x4),
 678};
 679
 680struct platform_device s3c2410_device_dclk = {
 681        .name           = "s3c2410-dclk",
 682        .id             = 0,
 683        .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
 684        .resource       = s3c2410_dclk_resource,
 685};
 686#endif
 687