1/* arch/arm/mach-s3c2410/include/mach/regs-lcd.h 2 * 3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9*/ 10 11 12#ifndef ___ASM_ARCH_REGS_LCD_H 13#define ___ASM_ARCH_REGS_LCD_H 14 15#define S3C2410_LCDREG(x) (x) 16 17/* LCD control registers */ 18#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) 19#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) 20#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) 21#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) 22#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) 23 24#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) 25#define S3C2410_LCDCON1_MMODE (1<<7) 26#define S3C2410_LCDCON1_DSCAN4 (0<<5) 27#define S3C2410_LCDCON1_STN4 (1<<5) 28#define S3C2410_LCDCON1_STN8 (2<<5) 29#define S3C2410_LCDCON1_TFT (3<<5) 30 31#define S3C2410_LCDCON1_STN1BPP (0<<1) 32#define S3C2410_LCDCON1_STN2GREY (1<<1) 33#define S3C2410_LCDCON1_STN4GREY (2<<1) 34#define S3C2410_LCDCON1_STN8BPP (3<<1) 35#define S3C2410_LCDCON1_STN12BPP (4<<1) 36 37#define S3C2410_LCDCON1_TFT1BPP (8<<1) 38#define S3C2410_LCDCON1_TFT2BPP (9<<1) 39#define S3C2410_LCDCON1_TFT4BPP (10<<1) 40#define S3C2410_LCDCON1_TFT8BPP (11<<1) 41#define S3C2410_LCDCON1_TFT16BPP (12<<1) 42#define S3C2410_LCDCON1_TFT24BPP (13<<1) 43 44#define S3C2410_LCDCON1_ENVID (1) 45 46#define S3C2410_LCDCON1_MODEMASK 0x1E 47 48#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) 49#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) 50#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) 51#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) 52 53#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) 54#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) 55#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) 56 57#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) 58#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) 59#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) 60#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) 61#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) 62 63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) 64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) 65 66/* LDCCON4 changes for STN mode on the S3C2412 */ 67 68#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) 69#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) 70#define S3C2410_LCDCON4_WLH(x) ((x) << 0) 71 72#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) 73 74#define S3C2410_LCDCON5_BPP24BL (1<<12) 75#define S3C2410_LCDCON5_FRM565 (1<<11) 76#define S3C2410_LCDCON5_INVVCLK (1<<10) 77#define S3C2410_LCDCON5_INVVLINE (1<<9) 78#define S3C2410_LCDCON5_INVVFRAME (1<<8) 79#define S3C2410_LCDCON5_INVVD (1<<7) 80#define S3C2410_LCDCON5_INVVDEN (1<<6) 81#define S3C2410_LCDCON5_INVPWREN (1<<5) 82#define S3C2410_LCDCON5_INVLEND (1<<4) 83#define S3C2410_LCDCON5_PWREN (1<<3) 84#define S3C2410_LCDCON5_ENLEND (1<<2) 85#define S3C2410_LCDCON5_BSWP (1<<1) 86#define S3C2410_LCDCON5_HWSWP (1<<0) 87 88/* framebuffer start addressed */ 89#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) 90#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) 91#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) 92 93#define S3C2410_LCDBANK(x) ((x) << 21) 94#define S3C2410_LCDBASEU(x) (x) 95 96#define S3C2410_OFFSIZE(x) ((x) << 11) 97#define S3C2410_PAGEWIDTH(x) (x) 98 99/* colour lookup and miscellaneous controls */ 100 101#define S3C2410_REDLUT S3C2410_LCDREG(0x20) 102#define S3C2410_GREENLUT S3C2410_LCDREG(0x24) 103#define S3C2410_BLUELUT S3C2410_LCDREG(0x28) 104 105#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) 106#define S3C2410_TPAL S3C2410_LCDREG(0x50) 107 108#define S3C2410_TPAL_EN (1<<24) 109 110/* interrupt info */ 111#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) 112#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) 113#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) 114#define S3C2410_LCDINT_FIWSEL (1<<2) 115#define S3C2410_LCDINT_FRSYNC (1<<1) 116#define S3C2410_LCDINT_FICNT (1<<0) 117 118/* s3c2442 extra stn registers */ 119 120#define S3C2442_REDLUT S3C2410_LCDREG(0x20) 121#define S3C2442_GREENLUT S3C2410_LCDREG(0x24) 122#define S3C2442_BLUELUT S3C2410_LCDREG(0x28) 123#define S3C2442_DITHMODE S3C2410_LCDREG(0x20) 124 125#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) 126 127#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) 128 129/* S3C2412 registers */ 130 131#define S3C2412_TPAL S3C2410_LCDREG(0x20) 132 133#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) 134#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) 135#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) 136 137#define S3C2412_TCONSEL S3C2410_LCDREG(0x30) 138 139#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) 140#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) 141#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) 142#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) 143 144#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) 145#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) 146#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) 147 148#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) 149 150/* general registers */ 151 152/* base of the LCD registers, where INTPND, INTSRC and then INTMSK 153 * are available. */ 154 155#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54) 156#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24) 157 158#define S3C24XX_LCDINTPND (0x00) 159#define S3C24XX_LCDSRCPND (0x04) 160#define S3C24XX_LCDINTMSK (0x08) 161 162#endif /* ___ASM_ARCH_REGS_LCD_H */ 163