1comment "Processor Type"
2
3
4
5
6
7
8config CPU_ARM7TDMI
9 bool
10 depends on !MMU
11 select CPU_32v4T
12 select CPU_ABRT_LV4T
13 select CPU_CACHE_V4
14 select CPU_PABRT_LEGACY
15 help
16 A 32-bit RISC microprocessor based on the ARM7 processor core
17 which has no memory control unit and cache.
18
19 Say Y if you want support for the ARM7TDMI processor.
20 Otherwise, say N.
21
22
23config CPU_ARM720T
24 bool
25 select CPU_32v4T
26 select CPU_ABRT_LV4T
27 select CPU_CACHE_V4
28 select CPU_CACHE_VIVT
29 select CPU_COPY_V4WT if MMU
30 select CPU_CP15_MMU
31 select CPU_PABRT_LEGACY
32 select CPU_THUMB_CAPABLE
33 select CPU_TLB_V4WT if MMU
34 help
35 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
36 MMU built around an ARM7TDMI core.
37
38 Say Y if you want support for the ARM720T processor.
39 Otherwise, say N.
40
41
42config CPU_ARM740T
43 bool
44 depends on !MMU
45 select CPU_32v4T
46 select CPU_ABRT_LV4T
47 select CPU_CACHE_V4
48 select CPU_CP15_MPU
49 select CPU_PABRT_LEGACY
50 select CPU_THUMB_CAPABLE
51 help
52 A 32-bit RISC processor with 8KB cache or 4KB variants,
53 write buffer and MPU(Protection Unit) built around
54 an ARM7TDMI core.
55
56 Say Y if you want support for the ARM740T processor.
57 Otherwise, say N.
58
59
60config CPU_ARM9TDMI
61 bool
62 depends on !MMU
63 select CPU_32v4T
64 select CPU_ABRT_NOMMU
65 select CPU_CACHE_V4
66 select CPU_PABRT_LEGACY
67 help
68 A 32-bit RISC microprocessor based on the ARM9 processor core
69 which has no memory control unit and cache.
70
71 Say Y if you want support for the ARM9TDMI processor.
72 Otherwise, say N.
73
74
75config CPU_ARM920T
76 bool
77 select CPU_32v4T
78 select CPU_ABRT_EV4T
79 select CPU_CACHE_V4WT
80 select CPU_CACHE_VIVT
81 select CPU_COPY_V4WB if MMU
82 select CPU_CP15_MMU
83 select CPU_PABRT_LEGACY
84 select CPU_THUMB_CAPABLE
85 select CPU_TLB_V4WBI if MMU
86 help
87 The ARM920T is licensed to be produced by numerous vendors,
88 and is used in the Cirrus EP93xx and the Samsung S3C2410.
89
90 Say Y if you want support for the ARM920T processor.
91 Otherwise, say N.
92
93
94config CPU_ARM922T
95 bool
96 select CPU_32v4T
97 select CPU_ABRT_EV4T
98 select CPU_CACHE_V4WT
99 select CPU_CACHE_VIVT
100 select CPU_COPY_V4WB if MMU
101 select CPU_CP15_MMU
102 select CPU_PABRT_LEGACY
103 select CPU_THUMB_CAPABLE
104 select CPU_TLB_V4WBI if MMU
105 help
106 The ARM922T is a version of the ARM920T, but with smaller
107 instruction and data caches. It is used in Altera's
108 Excalibur XA device family and Micrel's KS8695 Centaur.
109
110 Say Y if you want support for the ARM922T processor.
111 Otherwise, say N.
112
113
114config CPU_ARM925T
115 bool
116 select CPU_32v4T
117 select CPU_ABRT_EV4T
118 select CPU_CACHE_V4WT
119 select CPU_CACHE_VIVT
120 select CPU_COPY_V4WB if MMU
121 select CPU_CP15_MMU
122 select CPU_PABRT_LEGACY
123 select CPU_THUMB_CAPABLE
124 select CPU_TLB_V4WBI if MMU
125 help
126 The ARM925T is a mix between the ARM920T and ARM926T, but with
127 different instruction and data caches. It is used in TI's OMAP
128 device family.
129
130 Say Y if you want support for the ARM925T processor.
131 Otherwise, say N.
132
133
134config CPU_ARM926T
135 bool
136 select CPU_32v5
137 select CPU_ABRT_EV5TJ
138 select CPU_CACHE_VIVT
139 select CPU_COPY_V4WB if MMU
140 select CPU_CP15_MMU
141 select CPU_PABRT_LEGACY
142 select CPU_THUMB_CAPABLE
143 select CPU_TLB_V4WBI if MMU
144 help
145 This is a variant of the ARM920. It has slightly different
146 instruction sequences for cache and TLB operations. Curiously,
147 there is no documentation on it at the ARM corporate website.
148
149 Say Y if you want support for the ARM926T processor.
150 Otherwise, say N.
151
152
153config CPU_FA526
154 bool
155 select CPU_32v4
156 select CPU_ABRT_EV4
157 select CPU_CACHE_FA
158 select CPU_CACHE_VIVT
159 select CPU_COPY_FA if MMU
160 select CPU_CP15_MMU
161 select CPU_PABRT_LEGACY
162 select CPU_TLB_FA if MMU
163 help
164 The FA526 is a version of the ARMv4 compatible processor with
165 Branch Target Buffer, Unified TLB and cache line size 16.
166
167 Say Y if you want support for the FA526 processor.
168 Otherwise, say N.
169
170
171config CPU_ARM940T
172 bool
173 depends on !MMU
174 select CPU_32v4T
175 select CPU_ABRT_NOMMU
176 select CPU_CACHE_VIVT
177 select CPU_CP15_MPU
178 select CPU_PABRT_LEGACY
179 select CPU_THUMB_CAPABLE
180 help
181 ARM940T is a member of the ARM9TDMI family of general-
182 purpose microprocessors with MPU and separate 4KB
183 instruction and 4KB data cases, each with a 4-word line
184 length.
185
186 Say Y if you want support for the ARM940T processor.
187 Otherwise, say N.
188
189
190config CPU_ARM946E
191 bool
192 depends on !MMU
193 select CPU_32v5
194 select CPU_ABRT_NOMMU
195 select CPU_CACHE_VIVT
196 select CPU_CP15_MPU
197 select CPU_PABRT_LEGACY
198 select CPU_THUMB_CAPABLE
199 help
200 ARM946E-S is a member of the ARM9E-S family of high-
201 performance, 32-bit system-on-chip processor solutions.
202 The TCM and ARMv5TE 32-bit instruction set is supported.
203
204 Say Y if you want support for the ARM946E-S processor.
205 Otherwise, say N.
206
207
208config CPU_ARM1020
209 bool
210 select CPU_32v5
211 select CPU_ABRT_EV4T
212 select CPU_CACHE_V4WT
213 select CPU_CACHE_VIVT
214 select CPU_COPY_V4WB if MMU
215 select CPU_CP15_MMU
216 select CPU_PABRT_LEGACY
217 select CPU_THUMB_CAPABLE
218 select CPU_TLB_V4WBI if MMU
219 help
220 The ARM1020 is the 32K cached version of the ARM10 processor,
221 with an addition of a floating-point unit.
222
223 Say Y if you want support for the ARM1020 processor.
224 Otherwise, say N.
225
226
227config CPU_ARM1020E
228 bool
229 depends on n
230 select CPU_32v5
231 select CPU_ABRT_EV4T
232 select CPU_CACHE_V4WT
233 select CPU_CACHE_VIVT
234 select CPU_COPY_V4WB if MMU
235 select CPU_CP15_MMU
236 select CPU_PABRT_LEGACY
237 select CPU_THUMB_CAPABLE
238 select CPU_TLB_V4WBI if MMU
239
240
241config CPU_ARM1022
242 bool
243 select CPU_32v5
244 select CPU_ABRT_EV4T
245 select CPU_CACHE_VIVT
246 select CPU_COPY_V4WB if MMU
247 select CPU_CP15_MMU
248 select CPU_PABRT_LEGACY
249 select CPU_THUMB_CAPABLE
250 select CPU_TLB_V4WBI if MMU
251 help
252 The ARM1022E is an implementation of the ARMv5TE architecture
253 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
254 embedded trace macrocell, and a floating-point unit.
255
256 Say Y if you want support for the ARM1022E processor.
257 Otherwise, say N.
258
259
260config CPU_ARM1026
261 bool
262 select CPU_32v5
263 select CPU_ABRT_EV5T
264 select CPU_CACHE_VIVT
265 select CPU_COPY_V4WB if MMU
266 select CPU_CP15_MMU
267 select CPU_PABRT_LEGACY
268 select CPU_THUMB_CAPABLE
269 select CPU_TLB_V4WBI if MMU
270 help
271 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
272 based upon the ARM10 integer core.
273
274 Say Y if you want support for the ARM1026EJ-S processor.
275 Otherwise, say N.
276
277
278config CPU_SA110
279 bool
280 select CPU_32v3 if ARCH_RPC
281 select CPU_32v4 if !ARCH_RPC
282 select CPU_ABRT_EV4
283 select CPU_CACHE_V4WB
284 select CPU_CACHE_VIVT
285 select CPU_COPY_V4WB if MMU
286 select CPU_CP15_MMU
287 select CPU_PABRT_LEGACY
288 select CPU_TLB_V4WB if MMU
289 help
290 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
291 is available at five speeds ranging from 100 MHz to 233 MHz.
292 More information is available at
293 <http://developer.intel.com/design/strong/sa110.htm>.
294
295 Say Y if you want support for the SA-110 processor.
296 Otherwise, say N.
297
298
299config CPU_SA1100
300 bool
301 select CPU_32v4
302 select CPU_ABRT_EV4
303 select CPU_CACHE_V4WB
304 select CPU_CACHE_VIVT
305 select CPU_CP15_MMU
306 select CPU_PABRT_LEGACY
307 select CPU_TLB_V4WB if MMU
308
309
310config CPU_XSCALE
311 bool
312 select CPU_32v5
313 select CPU_ABRT_EV5T
314 select CPU_CACHE_VIVT
315 select CPU_CP15_MMU
316 select CPU_PABRT_LEGACY
317 select CPU_THUMB_CAPABLE
318 select CPU_TLB_V4WBI if MMU
319
320
321config CPU_XSC3
322 bool
323 select CPU_32v5
324 select CPU_ABRT_EV5T
325 select CPU_CACHE_VIVT
326 select CPU_CP15_MMU
327 select CPU_PABRT_LEGACY
328 select CPU_THUMB_CAPABLE
329 select CPU_TLB_V4WBI if MMU
330 select IO_36
331
332
333config CPU_MOHAWK
334 bool
335 select CPU_32v5
336 select CPU_ABRT_EV5T
337 select CPU_CACHE_VIVT
338 select CPU_COPY_V4WB if MMU
339 select CPU_CP15_MMU
340 select CPU_PABRT_LEGACY
341 select CPU_THUMB_CAPABLE
342 select CPU_TLB_V4WBI if MMU
343
344
345config CPU_FEROCEON
346 bool
347 select CPU_32v5
348 select CPU_ABRT_EV5T
349 select CPU_CACHE_VIVT
350 select CPU_COPY_FEROCEON if MMU
351 select CPU_CP15_MMU
352 select CPU_PABRT_LEGACY
353 select CPU_THUMB_CAPABLE
354 select CPU_TLB_FEROCEON if MMU
355
356config CPU_FEROCEON_OLD_ID
357 bool "Accept early Feroceon cores with an ARM926 ID"
358 depends on CPU_FEROCEON && !CPU_ARM926T
359 default y
360 help
361 This enables the usage of some old Feroceon cores
362 for which the CPU ID is equal to the ARM926 ID.
363 Relevant for Feroceon-1850 and early Feroceon-2850.
364
365
366config CPU_PJ4
367 bool
368 select ARM_THUMBEE
369 select CPU_V7
370
371config CPU_PJ4B
372 bool
373 select CPU_V7
374
375
376config CPU_V6
377 bool
378 select CPU_32v6
379 select CPU_ABRT_EV6
380 select CPU_CACHE_V6
381 select CPU_CACHE_VIPT
382 select CPU_COPY_V6 if MMU
383 select CPU_CP15_MMU
384 select CPU_HAS_ASID if MMU
385 select CPU_PABRT_V6
386 select CPU_THUMB_CAPABLE
387 select CPU_TLB_V6 if MMU
388
389
390config CPU_V6K
391 bool
392 select CPU_32v6
393 select CPU_32v6K
394 select CPU_ABRT_EV6
395 select CPU_CACHE_V6
396 select CPU_CACHE_VIPT
397 select CPU_COPY_V6 if MMU
398 select CPU_CP15_MMU
399 select CPU_HAS_ASID if MMU
400 select CPU_PABRT_V6
401 select CPU_THUMB_CAPABLE
402 select CPU_TLB_V6 if MMU
403
404
405config CPU_V7
406 bool
407 select CPU_32v6K
408 select CPU_32v7
409 select CPU_ABRT_EV7
410 select CPU_CACHE_V7
411 select CPU_CACHE_VIPT
412 select CPU_COPY_V6 if MMU
413 select CPU_CP15_MMU if MMU
414 select CPU_CP15_MPU if !MMU
415 select CPU_HAS_ASID if MMU
416 select CPU_PABRT_V7
417 select CPU_THUMB_CAPABLE
418 select CPU_TLB_V7 if MMU
419
420
421config CPU_V7M
422 bool
423 select CPU_32v7M
424 select CPU_ABRT_NOMMU
425 select CPU_CACHE_V7M
426 select CPU_CACHE_NOP
427 select CPU_PABRT_LEGACY
428 select CPU_THUMBONLY
429
430config CPU_THUMBONLY
431 bool
432 select CPU_THUMB_CAPABLE
433
434 depends on !MMU
435 help
436 Select this if your CPU doesn't support the 32 bit ARM instructions.
437
438config CPU_THUMB_CAPABLE
439 bool
440 help
441 Select this if your CPU can support Thumb mode.
442
443
444
445config CPU_32v3
446 bool
447 select CPU_USE_DOMAINS if MMU
448 select NEED_KUSER_HELPERS
449 select TLS_REG_EMUL if SMP || !MMU
450 select CPU_NO_EFFICIENT_FFS
451
452config CPU_32v4
453 bool
454 select CPU_USE_DOMAINS if MMU
455 select NEED_KUSER_HELPERS
456 select TLS_REG_EMUL if SMP || !MMU
457 select CPU_NO_EFFICIENT_FFS
458
459config CPU_32v4T
460 bool
461 select CPU_USE_DOMAINS if MMU
462 select NEED_KUSER_HELPERS
463 select TLS_REG_EMUL if SMP || !MMU
464 select CPU_NO_EFFICIENT_FFS
465
466config CPU_32v5
467 bool
468 select CPU_USE_DOMAINS if MMU
469 select NEED_KUSER_HELPERS
470 select TLS_REG_EMUL if SMP || !MMU
471
472config CPU_32v6
473 bool
474 select TLS_REG_EMUL if !CPU_32v6K && !MMU
475
476config CPU_32v6K
477 bool
478
479config CPU_32v7
480 bool
481
482config CPU_32v7M
483 bool
484
485
486config CPU_ABRT_NOMMU
487 bool
488
489config CPU_ABRT_EV4
490 bool
491
492config CPU_ABRT_EV4T
493 bool
494
495config CPU_ABRT_LV4T
496 bool
497
498config CPU_ABRT_EV5T
499 bool
500
501config CPU_ABRT_EV5TJ
502 bool
503
504config CPU_ABRT_EV6
505 bool
506
507config CPU_ABRT_EV7
508 bool
509
510config CPU_PABRT_LEGACY
511 bool
512
513config CPU_PABRT_V6
514 bool
515
516config CPU_PABRT_V7
517 bool
518
519
520config CPU_CACHE_V4
521 bool
522
523config CPU_CACHE_V4WT
524 bool
525
526config CPU_CACHE_V4WB
527 bool
528
529config CPU_CACHE_V6
530 bool
531
532config CPU_CACHE_V7
533 bool
534
535config CPU_CACHE_NOP
536 bool
537
538config CPU_CACHE_VIVT
539 bool
540
541config CPU_CACHE_VIPT
542 bool
543
544config CPU_CACHE_FA
545 bool
546
547config CPU_CACHE_V7M
548 bool
549
550if MMU
551
552config CPU_COPY_V4WT
553 bool
554
555config CPU_COPY_V4WB
556 bool
557
558config CPU_COPY_FEROCEON
559 bool
560
561config CPU_COPY_FA
562 bool
563
564config CPU_COPY_V6
565 bool
566
567
568config CPU_TLB_V4WT
569 bool
570 help
571 ARM Architecture Version 4 TLB with writethrough cache.
572
573config CPU_TLB_V4WB
574 bool
575 help
576 ARM Architecture Version 4 TLB with writeback cache.
577
578config CPU_TLB_V4WBI
579 bool
580 help
581 ARM Architecture Version 4 TLB with writeback cache and invalidate
582 instruction cache entry.
583
584config CPU_TLB_FEROCEON
585 bool
586 help
587 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
588
589config CPU_TLB_FA
590 bool
591 help
592 Faraday ARM FA526 architecture, unified TLB with writeback cache
593 and invalidate instruction cache entry. Branch target buffer is
594 also supported.
595
596config CPU_TLB_V6
597 bool
598
599config CPU_TLB_V7
600 bool
601
602config VERIFY_PERMISSION_FAULT
603 bool
604endif
605
606config CPU_HAS_ASID
607 bool
608 help
609 This indicates whether the CPU has the ASID register; used to
610 tag TLB and possibly cache entries.
611
612config CPU_CP15
613 bool
614 help
615 Processor has the CP15 register.
616
617config CPU_CP15_MMU
618 bool
619 select CPU_CP15
620 help
621 Processor has the CP15 register, which has MMU related registers.
622
623config CPU_CP15_MPU
624 bool
625 select CPU_CP15
626 help
627 Processor has the CP15 register, which has MPU related registers.
628
629config CPU_USE_DOMAINS
630 bool
631 help
632 This option enables or disables the use of domain switching
633 via the set_fs() function.
634
635config CPU_V7M_NUM_IRQ
636 int "Number of external interrupts connected to the NVIC"
637 depends on CPU_V7M
638 default 90 if ARCH_STM32
639 default 38 if ARCH_EFM32
640 default 112 if SOC_VF610
641 default 240
642 help
643 This option indicates the number of interrupts connected to the NVIC.
644 The value can be larger than the real number of interrupts supported
645 by the system, but must not be lower.
646 The default value is 240, corresponding to the maximum number of
647 interrupts supported by the NVIC on Cortex-M family.
648
649 If unsure, keep default value.
650
651
652
653
654config IO_36
655 bool
656
657comment "Processor Features"
658
659config ARM_LPAE
660 bool "Support for the Large Physical Address Extension"
661 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
662 !CPU_32v4 && !CPU_32v3
663 help
664 Say Y if you have an ARMv7 processor supporting the LPAE page
665 table format and you would like to access memory beyond the
666 4GB limit. The resulting kernel image will not run on
667 processors without the LPA extension.
668
669 If unsure, say N.
670
671config ARM_PV_FIXUP
672 def_bool y
673 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
674
675config ARCH_PHYS_ADDR_T_64BIT
676 def_bool ARM_LPAE
677
678config ARCH_DMA_ADDR_T_64BIT
679 bool
680
681config ARM_THUMB
682 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
683 depends on CPU_THUMB_CAPABLE
684 default y
685 help
686 Say Y if you want to include kernel support for running user space
687 Thumb binaries.
688
689 The Thumb instruction set is a compressed form of the standard ARM
690 instruction set resulting in smaller binaries at the expense of
691 slightly less efficient code.
692
693 If this option is disabled, and you run userspace that switches to
694 Thumb mode, signal handling will not work correctly, resulting in
695 segmentation faults or illegal instruction aborts.
696
697 If you don't know what this all is, saying Y is a safe choice.
698
699config ARM_THUMBEE
700 bool "Enable ThumbEE CPU extension"
701 depends on CPU_V7
702 help
703 Say Y here if you have a CPU with the ThumbEE extension and code to
704 make use of it. Say N for code that can run on CPUs without ThumbEE.
705
706config ARM_VIRT_EXT
707 bool
708 depends on MMU
709 default y if CPU_V7
710 help
711 Enable the kernel to make use of the ARM Virtualization
712 Extensions to install hypervisors without run-time firmware
713 assistance.
714
715 A compliant bootloader is required in order to make maximum
716 use of this feature. Refer to Documentation/arm/Booting for
717 details.
718
719config SWP_EMULATE
720 bool "Emulate SWP/SWPB instructions" if !SMP
721 depends on CPU_V7
722 default y if SMP
723 select HAVE_PROC_CPU if PROC_FS
724 help
725 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
726 ARMv7 multiprocessing extensions introduce the ability to disable
727 these instructions, triggering an undefined instruction exception
728 when executed. Say Y here to enable software emulation of these
729 instructions for userspace (not kernel) using LDREX/STREX.
730 Also creates /proc/cpu/swp_emulation for statistics.
731
732 In some older versions of glibc [<=2.8] SWP is used during futex
733 trylock() operations with the assumption that the code will not
734 be preempted. This invalid assumption may be more likely to fail
735 with SWP emulation enabled, leading to deadlock of the user
736 application.
737
738 NOTE: when accessing uncached shared regions, LDREX/STREX rely
739 on an external transaction monitoring block called a global
740 monitor to maintain update atomicity. If your system does not
741 implement a global monitor, this option can cause programs that
742 perform SWP operations to uncached memory to deadlock.
743
744 If unsure, say Y.
745
746config CPU_BIG_ENDIAN
747 bool "Build big-endian kernel"
748 depends on ARCH_SUPPORTS_BIG_ENDIAN
749 help
750 Say Y if you plan on running a kernel in big-endian mode.
751 Note that your board must be properly built and your board
752 port must properly enable any big-endian related features
753 of your chipset/board/processor.
754
755config CPU_ENDIAN_BE8
756 bool
757 depends on CPU_BIG_ENDIAN
758 default CPU_V6 || CPU_V6K || CPU_V7
759 help
760 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
761
762config CPU_ENDIAN_BE32
763 bool
764 depends on CPU_BIG_ENDIAN
765 default !CPU_ENDIAN_BE8
766 help
767 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
768
769config CPU_HIGH_VECTOR
770 depends on !MMU && CPU_CP15 && !CPU_ARM740T
771 bool "Select the High exception vector"
772 help
773 Say Y here to select high exception vector(0xFFFF0000~).
774 The exception vector can vary depending on the platform
775 design in nommu mode. If your platform needs to select
776 high exception vector, say Y.
777 Otherwise or if you are unsure, say N, and the low exception
778 vector (0x00000000~) will be used.
779
780config CPU_ICACHE_DISABLE
781 bool "Disable I-Cache (I-bit)"
782 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
783 help
784 Say Y here to disable the processor instruction cache. Unless
785 you have a reason not to or are unsure, say N.
786
787config CPU_DCACHE_DISABLE
788 bool "Disable D-Cache (C-bit)"
789 depends on (CPU_CP15 && !SMP) || CPU_V7M
790 help
791 Say Y here to disable the processor data cache. Unless
792 you have a reason not to or are unsure, say N.
793
794config CPU_DCACHE_SIZE
795 hex
796 depends on CPU_ARM740T || CPU_ARM946E
797 default 0x00001000 if CPU_ARM740T
798 default 0x00002000
799 help
800 Some cores are synthesizable to have various sized cache. For
801 ARM946E-S case, it can vary from 0KB to 1MB.
802 To support such cache operations, it is efficient to know the size
803 before compile time.
804 If your SoC is configured to have a different size, define the value
805 here with proper conditions.
806
807config CPU_DCACHE_WRITETHROUGH
808 bool "Force write through D-cache"
809 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
810 default y if CPU_ARM925T
811 help
812 Say Y here to use the data cache in writethrough mode. Unless you
813 specifically require this or are unsure, say N.
814
815config CPU_CACHE_ROUND_ROBIN
816 bool "Round robin I and D cache replacement algorithm"
817 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
818 help
819 Say Y here to use the predictable round-robin cache replacement
820 policy. Unless you specifically require this or are unsure, say N.
821
822config CPU_BPREDICT_DISABLE
823 bool "Disable branch prediction"
824 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
825 help
826 Say Y here to disable branch prediction. If unsure, say N.
827
828config TLS_REG_EMUL
829 bool
830 select NEED_KUSER_HELPERS
831 help
832 An SMP system using a pre-ARMv6 processor (there are apparently
833 a few prototypes like that in existence) and therefore access to
834 that required register must be emulated.
835
836config NEED_KUSER_HELPERS
837 bool
838
839config KUSER_HELPERS
840 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
841 depends on MMU
842 default y
843 help
844 Warning: disabling this option may break user programs.
845
846 Provide kuser helpers in the vector page. The kernel provides
847 helper code to userspace in read only form at a fixed location
848 in the high vector page to allow userspace to be independent of
849 the CPU type fitted to the system. This permits binaries to be
850 run on ARMv4 through to ARMv7 without modification.
851
852 See Documentation/arm/kernel_user_helpers.txt for details.
853
854 However, the fixed address nature of these helpers can be used
855 by ROP (return orientated programming) authors when creating
856 exploits.
857
858 If all of the binaries and libraries which run on your platform
859 are built specifically for your platform, and make no use of
860 these helpers, then you can turn this option off to hinder
861 such exploits. However, in that case, if a binary or library
862 relying on those helpers is run, it will receive a SIGILL signal,
863 which will terminate the program.
864
865 Say N here only if you are absolutely certain that you do not
866 need these helpers; otherwise, the safe option is to say Y.
867
868config VDSO
869 bool "Enable VDSO for acceleration of some system calls"
870 depends on AEABI && MMU && CPU_V7
871 default y if ARM_ARCH_TIMER
872 select GENERIC_TIME_VSYSCALL
873 help
874 Place in the process address space an ELF shared object
875 providing fast implementations of gettimeofday and
876 clock_gettime. Systems that implement the ARM architected
877 timer will receive maximum benefit.
878
879 You must have glibc 2.22 or later for programs to seamlessly
880 take advantage of this.
881
882config DMA_CACHE_RWFO
883 bool "Enable read/write for ownership DMA cache maintenance"
884 depends on CPU_V6K && SMP
885 default y
886 help
887 The Snoop Control Unit on ARM11MPCore does not detect the
888 cache maintenance operations and the dma_{map,unmap}_area()
889 functions may leave stale cache entries on other CPUs. By
890 enabling this option, Read or Write For Ownership in the ARMv6
891 DMA cache maintenance functions is performed. These LDR/STR
892 instructions change the cache line state to shared or modified
893 so that the cache operation has the desired effect.
894
895 Note that the workaround is only valid on processors that do
896 not perform speculative loads into the D-cache. For such
897 processors, if cache maintenance operations are not broadcast
898 in hardware, other workarounds are needed (e.g. cache
899 maintenance broadcasting in software via FIQ).
900
901config OUTER_CACHE
902 bool
903
904config OUTER_CACHE_SYNC
905 bool
906 select ARM_HEAVY_MB
907 help
908 The outer cache has a outer_cache_fns.sync function pointer
909 that can be used to drain the write buffer of the outer cache.
910
911config CACHE_FEROCEON_L2
912 bool "Enable the Feroceon L2 cache controller"
913 depends on ARCH_MV78XX0 || ARCH_MVEBU
914 default y
915 select OUTER_CACHE
916 help
917 This option enables the Feroceon L2 cache controller.
918
919config CACHE_FEROCEON_L2_WRITETHROUGH
920 bool "Force Feroceon L2 cache write through"
921 depends on CACHE_FEROCEON_L2
922 help
923 Say Y here to use the Feroceon L2 cache in writethrough mode.
924 Unless you specifically require this, say N for writeback mode.
925
926config MIGHT_HAVE_CACHE_L2X0
927 bool
928 help
929 This option should be selected by machines which have a L2x0
930 or PL310 cache controller, but where its use is optional.
931
932 The only effect of this option is to make CACHE_L2X0 and
933 related options available to the user for configuration.
934
935 Boards or SoCs which always require the cache controller
936 support to be present should select CACHE_L2X0 directly
937 instead of this option, thus preventing the user from
938 inadvertently configuring a broken kernel.
939
940config CACHE_L2X0
941 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
942 default MIGHT_HAVE_CACHE_L2X0
943 select OUTER_CACHE
944 select OUTER_CACHE_SYNC
945 help
946 This option enables the L2x0 PrimeCell.
947
948config CACHE_L2X0_PMU
949 bool "L2x0 performance monitor support" if CACHE_L2X0
950 depends on PERF_EVENTS
951 help
952 This option enables support for the performance monitoring features
953 of the L220 and PL310 outer cache controllers.
954
955if CACHE_L2X0
956
957config PL310_ERRATA_588369
958 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
959 help
960 The PL310 L2 cache controller implements three types of Clean &
961 Invalidate maintenance operations: by Physical Address
962 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
963 They are architecturally defined to behave as the execution of a
964 clean operation followed immediately by an invalidate operation,
965 both performing to the same memory location. This functionality
966 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
967 as clean lines are not invalidated as a result of these operations.
968
969config PL310_ERRATA_727915
970 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
971 help
972 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
973 operation (offset 0x7FC). This operation runs in background so that
974 PL310 can handle normal accesses while it is in progress. Under very
975 rare circumstances, due to this erratum, write data can be lost when
976 PL310 treats a cacheable write transaction during a Clean &
977 Invalidate by Way operation. Revisions prior to r3p1 are affected by
978 this errata (fixed in r3p1).
979
980config PL310_ERRATA_753970
981 bool "PL310 errata: cache sync operation may be faulty"
982 help
983 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
984
985 Under some condition the effect of cache sync operation on
986 the store buffer still remains when the operation completes.
987 This means that the store buffer is always asked to drain and
988 this prevents it from merging any further writes. The workaround
989 is to replace the normal offset of cache sync operation (0x730)
990 by another offset targeting an unmapped PL310 register 0x740.
991 This has the same effect as the cache sync operation: store buffer
992 drain and waiting for all buffers empty.
993
994config PL310_ERRATA_769419
995 bool "PL310 errata: no automatic Store Buffer drain"
996 help
997 On revisions of the PL310 prior to r3p2, the Store Buffer does
998 not automatically drain. This can cause normal, non-cacheable
999 writes to be retained when the memory system is idle, leading
1000 to suboptimal I/O performance for drivers using coherent DMA.
1001 This option adds a write barrier to the cpu_idle loop so that,
1002 on systems with an outer cache, the store buffer is drained
1003 explicitly.
1004
1005endif
1006
1007config CACHE_TAUROS2
1008 bool "Enable the Tauros2 L2 cache controller"
1009 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
1010 default y
1011 select OUTER_CACHE
1012 help
1013 This option enables the Tauros2 L2 cache controller (as
1014 found on PJ1/PJ4).
1015
1016config CACHE_UNIPHIER
1017 bool "Enable the UniPhier outer cache controller"
1018 depends on ARCH_UNIPHIER
1019 select ARM_L1_CACHE_SHIFT_7
1020 select OUTER_CACHE
1021 select OUTER_CACHE_SYNC
1022 help
1023 This option enables the UniPhier outer cache (system cache)
1024 controller.
1025
1026config CACHE_XSC3L2
1027 bool "Enable the L2 cache on XScale3"
1028 depends on CPU_XSC3
1029 default y
1030 select OUTER_CACHE
1031 help
1032 This option enables the L2 cache on XScale3.
1033
1034config ARM_L1_CACHE_SHIFT_6
1035 bool
1036 default y if CPU_V7
1037 help
1038 Setting ARM L1 cache line size to 64 Bytes.
1039
1040config ARM_L1_CACHE_SHIFT_7
1041 bool
1042 help
1043 Setting ARM L1 cache line size to 128 Bytes.
1044
1045config ARM_L1_CACHE_SHIFT
1046 int
1047 default 7 if ARM_L1_CACHE_SHIFT_7
1048 default 6 if ARM_L1_CACHE_SHIFT_6
1049 default 5
1050
1051config ARM_DMA_MEM_BUFFERABLE
1052 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1053 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1054 help
1055 Historically, the kernel has used strongly ordered mappings to
1056 provide DMA coherent memory. With the advent of ARMv7, mapping
1057 memory with differing types results in unpredictable behaviour,
1058 so on these CPUs, this option is forced on.
1059
1060 Multiple mappings with differing attributes is also unpredictable
1061 on ARMv6 CPUs, but since they do not have aggressive speculative
1062 prefetch, no harm appears to occur.
1063
1064 However, drivers may be missing the necessary barriers for ARMv6,
1065 and therefore turning this on may result in unpredictable driver
1066 behaviour. Therefore, we offer this as an option.
1067
1068 On some of the beefier ARMv7-M machines (with DMA and write
1069 buffers) you likely want this enabled, while those that
1070 didn't need it until now also won't need it in the future.
1071
1072 You are recommended say 'Y' here and debug any affected drivers.
1073
1074config ARM_HEAVY_MB
1075 bool
1076
1077config ARCH_SUPPORTS_BIG_ENDIAN
1078 bool
1079 help
1080 This option specifies the architecture can support big endian
1081 operation.
1082
1083config DEBUG_ALIGN_RODATA
1084 bool "Make rodata strictly non-executable"
1085 depends on STRICT_KERNEL_RWX
1086 default y
1087 help
1088 If this is set, rodata will be made explicitly non-executable. This
1089 provides protection on the rare chance that attackers might find and
1090 use ROP gadgets that exist in the rodata section. This adds an
1091 additional section-aligned split of rodata from kernel text so it
1092 can be made explicitly non-executable. This padding may waste memory
1093 space to gain the additional protection.
1094
