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16#ifndef __ASM_CPUTYPE_H
17#define __ASM_CPUTYPE_H
18
19#define INVALID_HWID ULONG_MAX
20
21#define MPIDR_UP_BITMASK (0x1 << 30)
22#define MPIDR_MT_BITMASK (0x1 << 24)
23#define MPIDR_HWID_BITMASK 0xff00ffffff
24
25#define MPIDR_LEVEL_BITS_SHIFT 3
26#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
27#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
28
29#define MPIDR_LEVEL_SHIFT(level) \
30 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
31
32#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
33 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
34
35#define MIDR_REVISION_MASK 0xf
36#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
37#define MIDR_PARTNUM_SHIFT 4
38#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
39#define MIDR_PARTNUM(midr) \
40 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
41#define MIDR_ARCHITECTURE_SHIFT 16
42#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
43#define MIDR_ARCHITECTURE(midr) \
44 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
45#define MIDR_VARIANT_SHIFT 20
46#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
47#define MIDR_VARIANT(midr) \
48 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
49#define MIDR_IMPLEMENTOR_SHIFT 24
50#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
51#define MIDR_IMPLEMENTOR(midr) \
52 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
53
54#define MIDR_CPU_MODEL(imp, partnum) \
55 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
56 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
57 ((partnum) << MIDR_PARTNUM_SHIFT))
58
59#define MIDR_CPU_VAR_REV(var, rev) \
60 (((var) << MIDR_VARIANT_SHIFT) | (rev))
61
62#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
63 MIDR_ARCHITECTURE_MASK)
64
65#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \
66({ \
67 u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \
68 u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \
69 \
70 _model == (model) && rv >= (rv_min) && rv <= (rv_max); \
71 })
72
73#define ARM_CPU_IMP_ARM 0x41
74#define ARM_CPU_IMP_APM 0x50
75#define ARM_CPU_IMP_CAVIUM 0x43
76#define ARM_CPU_IMP_BRCM 0x42
77#define ARM_CPU_IMP_QCOM 0x51
78
79#define ARM_CPU_PART_AEM_V8 0xD0F
80#define ARM_CPU_PART_FOUNDATION 0xD00
81#define ARM_CPU_PART_CORTEX_A57 0xD07
82#define ARM_CPU_PART_CORTEX_A53 0xD03
83#define ARM_CPU_PART_CORTEX_A73 0xD09
84
85#define APM_CPU_PART_POTENZA 0x000
86
87#define CAVIUM_CPU_PART_THUNDERX 0x0A1
88#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
89#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
90
91#define BRCM_CPU_PART_VULCAN 0x516
92
93#define QCOM_CPU_PART_FALKOR_V1 0x800
94
95#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
96#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
97#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
98#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
99#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
100#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
101#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
102
103#ifndef __ASSEMBLY__
104
105#include <asm/sysreg.h>
106
107#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
108
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113
114static inline u32 __attribute_const__ read_cpuid_id(void)
115{
116 return read_cpuid(MIDR_EL1);
117}
118
119static inline u64 __attribute_const__ read_cpuid_mpidr(void)
120{
121 return read_cpuid(MPIDR_EL1);
122}
123
124static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
125{
126 return MIDR_IMPLEMENTOR(read_cpuid_id());
127}
128
129static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
130{
131 return MIDR_PARTNUM(read_cpuid_id());
132}
133
134static inline u32 __attribute_const__ read_cpuid_cachetype(void)
135{
136 return read_cpuid(CTR_EL0);
137}
138#endif
139
140#endif
141