LXR linux/arch/arm64/include/asm/kvm

   1/*
   2 * Copyright (C) 2012,2013 - ARM Ltd
   3 * Author: Marc Zyngier <marc.zyngier@arm.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __ARM64_KVM_ARM_H__
  19#define __ARM64_KVM_ARM_H__
  20
  21#include <asm/esr.h>
  22#include <asm/memory.h>
  23#include <asm/types.h>
  24
  25/* Hyp Configuration Register (HCR) bits */
  26#define HCR_E2H         (UL(1) << 34)
  27#define HCR_ID          (UL(1) << 33)
  28#define HCR_CD          (UL(1) << 32)
  29#define HCR_RW_SHIFT    31
  30#define HCR_RW          (UL(1) << HCR_RW_SHIFT)
  31#define HCR_TRVM        (UL(1) << 30)
  32#define HCR_HCD         (UL(1) << 29)
  33#define HCR_TDZ         (UL(1) << 28)
  34#define HCR_TGE         (UL(1) << 27)
  35#define HCR_TVM         (UL(1) << 26)
  36#define HCR_TTLB        (UL(1) << 25)
  37#define HCR_TPU         (UL(1) << 24)
  38#define HCR_TPC         (UL(1) << 23)
  39#define HCR_TSW         (UL(1) << 22)
  40#define HCR_TAC         (UL(1) << 21)
  41#define HCR_TIDCP       (UL(1) << 20)
  42#define HCR_TSC         (UL(1) << 19)
  43#define HCR_TID3        (UL(1) << 18)
  44#define HCR_TID2        (UL(1) << 17)
  45#define HCR_TID1        (UL(1) << 16)
  46#define HCR_TID0        (UL(1) << 15)
  47#define HCR_TWE         (UL(1) << 14)
  48#define HCR_TWI         (UL(1) << 13)
  49#define HCR_DC          (UL(1) << 12)
  50#define HCR_BSU         (3 << 10)
  51#define HCR_BSU_IS      (UL(1) << 10)
  52#define HCR_FB          (UL(1) << 9)
  53#define HCR_VSE         (UL(1) << 8)
  54#define HCR_VI          (UL(1) << 7)
  55#define HCR_VF          (UL(1) << 6)
  56#define HCR_AMO         (UL(1) << 5)
  57#define HCR_IMO         (UL(1) << 4)
  58#define HCR_FMO         (UL(1) << 3)
  59#define HCR_PTW         (UL(1) << 2)
  60#define HCR_SWIO        (UL(1) << 1)
  61#define HCR_VM          (UL(1) << 0)
  62
  63/*
  64 * The bits we set in HCR:
  65 * RW:          64bit by default, can be overridden for 32bit VMs
  66 * TAC:         Trap ACTLR
  67 * TSC:         Trap SMC
  68 * TVM:         Trap VM ops (until M+C set in SCTLR_EL1)
  69 * TSW:         Trap cache operations by set/way
  70 * TWE:         Trap WFE
  71 * TWI:         Trap WFI
  72 * TIDCP:       Trap L2CTLR/L2ECTLR
  73 * BSU_IS:      Upgrade barriers to the inner shareable domain
  74 * FB:          Force broadcast of all maintainance operations
  75 * AMO:         Override CPSR.A and enable signaling with VA
  76 * IMO:         Override CPSR.I and enable signaling with VI
  77 * FMO:         Override CPSR.F and enable signaling with VF
  78 * SWIO:        Turn set/way invalidates into set/way clean+invalidate
  79 */
  80#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
  81                         HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
  82                         HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW)
  83#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
  84#define HCR_INT_OVERRIDE   (HCR_FMO | HCR_IMO)
  85#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
  86
  87/* TCR_EL2 Registers bits */
  88#define TCR_EL2_RES1            ((1 << 31) | (1 << 23))
  89#define TCR_EL2_TBI             (1 << 20)
  90#define TCR_EL2_PS_SHIFT        16
  91#define TCR_EL2_PS_MASK         (7 << TCR_EL2_PS_SHIFT)
  92#define TCR_EL2_PS_40B          (2 << TCR_EL2_PS_SHIFT)
  93#define TCR_EL2_TG0_MASK        TCR_TG0_MASK
  94#define TCR_EL2_SH0_MASK        TCR_SH0_MASK
  95#define TCR_EL2_ORGN0_MASK      TCR_ORGN0_MASK
  96#define TCR_EL2_IRGN0_MASK      TCR_IRGN0_MASK
  97#define TCR_EL2_T0SZ_MASK       0x3f
  98#define TCR_EL2_MASK    (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
  99                         TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
 100
 101/* VTCR_EL2 Registers bits */
 102#define VTCR_EL2_RES1           (1 << 31)
 103#define VTCR_EL2_HD             (1 << 22)
 104#define VTCR_EL2_HA             (1 << 21)
 105#define VTCR_EL2_PS_MASK        TCR_EL2_PS_MASK
 106#define VTCR_EL2_TG0_MASK       TCR_TG0_MASK
 107#define VTCR_EL2_TG0_4K         TCR_TG0_4K
 108#define VTCR_EL2_TG0_16K        TCR_TG0_16K
 109#define VTCR_EL2_TG0_64K        TCR_TG0_64K
 110#define VTCR_EL2_SH0_MASK       TCR_SH0_MASK
 111#define VTCR_EL2_SH0_INNER      TCR_SH0_INNER
 112#define VTCR_EL2_ORGN0_MASK     TCR_ORGN0_MASK
 113#define VTCR_EL2_ORGN0_WBWA     TCR_ORGN0_WBWA
 114#define VTCR_EL2_IRGN0_MASK     TCR_IRGN0_MASK
 115#define VTCR_EL2_IRGN0_WBWA     TCR_IRGN0_WBWA
 116#define VTCR_EL2_SL0_SHIFT      6
 117#define VTCR_EL2_SL0_MASK       (3 << VTCR_EL2_SL0_SHIFT)
 118#define VTCR_EL2_SL0_LVL1       (1 << VTCR_EL2_SL0_SHIFT)
 119#define VTCR_EL2_T0SZ_MASK      0x3f
 120#define VTCR_EL2_T0SZ_40B       24
 121#define VTCR_EL2_VS_SHIFT       19
 122#define VTCR_EL2_VS_8BIT        (0 << VTCR_EL2_VS_SHIFT)
 123#define VTCR_EL2_VS_16BIT       (1 << VTCR_EL2_VS_SHIFT)
 124
 125/*
 126 * We configure the Stage-2 page tables to always restrict the IPA space to be
 127 * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
 128 * not known to exist and will break with this configuration.
 129 *
 130 * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
 131 * (see hyp-init.S).
 132 *
 133 * Note that when using 4K pages, we concatenate two first level page tables
 134 * together. With 16K pages, we concatenate 16 first level page tables.
 135 *
 136 * The magic numbers used for VTTBR_X in this patch can be found in Tables
 137 * D4-23 and D4-25 in ARM DDI 0487A.b.
 138 */
 139
 140#define VTCR_EL2_T0SZ_IPA       VTCR_EL2_T0SZ_40B
 141#define VTCR_EL2_COMMON_BITS    (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
 142                                 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
 143
 144#ifdef CONFIG_ARM64_64K_PAGES
 145/*
 146 * Stage2 translation configuration:
 147 * 64kB pages (TG0 = 1)
 148 * 2 level page tables (SL = 1)
 149 */
 150#define VTCR_EL2_TGRAN_FLAGS            (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)
 151#define VTTBR_X_TGRAN_MAGIC             38
 152#elif defined(CONFIG_ARM64_16K_PAGES)
 153/*
 154 * Stage2 translation configuration:
 155 * 16kB pages (TG0 = 2)
 156 * 2 level page tables (SL = 1)
 157 */
 158#define VTCR_EL2_TGRAN_FLAGS            (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)
 159#define VTTBR_X_TGRAN_MAGIC             42
 160#else   /* 4K */
 161/*
 162 * Stage2 translation configuration:
 163 * 4kB pages (TG0 = 0)
 164 * 3 level page tables (SL = 1)
 165 */
 166#define VTCR_EL2_TGRAN_FLAGS            (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1)
 167#define VTTBR_X_TGRAN_MAGIC             37
 168#endif
 169
 170#define VTCR_EL2_FLAGS                  (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
 171#define VTTBR_X                         (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
 172
 173#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
 174#define VTTBR_BADDR_MASK  (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
 175#define VTTBR_VMID_SHIFT  (UL(48))
 176#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
 177
 178/* Hyp System Trap Register */
 179#define HSTR_EL2_T(x)   (1 << x)
 180
 181/* Hyp Coprocessor Trap Register Shifts */
 182#define CPTR_EL2_TFP_SHIFT 10
 183
 184/* Hyp Coprocessor Trap Register */
 185#define CPTR_EL2_TCPAC  (1 << 31)
 186#define CPTR_EL2_TTA    (1 << 20)
 187#define CPTR_EL2_TFP    (1 << CPTR_EL2_TFP_SHIFT)
 188#define CPTR_EL2_DEFAULT        0x000033ff
 189
 190/* Hyp Debug Configuration Register bits */
 191#define MDCR_EL2_TPMS           (1 << 14)
 192#define MDCR_EL2_E2PB_MASK      (UL(0x3))
 193#define MDCR_EL2_E2PB_SHIFT     (UL(12))
 194#define MDCR_EL2_TDRA           (1 << 11)
 195#define MDCR_EL2_TDOSA          (1 << 10)
 196#define MDCR_EL2_TDA            (1 << 9)
 197#define MDCR_EL2_TDE            (1 << 8)
 198#define MDCR_EL2_HPME           (1 << 7)
 199#define MDCR_EL2_TPM            (1 << 6)
 200#define MDCR_EL2_TPMCR          (1 << 5)
 201#define MDCR_EL2_HPMN_MASK      (0x1F)
 202
 203/* For compatibility with fault code shared with 32-bit */
 204#define FSC_FAULT       ESR_ELx_FSC_FAULT
 205#define FSC_ACCESS      ESR_ELx_FSC_ACCESS
 206#define FSC_PERM        ESR_ELx_FSC_PERM
 207#define FSC_SEA         ESR_ELx_FSC_EXTABT
 208#define FSC_SEA_TTW0    (0x14)
 209#define FSC_SEA_TTW1    (0x15)
 210#define FSC_SEA_TTW2    (0x16)
 211#define FSC_SEA_TTW3    (0x17)
 212#define FSC_SECC        (0x18)
 213#define FSC_SECC_TTW0   (0x1c)
 214#define FSC_SECC_TTW1   (0x1d)
 215#define FSC_SECC_TTW2   (0x1e)
 216#define FSC_SECC_TTW3   (0x1f)
 217
 218/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
 219#define HPFAR_MASK      (~UL(0xf))
 220
 221#define kvm_arm_exception_type  \
 222        {0, "IRQ" },            \
 223        {1, "TRAP" }
 224
 225#define ECN(x) { ESR_ELx_EC_##x, #x }
 226
 227#define kvm_arm_exception_class \
 228        ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
 229        ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
 230        ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
 231        ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
 232        ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
 233        ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
 234        ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
 235        ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
 236
 237#define CPACR_EL1_FPEN          (3 << 20)
 238#define CPACR_EL1_TTA           (1 << 28)
 239
 240#endif /* __ARM64_KVM_ARM_H__ */
 241