LXR linux/arch/blackfin/mach-bf533/include/mach/bf533.h

   1/*
   2 * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
   3 *
   4 * Copyright 2005-2008 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#ifndef __MACH_BF533_H__
  10#define __MACH_BF533_H__
  11
  12#define OFFSET_(x) ((x) & 0x0000FFFF)
  13
  14/*some misc defines*/
  15#define IMASK_IVG15             0x8000
  16#define IMASK_IVG14             0x4000
  17#define IMASK_IVG13             0x2000
  18#define IMASK_IVG12             0x1000
  19
  20#define IMASK_IVG11             0x0800
  21#define IMASK_IVG10             0x0400
  22#define IMASK_IVG9              0x0200
  23#define IMASK_IVG8              0x0100
  24
  25#define IMASK_IVG7              0x0080
  26#define IMASK_IVGTMR            0x0040
  27#define IMASK_IVGHW             0x0020
  28
  29/***************************/
  30
  31
  32#define BFIN_DSUBBANKS  4
  33#define BFIN_DWAYS              2
  34#define BFIN_DLINES             64
  35#define BFIN_ISUBBANKS  4
  36#define BFIN_IWAYS              4
  37#define BFIN_ILINES             32
  38
  39#define WAY0_L                  0x1
  40#define WAY1_L                  0x2
  41#define WAY01_L                 0x3
  42#define WAY2_L                  0x4
  43#define WAY02_L                 0x5
  44#define WAY12_L                 0x6
  45#define WAY012_L                0x7
  46
  47#define WAY3_L                  0x8
  48#define WAY03_L                 0x9
  49#define WAY13_L                 0xA
  50#define WAY013_L                0xB
  51
  52#define WAY32_L                 0xC
  53#define WAY320_L                0xD
  54#define WAY321_L                0xE
  55#define WAYALL_L                0xF
  56
  57#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
  58
  59/* IAR0 BIT FIELDS*/
  60#define RTC_ERROR_BIT                   0x0FFFFFFF
  61#define UART_ERROR_BIT                  0xF0FFFFFF
  62#define SPORT1_ERROR_BIT                0xFF0FFFFF
  63#define SPI_ERROR_BIT                   0xFFF0FFFF
  64#define SPORT0_ERROR_BIT                0xFFFF0FFF
  65#define PPI_ERROR_BIT                   0xFFFFF0FF
  66#define DMA_ERROR_BIT                   0xFFFFFF0F
  67#define PLLWAKE_ERROR_BIT               0xFFFFFFFF
  68
  69/* IAR1 BIT FIELDS*/
  70#define DMA7_UARTTX_BIT                 0x0FFFFFFF
  71#define DMA6_UARTRX_BIT                 0xF0FFFFFF
  72#define DMA5_SPI_BIT                    0xFF0FFFFF
  73#define DMA4_SPORT1TX_BIT               0xFFF0FFFF
  74#define DMA3_SPORT1RX_BIT               0xFFFF0FFF
  75#define DMA2_SPORT0TX_BIT               0xFFFFF0FF
  76#define DMA1_SPORT0RX_BIT               0xFFFFFF0F
  77#define DMA0_PPI_BIT                    0xFFFFFFFF
  78
  79/* IAR2 BIT FIELDS*/
  80#define WDTIMER_BIT                     0x0FFFFFFF
  81#define MEMDMA1_BIT                     0xF0FFFFFF
  82#define MEMDMA0_BIT                     0xFF0FFFFF
  83#define PFB_BIT                         0xFFF0FFFF
  84#define PFA_BIT                         0xFFFF0FFF
  85#define TIMER2_BIT                      0xFFFFF0FF
  86#define TIMER1_BIT                      0xFFFFFF0F
  87#define TIMER0_BIT                      0xFFFFFFFF
  88
  89/********************************* EBIU Settings ************************************/
  90#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
  91#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
  92
  93#ifdef CONFIG_C_AMBEN_ALL
  94#define V_AMBEN AMBEN_ALL
  95#endif
  96#ifdef CONFIG_C_AMBEN
  97#define V_AMBEN 0x0
  98#endif
  99#ifdef CONFIG_C_AMBEN_B0
 100#define V_AMBEN AMBEN_B0
 101#endif
 102#ifdef CONFIG_C_AMBEN_B0_B1
 103#define V_AMBEN AMBEN_B0_B1
 104#endif
 105#ifdef CONFIG_C_AMBEN_B0_B1_B2
 106#define V_AMBEN AMBEN_B0_B1_B2
 107#endif
 108#ifdef CONFIG_C_AMCKEN
 109#define V_AMCKEN AMCKEN
 110#else
 111#define V_AMCKEN 0x0
 112#endif
 113#ifdef CONFIG_C_CDPRIO
 114#define V_CDPRIO 0x100
 115#else
 116#define V_CDPRIO 0x0
 117#endif
 118
 119#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
 120
 121#ifdef CONFIG_BF533
 122#define CPU "BF533"
 123#define CPUID 0x27a5
 124#endif
 125#ifdef CONFIG_BF532
 126#define CPU "BF532"
 127#define CPUID 0x27a5
 128#endif
 129#ifdef CONFIG_BF531
 130#define CPU "BF531"
 131#define CPUID 0x27a5
 132#endif
 133
 134#ifndef CPU
 135#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
 136#endif
 137
 138#endif                          /* __MACH_BF533_H__  */
 139