1/****************************************************************************/ 2 3/* 4 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 5 * 6 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 7 */ 8 9/****************************************************************************/ 10#ifndef m520xsim_h 11#define m520xsim_h 12/****************************************************************************/ 13 14#define CPU_NAME "COLDFIRE(m520x)" 15#define CPU_INSTR_PER_JIFFY 3 16#define MCF_BUSCLK (MCF_CLK / 2) 17 18#include <asm/m52xxacr.h> 19 20/* 21 * Define the 520x SIM register set addresses. 22 */ 23#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ 24#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 25#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 26#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 27#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 28#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 29#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 30#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 31#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 32#define MCFINTC_ICR0 0x40 /* Base ICR register */ 33 34/* 35 * The common interrupt controller code just wants to know the absolute 36 * address to the SIMR and CIMR registers (not offsets into IPSBAR). 37 * The 520x family only has a single INTC unit. 38 */ 39#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) 40#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) 41#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) 42#define MCFINTC1_SIMR (0) 43#define MCFINTC1_CIMR (0) 44#define MCFINTC1_ICR0 (0) 45#define MCFINTC2_SIMR (0) 46#define MCFINTC2_CIMR (0) 47#define MCFINTC2_ICR0 (0) 48 49#define MCFINT_VECBASE 64 50#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 51#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 52#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 53#define MCFINT_I2C0 30 /* Interrupt number for I2C */ 54#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 55#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ 56#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ 57#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */ 58#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 59 60#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 61#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 62#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 63 64#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 65#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 66#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 67 68#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 69#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 70 71#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 72/* 73 * SDRAM configuration registers. 74 */ 75#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ 76#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ 77#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ 78#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ 79#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ 80#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ 81 82/* 83 * EPORT and GPIO registers. 84 */ 85#define MCFEPORT_EPPAR 0xFC088000 86#define MCFEPORT_EPDDR 0xFC088002 87#define MCFEPORT_EPIER 0xFC088003 88#define MCFEPORT_EPDR 0xFC088004 89#define MCFEPORT_EPPDR 0xFC088005 90#define MCFEPORT_EPFR 0xFC088006 91 92#define MCFGPIO_PODR_BUSCTL 0xFC0A4000 93#define MCFGPIO_PODR_BE 0xFC0A4001 94#define MCFGPIO_PODR_CS 0xFC0A4002 95#define MCFGPIO_PODR_FECI2C 0xFC0A4003 96#define MCFGPIO_PODR_QSPI 0xFC0A4004 97#define MCFGPIO_PODR_TIMER 0xFC0A4005 98#define MCFGPIO_PODR_UART 0xFC0A4006 99#define MCFGPIO_PODR_FECH 0xFC0A4007 100#define MCFGPIO_PODR_FECL 0xFC0A4008 101 102#define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 103#define MCFGPIO_PDDR_BE 0xFC0A400D 104#define MCFGPIO_PDDR_CS 0xFC0A400E 105#define MCFGPIO_PDDR_FECI2C 0xFC0A400F 106#define MCFGPIO_PDDR_QSPI 0xFC0A4010 107#define MCFGPIO_PDDR_TIMER 0xFC0A4011 108#define MCFGPIO_PDDR_UART 0xFC0A4012 109#define MCFGPIO_PDDR_FECH 0xFC0A4013 110#define MCFGPIO_PDDR_FECL 0xFC0A4014 111 112#define MCFGPIO_PPDSDR_CS 0xFC0A401A 113#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 114#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 115#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 116#define MCFGPIO_PPDSDR_UART 0xFC0A401E 117#define MCFGPIO_PPDSDR_FECH 0xFC0A401F 118#define MCFGPIO_PPDSDR_FECL 0xFC0A4020 119 120#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 121#define MCFGPIO_PCLRR_BE 0xFC0A4025 122#define MCFGPIO_PCLRR_CS 0xFC0A4026 123#define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 124#define MCFGPIO_PCLRR_QSPI 0xFC0A4028 125#define MCFGPIO_PCLRR_TIMER 0xFC0A4029 126#define MCFGPIO_PCLRR_UART 0xFC0A402A 127#define MCFGPIO_PCLRR_FECH 0xFC0A402B 128#define MCFGPIO_PCLRR_FECL 0xFC0A402C 129 130/* 131 * Generic GPIO support 132 */ 133#define MCFGPIO_PODR MCFGPIO_PODR_CS 134#define MCFGPIO_PDDR MCFGPIO_PDDR_CS 135#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 136#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 137#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 138 139#define MCFGPIO_PIN_MAX 80 140#define MCFGPIO_IRQ_MAX 8 141#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 142 143#define MCF_GPIO_PAR_UART 0xFC0A4036 144#define MCF_GPIO_PAR_FECI2C 0xFC0A4033 145#define MCF_GPIO_PAR_QSPI 0xFC0A4034 146#define MCF_GPIO_PAR_FEC 0xFC0A4038 147 148#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 149#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 150 151#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 152#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 153 154#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 155#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 156 157/* 158 * PIT timer module. 159 */ 160#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ 161#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ 162 163/* 164 * UART module. 165 */ 166#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ 167#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ 168#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ 169 170/* 171 * FEC module. 172 */ 173#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ 174#define MCFFEC_SIZE0 0x800 /* Register set size */ 175 176/* 177 * QSPI module. 178 */ 179#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ 180#define MCFQSPI_SIZE 0x40 /* Register set size */ 181 182#define MCFQSPI_CS0 46 183#define MCFQSPI_CS1 47 184#define MCFQSPI_CS2 27 185 186/* 187 * Reset Control Unit. 188 */ 189#define MCF_RCR 0xFC0A0000 190#define MCF_RSR 0xFC0A0001 191 192#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 193#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 194 195/* 196 * Power Management. 197 */ 198#define MCFPM_WCR 0xfc040013 199#define MCFPM_PPMSR0 0xfc04002c 200#define MCFPM_PPMCR0 0xfc04002d 201#define MCFPM_PPMHR0 0xfc040030 202#define MCFPM_PPMLR0 0xfc040034 203#define MCFPM_LPCR 0xfc0a0007 204 205/* 206 * I2C module. 207 */ 208#define MCFI2C_BASE0 0xFC058000 209#define MCFI2C_SIZE0 0x40 210 211/****************************************************************************/ 212#endif /* m520xsim_h */ 213