LXR linux/arch/mips/lantiq/prom.c

   1/*
   2 *  This program is free software; you can redistribute it and/or modify it
   3 *  under the terms of the GNU General Public License version 2 as published
   4 *  by the Free Software Foundation.
   5 *
   6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
   7 */
   8
   9#include <linux/export.h>
  10#include <linux/clk.h>
  11#include <linux/bootmem.h>
  12#include <linux/of_platform.h>
  13#include <linux/of_fdt.h>
  14
  15#include <asm/bootinfo.h>
  16#include <asm/time.h>
  17#include <asm/prom.h>
  18
  19#include <lantiq.h>
  20
  21#include "prom.h"
  22#include "clk.h"
  23
  24/* access to the ebu needs to be locked between different drivers */
  25DEFINE_SPINLOCK(ebu_lock);
  26EXPORT_SYMBOL_GPL(ebu_lock);
  27
  28/*
  29 * This is needed by the VPE loader code, just set it to 0 and assume
  30 * that the firmware hardcodes this value to something useful.
  31 */
  32unsigned long physical_memsize = 0L;
  33
  34/*
  35 * this struct is filled by the soc specific detection code and holds
  36 * information about the specific soc type, revision and name
  37 */
  38static struct ltq_soc_info soc_info;
  39
  40const char *get_system_type(void)
  41{
  42        return soc_info.sys_type;
  43}
  44
  45int ltq_soc_type(void)
  46{
  47        return soc_info.type;
  48}
  49
  50void __init prom_free_prom_memory(void)
  51{
  52}
  53
  54static void __init prom_init_cmdline(void)
  55{
  56        int argc = fw_arg0;
  57        char **argv = (char **) KSEG1ADDR(fw_arg1);
  58        int i;
  59
  60        arcs_cmdline[0] = '\0';
  61
  62        for (i = 0; i < argc; i++) {
  63                char *p = (char *) KSEG1ADDR(argv[i]);
  64
  65                if (CPHYSADDR(p) && *p) {
  66                        strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
  67                        strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
  68                }
  69        }
  70}
  71
  72void __init plat_mem_setup(void)
  73{
  74        void *dtb;
  75
  76        ioport_resource.start = IOPORT_RESOURCE_START;
  77        ioport_resource.end = IOPORT_RESOURCE_END;
  78        iomem_resource.start = IOMEM_RESOURCE_START;
  79        iomem_resource.end = IOMEM_RESOURCE_END;
  80
  81        set_io_port_base((unsigned long) KSEG1);
  82
  83        if (fw_passed_dtb) /* UHI interface */
  84                dtb = (void *)fw_passed_dtb;
  85        else if (__dtb_start != __dtb_end)
  86                dtb = (void *)__dtb_start;
  87        else
  88                panic("no dtb found");
  89
  90        /*
  91         * Load the devicetree. This causes the chosen node to be
  92         * parsed resulting in our memory appearing
  93         */
  94        __dt_setup_arch(dtb);
  95}
  96
  97void __init device_tree_init(void)
  98{
  99        unflatten_and_copy_device_tree();
 100}
 101
 102void __init prom_init(void)
 103{
 104        /* call the soc specific detetcion code and get it to fill soc_info */
 105        ltq_soc_detect(&soc_info);
 106        snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
 107                soc_info.name, soc_info.rev_type);
 108        soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
 109        pr_info("SoC: %s\n", soc_info.sys_type);
 110        prom_init_cmdline();
 111
 112#if defined(CONFIG_MIPS_MT_SMP)
 113        if (register_vsmp_smp_ops())
 114                panic("failed to register_vsmp_smp_ops()");
 115#endif
 116}
 117
 118int __init plat_of_setup(void)
 119{
 120        return __dt_register_buses(soc_info.compatible, "simple-bus");
 121}
 122
 123arch_initcall(plat_of_setup);
 124