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9#ifndef _ASM_POWERPC_REG_H
10#define _ASM_POWERPC_REG_H
11#ifdef __KERNEL__
12
13#include <linux/stringify.h>
14#include <asm/cputable.h>
15
16
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h>
19#endif
20
21#ifdef CONFIG_FSL_EMB_PERFMON
22#include <asm/reg_fsl_emb.h>
23#endif
24
25#ifdef CONFIG_8xx
26#include <asm/reg_8xx.h>
27#endif
28
29#define MSR_SF_LG 63
30#define MSR_ISF_LG 61
31#define MSR_HV_LG 60
32#define MSR_TS_T_LG 34
33#define MSR_TS_S_LG 33
34#define MSR_TS_LG 33
35#define MSR_TM_LG 32
36#define MSR_VEC_LG 25
37#define MSR_VSX_LG 23
38#define MSR_POW_LG 18
39#define MSR_WE_LG 18
40#define MSR_TGPR_LG 17
41#define MSR_CE_LG 17
42#define MSR_ILE_LG 16
43#define MSR_EE_LG 15
44#define MSR_PR_LG 14
45#define MSR_FP_LG 13
46#define MSR_ME_LG 12
47#define MSR_FE0_LG 11
48#define MSR_SE_LG 10
49#define MSR_BE_LG 9
50#define MSR_DE_LG 9
51#define MSR_FE1_LG 8
52#define MSR_IP_LG 6
53#define MSR_IR_LG 5
54#define MSR_DR_LG 4
55#define MSR_PE_LG 3
56#define MSR_PX_LG 2
57#define MSR_PMM_LG 2
58#define MSR_RI_LG 1
59#define MSR_LE_LG 0
60
61#ifdef __ASSEMBLY__
62#define __MASK(X) (1<<(X))
63#else
64#define __MASK(X) (1UL<<(X))
65#endif
66
67#ifdef CONFIG_PPC64
68#define MSR_SF __MASK(MSR_SF_LG)
69#define MSR_ISF __MASK(MSR_ISF_LG)
70#define MSR_HV __MASK(MSR_HV_LG)
71#else
72
73#define MSR_SF 0
74#define MSR_ISF 0
75#define MSR_HV 0
76#endif
77
78
79
80
81
82#ifndef MSR_SPE
83#define MSR_SPE 0
84#endif
85
86#define MSR_VEC __MASK(MSR_VEC_LG)
87#define MSR_VSX __MASK(MSR_VSX_LG)
88#define MSR_POW __MASK(MSR_POW_LG)
89#define MSR_WE __MASK(MSR_WE_LG)
90#define MSR_TGPR __MASK(MSR_TGPR_LG)
91#define MSR_CE __MASK(MSR_CE_LG)
92#define MSR_ILE __MASK(MSR_ILE_LG)
93#define MSR_EE __MASK(MSR_EE_LG)
94#define MSR_PR __MASK(MSR_PR_LG)
95#define MSR_FP __MASK(MSR_FP_LG)
96#define MSR_ME __MASK(MSR_ME_LG)
97#define MSR_FE0 __MASK(MSR_FE0_LG)
98#define MSR_SE __MASK(MSR_SE_LG)
99#define MSR_BE __MASK(MSR_BE_LG)
100#define MSR_DE __MASK(MSR_DE_LG)
101#define MSR_FE1 __MASK(MSR_FE1_LG)
102#define MSR_IP __MASK(MSR_IP_LG)
103#define MSR_IR __MASK(MSR_IR_LG)
104#define MSR_DR __MASK(MSR_DR_LG)
105#define MSR_PE __MASK(MSR_PE_LG)
106#define MSR_PX __MASK(MSR_PX_LG)
107#ifndef MSR_PMM
108#define MSR_PMM __MASK(MSR_PMM_LG)
109#endif
110#define MSR_RI __MASK(MSR_RI_LG)
111#define MSR_LE __MASK(MSR_LE_LG)
112
113#define MSR_TM __MASK(MSR_TM_LG)
114#define MSR_TS_N 0
115#define MSR_TS_S __MASK(MSR_TS_S_LG)
116#define MSR_TS_T __MASK(MSR_TS_T_LG)
117#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S)
118#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0)
119#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK)
120#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
121#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
122
123#if defined(CONFIG_PPC_BOOK3S_64)
124#define MSR_64BIT MSR_SF
125
126
127#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
128#ifdef __BIG_ENDIAN__
129#define MSR_ __MSR
130#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
131#else
132#define MSR_ (__MSR | MSR_LE)
133#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
134#endif
135#define MSR_KERNEL (MSR_ | MSR_64BIT)
136#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
137#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
138#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
139
140#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
141#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
142#endif
143
144#ifndef MSR_64BIT
145#define MSR_64BIT 0
146#endif
147
148
149#define PSSCR_RL_MASK 0x0000000F
150#define PSSCR_MTL_MASK 0x000000F0
151#define PSSCR_TR_MASK 0x00000300
152#define PSSCR_PSLL_MASK 0x000F0000
153#define PSSCR_EC 0x00100000
154#define PSSCR_ESL 0x00200000
155#define PSSCR_SD 0x00400000
156#define PSSCR_PLS 0xf000000000000000
157#define PSSCR_GUEST_VIS 0xf0000000000003ff
158
159
160#define FPSCR_FX 0x80000000
161#define FPSCR_FEX 0x40000000
162#define FPSCR_VX 0x20000000
163#define FPSCR_OX 0x10000000
164#define FPSCR_UX 0x08000000
165#define FPSCR_ZX 0x04000000
166#define FPSCR_XX 0x02000000
167#define FPSCR_VXSNAN 0x01000000
168#define FPSCR_VXISI 0x00800000
169#define FPSCR_VXIDI 0x00400000
170#define FPSCR_VXZDZ 0x00200000
171#define FPSCR_VXIMZ 0x00100000
172#define FPSCR_VXVC 0x00080000
173#define FPSCR_FR 0x00040000
174#define FPSCR_FI 0x00020000
175#define FPSCR_FPRF 0x0001f000
176#define FPSCR_FPCC 0x0000f000
177#define FPSCR_VXSOFT 0x00000400
178#define FPSCR_VXSQRT 0x00000200
179#define FPSCR_VXCVI 0x00000100
180#define FPSCR_VE 0x00000080
181#define FPSCR_OE 0x00000040
182#define FPSCR_UE 0x00000020
183#define FPSCR_ZE 0x00000010
184#define FPSCR_XE 0x00000008
185#define FPSCR_NI 0x00000004
186#define FPSCR_RN 0x00000003
187
188
189#define SPEFSCR_SOVH 0x80000000
190#define SPEFSCR_OVH 0x40000000
191#define SPEFSCR_FGH 0x20000000
192#define SPEFSCR_FXH 0x10000000
193#define SPEFSCR_FINVH 0x08000000
194#define SPEFSCR_FDBZH 0x04000000
195#define SPEFSCR_FUNFH 0x02000000
196#define SPEFSCR_FOVFH 0x01000000
197#define SPEFSCR_FINXS 0x00200000
198#define SPEFSCR_FINVS 0x00100000
199#define SPEFSCR_FDBZS 0x00080000
200#define SPEFSCR_FUNFS 0x00040000
201#define SPEFSCR_FOVFS 0x00020000
202#define SPEFSCR_MODE 0x00010000
203#define SPEFSCR_SOV 0x00008000
204#define SPEFSCR_OV 0x00004000
205#define SPEFSCR_FG 0x00002000
206#define SPEFSCR_FX 0x00001000
207#define SPEFSCR_FINV 0x00000800
208#define SPEFSCR_FDBZ 0x00000400
209#define SPEFSCR_FUNF 0x00000200
210#define SPEFSCR_FOVF 0x00000100
211#define SPEFSCR_FINXE 0x00000040
212#define SPEFSCR_FINVE 0x00000020
213#define SPEFSCR_FDBZE 0x00000010
214#define SPEFSCR_FUNFE 0x00000008
215#define SPEFSCR_FOVFE 0x00000004
216#define SPEFSCR_FRMC 0x00000003
217
218
219
220#ifdef CONFIG_40x
221#define SPRN_PID 0x3B1
222#else
223#define SPRN_PID 0x030
224#ifdef CONFIG_BOOKE
225#define SPRN_PID0 SPRN_PID
226#endif
227#endif
228
229#define SPRN_CTR 0x009
230#define SPRN_DSCR 0x11
231#define SPRN_CFAR 0x1c
232#define SPRN_AMR 0x1d
233#define SPRN_UAMOR 0x9d
234#define SPRN_AMOR 0x15d
235#define SPRN_ACOP 0x1F
236#define SPRN_TFIAR 0x81
237#define SPRN_TEXASR 0x82
238#define SPRN_TEXASRU 0x83
239#define TEXASR_FS __MASK(63-36)
240#define SPRN_TFHAR 0x80
241#define SPRN_TIDR 144
242#define SPRN_CTRLF 0x088
243#define SPRN_CTRLT 0x098
244#define CTRL_CT 0xc0000000
245#define CTRL_CT0 0x80000000
246#define CTRL_CT1 0x40000000
247#define CTRL_TE 0x00c00000
248#define CTRL_RUNLATCH 0x1
249#define SPRN_DAWR 0xB4
250#define SPRN_RPR 0xBA
251#define SPRN_CIABR 0xBB
252#define CIABR_PRIV 0x3
253#define CIABR_PRIV_USER 1
254#define CIABR_PRIV_SUPER 2
255#define CIABR_PRIV_HYPER 3
256#define SPRN_DAWRX 0xBC
257#define DAWRX_USER __MASK(0)
258#define DAWRX_KERNEL __MASK(1)
259#define DAWRX_HYP __MASK(2)
260#define DAWRX_WTI __MASK(3)
261#define DAWRX_WT __MASK(4)
262#define DAWRX_DR __MASK(5)
263#define DAWRX_DW __MASK(6)
264#define SPRN_DABR 0x3F5
265#define SPRN_DABR2 0x13D
266#define SPRN_DABRX 0x3F7
267#define DABRX_USER __MASK(0)
268#define DABRX_KERNEL __MASK(1)
269#define DABRX_HYP __MASK(2)
270#define DABRX_BTI __MASK(3)
271#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
272#define SPRN_DAR 0x013
273#define SPRN_DBCR 0x136
274#define SPRN_DSISR 0x012
275#define DSISR_NOHPTE 0x40000000
276#define DSISR_PROTFAULT 0x08000000
277#define DSISR_BADACCESS 0x04000000
278#define DSISR_ISSTORE 0x02000000
279#define DSISR_DABRMATCH 0x00400000
280#define DSISR_NOSEGMENT 0x00200000
281#define DSISR_KEYFAULT 0x00200000
282#define DSISR_UNSUPP_MMU 0x00080000
283#define DSISR_SET_RC 0x00040000
284#define DSISR_PGDIRFAULT 0x00020000
285#define SPRN_TBRL 0x10C
286#define SPRN_TBRU 0x10D
287#define SPRN_CIR 0x11B
288#define SPRN_TBWL 0x11C
289#define SPRN_TBWU 0x11D
290#define SPRN_TBU40 0x11E
291#define SPRN_SPURR 0x134
292#define SPRN_HSPRG0 0x130
293#define SPRN_HSPRG1 0x131
294#define SPRN_HDSISR 0x132
295#define SPRN_HDAR 0x133
296#define SPRN_HDEC 0x136
297#define SPRN_HIOR 0x137
298#define SPRN_RMOR 0x138
299#define SPRN_HRMOR 0x139
300#define SPRN_HSRR0 0x13A
301#define SPRN_HSRR1 0x13B
302#define SPRN_ASDR 0x330
303#define SPRN_IC 0x350
304#define SPRN_VTB 0x351
305#define SPRN_LDBAR 0x352
306#define SPRN_PMICR 0x354
307#define SPRN_PMSR 0x355
308#define SPRN_PMMAR 0x356
309#define SPRN_PSSCR 0x357
310#define SPRN_PMCR 0x374
311
312
313#define FSCR_SCV_LG 12
314#define FSCR_MSGP_LG 10
315#define FSCR_TAR_LG 8
316#define FSCR_EBB_LG 7
317#define FSCR_TM_LG 5
318#define FSCR_BHRB_LG 4
319#define FSCR_PM_LG 3
320#define FSCR_DSCR_LG 2
321#define FSCR_VECVSX_LG 1
322#define FSCR_FP_LG 0
323#define SPRN_FSCR 0x099
324#define FSCR_SCV __MASK(FSCR_SCV_LG)
325#define FSCR_TAR __MASK(FSCR_TAR_LG)
326#define FSCR_EBB __MASK(FSCR_EBB_LG)
327#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
328#define SPRN_HFSCR 0xbe
329#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
330#define HFSCR_TAR __MASK(FSCR_TAR_LG)
331#define HFSCR_EBB __MASK(FSCR_EBB_LG)
332#define HFSCR_TM __MASK(FSCR_TM_LG)
333#define HFSCR_PM __MASK(FSCR_PM_LG)
334#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
335#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
336#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
337#define HFSCR_FP __MASK(FSCR_FP_LG)
338#define SPRN_TAR 0x32f
339#define SPRN_LPCR 0x13E
340#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
341#define LPCR_VPM1 ASM_CONST(0x4000000000000000)
342#define LPCR_ISL ASM_CONST(0x2000000000000000)
343#define LPCR_VC_SH 61
344#define LPCR_DPFD_SH 52
345#define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
346#define LPCR_VRMASD_SH 47
347#define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
348#define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
349#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
350#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
351#define LPCR_RMLS 0x1C000000
352#define LPCR_RMLS_SH 26
353#define LPCR_ILE ASM_CONST(0x0000000002000000)
354#define LPCR_AIL ASM_CONST(0x0000000001800000)
355#define LPCR_AIL_0 ASM_CONST(0x0000000000000000)
356#define LPCR_AIL_3 ASM_CONST(0x0000000001800000)
357#define LPCR_ONL ASM_CONST(0x0000000000040000)
358#define LPCR_LD ASM_CONST(0x0000000000020000)
359#define LPCR_PECE ASM_CONST(0x000000000001f000)
360#define LPCR_PECEDP ASM_CONST(0x0000000000010000)
361#define LPCR_PECEDH ASM_CONST(0x0000000000008000)
362#define LPCR_PECE0 ASM_CONST(0x0000000000004000)
363#define LPCR_PECE1 ASM_CONST(0x0000000000002000)
364#define LPCR_PECE2 ASM_CONST(0x0000000000001000)
365#define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000)
366#define LPCR_MER ASM_CONST(0x0000000000000800)
367#define LPCR_MER_SH 11
368#define LPCR_GTSE ASM_CONST(0x0000000000000400)
369#define LPCR_TC ASM_CONST(0x0000000000000200)
370#define LPCR_HEIC ASM_CONST(0x0000000000000010)
371#define LPCR_LPES 0x0000000c
372#define LPCR_LPES0 ASM_CONST(0x0000000000000008)
373#define LPCR_LPES1 ASM_CONST(0x0000000000000004)
374#define LPCR_LPES_SH 2
375#define LPCR_RMI ASM_CONST(0x0000000000000002)
376#define LPCR_HVICE ASM_CONST(0x0000000000000002)
377#define LPCR_HDICE ASM_CONST(0x0000000000000001)
378#define LPCR_UPRT ASM_CONST(0x0000000000400000)
379#define LPCR_HR ASM_CONST(0x0000000000100000)
380#ifndef SPRN_LPID
381#define SPRN_LPID 0x13F
382#endif
383#define LPID_RSVD 0x3ff
384#define SPRN_HMER 0x150
385#define SPRN_HMEER 0x151
386#define SPRN_PCR 0x152
387#define PCR_VEC_DIS (1ul << (63-0))
388#define PCR_VSX_DIS (1ul << (63-1))
389#define PCR_TM_DIS (1ul << (63-2))
390
391
392
393
394
395#define PCR_ARCH_207 0x8
396#define PCR_ARCH_206 0x4
397#define PCR_ARCH_205 0x2
398#define SPRN_HEIR 0x153
399#define SPRN_TLBINDEXR 0x154
400#define SPRN_TLBVPNR 0x155
401#define SPRN_TLBRPNR 0x156
402#define SPRN_TLBLPIDR 0x157
403#define SPRN_DBAT0L 0x219
404#define SPRN_DBAT0U 0x218
405#define SPRN_DBAT1L 0x21B
406#define SPRN_DBAT1U 0x21A
407#define SPRN_DBAT2L 0x21D
408#define SPRN_DBAT2U 0x21C
409#define SPRN_DBAT3L 0x21F
410#define SPRN_DBAT3U 0x21E
411#define SPRN_DBAT4L 0x239
412#define SPRN_DBAT4U 0x238
413#define SPRN_DBAT5L 0x23B
414#define SPRN_DBAT5U 0x23A
415#define SPRN_DBAT6L 0x23D
416#define SPRN_DBAT6U 0x23C
417#define SPRN_DBAT7L 0x23F
418#define SPRN_DBAT7U 0x23E
419#define SPRN_PPR 0x380
420#define SPRN_TSCR 0x399
421
422#define SPRN_DEC 0x016
423#define SPRN_DER 0x095
424#define DER_RSTE 0x40000000
425#define DER_CHSTPE 0x20000000
426#define DER_MCIE 0x10000000
427#define DER_EXTIE 0x02000000
428#define DER_ALIE 0x01000000
429#define DER_PRIE 0x00800000
430#define DER_FPUVIE 0x00400000
431#define DER_DECIE 0x00200000
432#define DER_SYSIE 0x00040000
433#define DER_TRE 0x00020000
434#define DER_SEIE 0x00004000
435#define DER_ITLBMSE 0x00002000
436#define DER_ITLBERE 0x00001000
437#define DER_DTLBMSE 0x00000800
438#define DER_DTLBERE 0x00000400
439#define DER_LBRKE 0x00000008
440#define DER_IBRKE 0x00000004
441#define DER_EBRKE 0x00000002
442#define DER_DPIE 0x00000001
443#define SPRN_DMISS 0x3D0
444#define SPRN_DHDES 0x0B1
445#define SPRN_DPDES 0x0B0
446#define SPRN_EAR 0x11A
447#define SPRN_HASH1 0x3D2
448#define SPRN_HASH2 0x3D3
449#define SPRN_HID0 0x3F0
450#define HID0_HDICE_SH (63 - 23)
451#define HID0_EMCP (1<<31)
452#define HID0_EBA (1<<29)
453#define HID0_EBD (1<<28)
454#define HID0_SBCLK (1<<27)
455#define HID0_EICE (1<<26)
456#define HID0_TBEN (1<<26)
457#define HID0_ECLK (1<<25)
458#define HID0_PAR (1<<24)
459#define HID0_STEN (1<<24)
460#define HID0_HIGH_BAT (1<<23)
461#define HID0_DOZE (1<<23)
462#define HID0_NAP (1<<22)
463#define HID0_SLEEP (1<<21)
464#define HID0_DPM (1<<20)
465#define HID0_BHTCLR (1<<18)
466#define HID0_XAEN (1<<17)
467#define HID0_NHR (1<<16)
468#define HID0_ICE (1<<15)
469#define HID0_DCE (1<<14)
470#define HID0_ILOCK (1<<13)
471#define HID0_DLOCK (1<<12)
472#define HID0_ICFI (1<<11)
473#define HID0_DCI (1<<10)
474#define HID0_SPD (1<<9)
475#define HID0_DAPUEN (1<<8)
476#define HID0_SGE (1<<7)
477#define HID0_SIED (1<<7)
478#define HID0_DCFA (1<<6)
479#define HID0_LRSTK (1<<4)
480#define HID0_BTIC (1<<5)
481#define HID0_ABE (1<<3)
482#define HID0_FOLD (1<<3)
483#define HID0_BHTE (1<<2)
484#define HID0_BTCD (1<<1)
485#define HID0_NOPDST (1<<1)
486#define HID0_NOPTI (1<<0)
487
488#define HID0_POWER8_4LPARMODE __MASK(61)
489#define HID0_POWER8_2LPARMODE __MASK(57)
490#define HID0_POWER8_1TO2LPAR __MASK(52)
491#define HID0_POWER8_1TO4LPAR __MASK(51)
492#define HID0_POWER8_DYNLPARDIS __MASK(48)
493
494
495#define HID0_POWER9_RADIX __MASK(63 - 8)
496
497#define SPRN_HID1 0x3F1
498#ifdef CONFIG_6xx
499#define HID1_EMCP (1<<31)
500#define HID1_DFS (1<<22)
501#define HID1_PC0 (1<<16)
502#define HID1_PC1 (1<<15)
503#define HID1_PC2 (1<<14)
504#define HID1_PC3 (1<<13)
505#define HID1_SYNCBE (1<<11)
506#define HID1_ABE (1<<10)
507#define HID1_PS (1<<16)
508#endif
509#define SPRN_HID2 0x3F8
510#define SPRN_HID2_GEKKO 0x398
511#define SPRN_IABR 0x3F2
512#define SPRN_IABR2 0x3FA
513#define SPRN_IBCR 0x135
514#define SPRN_IAMR 0x03D
515#define SPRN_HID4 0x3F4
516#define HID4_LPES0 (1ul << (63-0))
517#define HID4_RMLS2_SH (63 - 2)
518#define HID4_LPID5_SH (63 - 6)
519#define HID4_RMOR_SH (63 - 22)
520#define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
521#define HID4_LPES1 (1 << (63-57))
522#define HID4_RMLS0_SH (63 - 58)
523#define HID4_LPID1_SH 0
524#define SPRN_HID4_GEKKO 0x3F3
525#define SPRN_HID5 0x3F6
526#define SPRN_HID6 0x3F9
527#define HID6_LB (0x0F<<12)
528#define HID6_DLP (1<<20)
529#define SPRN_TSC_CELL 0x399
530#define TSC_CELL_DEC_ENABLE_0 0x400000
531#define TSC_CELL_DEC_ENABLE_1 0x200000
532#define TSC_CELL_EE_ENABLE 0x100000
533#define TSC_CELL_EE_BOOST 0x080000
534#define SPRN_TSC 0x3FD
535#define SPRN_TST 0x3FC
536#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
537#define SPRN_IAC1 0x3F4
538#define SPRN_IAC2 0x3F5
539#endif
540#define SPRN_IBAT0L 0x211
541#define SPRN_IBAT0U 0x210
542#define SPRN_IBAT1L 0x213
543#define SPRN_IBAT1U 0x212
544#define SPRN_IBAT2L 0x215
545#define SPRN_IBAT2U 0x214
546#define SPRN_IBAT3L 0x217
547#define SPRN_IBAT3U 0x216
548#define SPRN_IBAT4L 0x231
549#define SPRN_IBAT4U 0x230
550#define SPRN_IBAT5L 0x233
551#define SPRN_IBAT5U 0x232
552#define SPRN_IBAT6L 0x235
553#define SPRN_IBAT6U 0x234
554#define SPRN_IBAT7L 0x237
555#define SPRN_IBAT7U 0x236
556#define SPRN_ICMP 0x3D5
557#define SPRN_ICTC 0x3FB
558#ifndef SPRN_ICTRL
559#define SPRN_ICTRL 0x3F3
560#endif
561#define ICTRL_EICE 0x08000000
562#define ICTRL_EDC 0x04000000
563#define ICTRL_EICP 0x00000100
564#define SPRN_IMISS 0x3D4
565#define SPRN_IMMR 0x27E
566#define SPRN_L2CR 0x3F9
567#define SPRN_L2CR2 0x3f8
568#define L2CR_L2E 0x80000000
569#define L2CR_L2PE 0x40000000
570#define L2CR_L2SIZ_MASK 0x30000000
571#define L2CR_L2SIZ_256KB 0x10000000
572#define L2CR_L2SIZ_512KB 0x20000000
573#define L2CR_L2SIZ_1MB 0x30000000
574#define L2CR_L2CLK_MASK 0x0e000000
575#define L2CR_L2CLK_DISABLED 0x00000000
576#define L2CR_L2CLK_DIV1 0x02000000
577#define L2CR_L2CLK_DIV1_5 0x04000000
578#define L2CR_L2CLK_DIV2 0x08000000
579#define L2CR_L2CLK_DIV2_5 0x0a000000
580#define L2CR_L2CLK_DIV3 0x0c000000
581#define L2CR_L2RAM_MASK 0x01800000
582#define L2CR_L2RAM_FLOW 0x00000000
583#define L2CR_L2RAM_PIPE 0x01000000
584#define L2CR_L2RAM_PIPE_LW 0x01800000
585#define L2CR_L2DO 0x00400000
586#define L2CR_L2I 0x00200000
587#define L2CR_L2CTL 0x00100000
588#define L2CR_L2WT 0x00080000
589#define L2CR_L2TS 0x00040000
590#define L2CR_L2OH_MASK 0x00030000
591#define L2CR_L2OH_0_5 0x00000000
592#define L2CR_L2OH_1_0 0x00010000
593#define L2CR_L2SL 0x00008000
594#define L2CR_L2DF 0x00004000
595#define L2CR_L2BYP 0x00002000
596#define L2CR_L2IP 0x00000001
597#define L2CR_L2IO_745x 0x00100000
598#define L2CR_L2DO_745x 0x00010000
599#define L2CR_L2REP_745x 0x00001000
600#define L2CR_L2HWF_745x 0x00000800
601#define SPRN_L3CR 0x3FA
602#define L3CR_L3E 0x80000000
603#define L3CR_L3PE 0x40000000
604#define L3CR_L3APE 0x20000000
605#define L3CR_L3SIZ 0x10000000
606#define L3CR_L3CLKEN 0x08000000
607#define L3CR_L3RES 0x04000000
608#define L3CR_L3CLKDIV 0x03800000
609#define L3CR_L3IO 0x00400000
610#define L3CR_L3SPO 0x00040000
611#define L3CR_L3CKSP 0x00030000
612#define L3CR_L3PSP 0x0000e000
613#define L3CR_L3REP 0x00001000
614#define L3CR_L3HWF 0x00000800
615#define L3CR_L3I 0x00000400
616#define L3CR_L3RT 0x00000300
617#define L3CR_L3NIRCA 0x00000080
618#define L3CR_L3DO 0x00000040
619#define L3CR_PMEN 0x00000004
620#define L3CR_PMSIZ 0x00000001
621
622#define SPRN_MSSCR0 0x3f6
623#define SPRN_MSSSR0 0x3f7
624#define SPRN_LDSTCR 0x3f8
625#define SPRN_LDSTDB 0x3f4
626#define SPRN_LR 0x008
627#ifndef SPRN_PIR
628#define SPRN_PIR 0x3FF
629#endif
630#define SPRN_TIR 0x1BE
631#define SPRN_PTCR 0x1D0
632#define SPRN_PSPB 0x09F
633#define SPRN_PTEHI 0x3D5
634#define SPRN_PTELO 0x3D6
635#define SPRN_PURR 0x135
636#define SPRN_PVR 0x11F
637#define SPRN_RPA 0x3D6
638#define SPRN_SDA 0x3BF
639#define SPRN_SDR1 0x019
640#define SPRN_ASR 0x118
641#define SPRN_SIA 0x3BB
642#define SPRN_SPRG0 0x110
643#define SPRN_SPRG1 0x111
644#define SPRN_SPRG2 0x112
645#define SPRN_SPRG3 0x113
646#define SPRN_USPRG3 0x103
647#define SPRN_SPRG4 0x114
648#define SPRN_USPRG4 0x104
649#define SPRN_SPRG5 0x115
650#define SPRN_USPRG5 0x105
651#define SPRN_SPRG6 0x116
652#define SPRN_USPRG6 0x106
653#define SPRN_SPRG7 0x117
654#define SPRN_USPRG7 0x107
655#define SPRN_SRR0 0x01A
656#define SPRN_SRR1 0x01B
657#define SRR1_ISI_NOPT 0x40000000
658#define SRR1_ISI_N_OR_G 0x10000000
659#define SRR1_ISI_PROT 0x08000000
660#define SRR1_WAKEMASK 0x00380000
661#define SRR1_WAKEMASK_P8 0x003c0000
662#define SRR1_WAKEMCE_RESVD 0x003c0000
663#define SRR1_WAKESYSERR 0x00300000
664#define SRR1_WAKEEE 0x00200000
665#define SRR1_WAKEHVI 0x00240000
666#define SRR1_WAKEMT 0x00280000
667#define SRR1_WAKEHMI 0x00280000
668#define SRR1_WAKEDEC 0x00180000
669#define SRR1_WAKEDBELL 0x00140000
670#define SRR1_WAKETHERM 0x00100000
671#define SRR1_WAKERESET 0x00100000
672#define SRR1_WAKEHDBELL 0x000c0000
673#define SRR1_WAKESTATE 0x00030000
674#define SRR1_WS_DEEPEST 0x00030000
675
676#define SRR1_WS_DEEPER 0x00020000
677#define SRR1_WS_DEEP 0x00010000
678#define SRR1_PROGFPE 0x00100000
679#define SRR1_PROGILL 0x00080000
680#define SRR1_PROGPRIV 0x00040000
681#define SRR1_PROGTRAP 0x00020000
682#define SRR1_PROGADDR 0x00010000
683
684#define SPRN_HSRR0 0x13A
685#define SPRN_HSRR1 0x13B
686#define HSRR1_DENORM 0x00100000
687
688#define SPRN_TBCTL 0x35f
689#define TBCTL_FREEZE 0x0000000000000000ull
690#define TBCTL_RESTART 0x0000000100000000ull
691#define TBCTL_UPDATE_UPPER 0x0000000200000000ull
692#define TBCTL_UPDATE_LOWER 0x0000000300000000ull
693
694#ifndef SPRN_SVR
695#define SPRN_SVR 0x11E
696#endif
697#define SPRN_THRM1 0x3FC
698
699#define THRM1_TIN (1 << 31)
700#define THRM1_TIV (1 << 30)
701#define THRM1_THRES(x) ((x&0x7f)<<23)
702#define THRM3_SITV(x) ((x&0x3fff)<<1)
703#define THRM1_TID (1<<2)
704#define THRM1_TIE (1<<1)
705#define THRM1_V (1<<0)
706#define SPRN_THRM2 0x3FD
707#define SPRN_THRM3 0x3FE
708#define THRM3_E (1<<0)
709#define SPRN_TLBMISS 0x3D4
710#define SPRN_UMMCR0 0x3A8
711#define SPRN_UMMCR1 0x3AC
712#define SPRN_UPMC1 0x3A9
713#define SPRN_UPMC2 0x3AA
714#define SPRN_UPMC3 0x3AD
715#define SPRN_UPMC4 0x3AE
716#define SPRN_USIA 0x3AB
717#define SPRN_VRSAVE 0x100
718#define SPRN_XER 0x001
719
720#define SPRN_MMCR0_GEKKO 0x3B8
721#define SPRN_MMCR1_GEKKO 0x3BC
722#define SPRN_PMC1_GEKKO 0x3B9
723#define SPRN_PMC2_GEKKO 0x3BA
724#define SPRN_PMC3_GEKKO 0x3BD
725#define SPRN_PMC4_GEKKO 0x3BE
726#define SPRN_WPAR_GEKKO 0x399
727
728#define SPRN_SCOMC 0x114
729#define SPRN_SCOMD 0x115
730
731
732#ifdef CONFIG_PPC64
733#define SPRN_MMCR0 795
734#define MMCR0_FC 0x80000000UL
735#define MMCR0_FCS 0x40000000UL
736#define MMCR0_KERNEL_DISABLE MMCR0_FCS
737#define MMCR0_FCP 0x20000000UL
738#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
739#define MMCR0_FCM1 0x10000000UL
740#define MMCR0_FCM0 0x08000000UL
741#define MMCR0_PMXE ASM_CONST(0x04000000)
742#define MMCR0_FCECE ASM_CONST(0x02000000)
743#define MMCR0_TBEE 0x00400000UL
744#define MMCR0_BHRBA 0x00200000UL
745#define MMCR0_EBE 0x00100000UL
746#define MMCR0_PMCC 0x000c0000UL
747#define MMCR0_PMCC_U6 0x00080000UL
748#define MMCR0_PMC1CE 0x00008000UL
749#define MMCR0_PMCjCE ASM_CONST(0x00004000)
750#define MMCR0_TRIGGER 0x00002000UL
751#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800)
752#define MMCR0_C56RUN ASM_CONST(0x00000100)
753
754#define MMCR0_PMAO ASM_CONST(0x00000080)
755#define MMCR0_SHRFC 0x00000040UL
756#define MMCR0_FC56 0x00000010UL
757#define MMCR0_FCTI 0x00000008UL
758#define MMCR0_FCTA 0x00000004UL
759#define MMCR0_FCWAIT 0x00000002UL
760#define MMCR0_FCHV 0x00000001UL
761#define SPRN_MMCR1 798
762#define SPRN_MMCR2 785
763#define SPRN_UMMCR2 769
764#define SPRN_MMCRA 0x312
765#define MMCRA_SDSYNC 0x80000000UL
766#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
767#define MMCRA_SDAR_ERAT_MISS 0x20000000UL
768#define MMCRA_SIHV 0x10000000UL
769#define MMCRA_SIPR 0x08000000UL
770#define MMCRA_SLOT 0x07000000UL
771#define MMCRA_SLOT_SHIFT 24
772#define MMCRA_SAMPLE_ENABLE 0x00000001UL
773#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL
774#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
775#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
776#define POWER6_MMCRA_THRM 0x00000020UL
777#define POWER6_MMCRA_OTHER 0x0000000EUL
778
779#define POWER7P_MMCRA_SIAR_VALID 0x10000000
780#define POWER7P_MMCRA_SDAR_VALID 0x08000000
781
782#define SPRN_MMCRH 316
783#define SPRN_MMCRS 894
784#define SPRN_MMCRC 851
785#define SPRN_EBBHR 804
786#define SPRN_EBBRR 805
787#define SPRN_BESCR 806
788#define BESCR_GE 0x8000000000000000ULL
789#define SPRN_WORT 895
790#define SPRN_WORC 863
791
792#define SPRN_PMC1 787
793#define SPRN_PMC2 788
794#define SPRN_PMC3 789
795#define SPRN_PMC4 790
796#define SPRN_PMC5 791
797#define SPRN_PMC6 792
798#define SPRN_PMC7 793
799#define SPRN_PMC8 794
800#define SPRN_SIER 784
801#define SIER_SIPR 0x2000000
802#define SIER_SIHV 0x1000000
803#define SIER_SIAR_VALID 0x0400000
804#define SIER_SDAR_VALID 0x0200000
805#define SPRN_SIAR 796
806#define SPRN_SDAR 797
807#define SPRN_TACR 888
808#define SPRN_TCSCR 889
809#define SPRN_CSIGR 890
810#define SPRN_SPMC1 892
811#define SPRN_SPMC2 893
812
813
814#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
815#define MMCR2_USER_MASK 0x4020100804020000UL
816#define SIER_USER_MASK 0x7fffffUL
817
818#define SPRN_PA6T_MMCR0 795
819#define PA6T_MMCR0_EN0 0x0000000000000001UL
820#define PA6T_MMCR0_EN1 0x0000000000000002UL
821#define PA6T_MMCR0_EN2 0x0000000000000004UL
822#define PA6T_MMCR0_EN3 0x0000000000000008UL
823#define PA6T_MMCR0_EN4 0x0000000000000010UL
824#define PA6T_MMCR0_EN5 0x0000000000000020UL
825#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
826#define PA6T_MMCR0_PREN 0x0000000000000080UL
827#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
828#define PA6T_MMCR0_FCM0 0x0000000000000200UL
829#define PA6T_MMCR0_FCM1 0x0000000000000400UL
830#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
831#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
832#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
833#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
834#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
835#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
836#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
837#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
838#define PA6T_MMCR0_UOP 0x0000000000080000UL
839#define PA6T_MMCR0_TRG 0x0000000000100000UL
840#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
841#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
842#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
843#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
844#define PA6T_MMCR0_PROEN 0x0000000008000000UL
845#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
846#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
847#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
848#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
849#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
850#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
851#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
852#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
853#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
854#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
855#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
856#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
857#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
858
859#define SPRN_PA6T_MMCR1 798
860#define PA6T_MMCR1_ES2 0x00000000000000ffUL
861#define PA6T_MMCR1_ES3 0x000000000000ff00UL
862#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
863#define PA6T_MMCR1_ES5 0x00000000ff000000UL
864
865#define SPRN_PA6T_UPMC0 771
866#define SPRN_PA6T_UPMC1 772
867#define SPRN_PA6T_UPMC2 773
868#define SPRN_PA6T_UPMC3 774
869#define SPRN_PA6T_UPMC4 775
870#define SPRN_PA6T_UPMC5 776
871#define SPRN_PA6T_UMMCR0 779
872#define SPRN_PA6T_SIAR 780
873#define SPRN_PA6T_UMMCR1 782
874#define SPRN_PA6T_SIER 785
875#define SPRN_PA6T_PMC0 787
876#define SPRN_PA6T_PMC1 788
877#define SPRN_PA6T_PMC2 789
878#define SPRN_PA6T_PMC3 790
879#define SPRN_PA6T_PMC4 791
880#define SPRN_PA6T_PMC5 792
881#define SPRN_PA6T_TSR0 793
882#define SPRN_PA6T_TSR1 794
883#define SPRN_PA6T_TSR2 799
884#define SPRN_PA6T_TSR3 784
885
886#define SPRN_PA6T_IER 981
887#define SPRN_PA6T_DER 982
888#define SPRN_PA6T_BER 862
889#define SPRN_PA6T_MER 849
890
891#define SPRN_PA6T_IMA0 880
892#define SPRN_PA6T_IMA1 881
893#define SPRN_PA6T_IMA2 882
894#define SPRN_PA6T_IMA3 883
895#define SPRN_PA6T_IMA4 884
896#define SPRN_PA6T_IMA5 885
897#define SPRN_PA6T_IMA6 886
898#define SPRN_PA6T_IMA7 887
899#define SPRN_PA6T_IMA8 888
900#define SPRN_PA6T_IMA9 889
901#define SPRN_PA6T_BTCR 978
902#define SPRN_PA6T_IMAAT 979
903#define SPRN_PA6T_PCCR 1019
904#define SPRN_BKMK 1020
905#define SPRN_PA6T_RPCCR 1021
906
907
908#else
909#define SPRN_MMCR0 952
910#define MMCR0_FC 0x80000000UL
911#define MMCR0_FCS 0x40000000UL
912#define MMCR0_FCP 0x20000000UL
913#define MMCR0_FCM1 0x10000000UL
914#define MMCR0_FCM0 0x08000000UL
915#define MMCR0_PMXE 0x04000000UL
916#define MMCR0_FCECE 0x02000000UL
917#define MMCR0_TBEE 0x00400000UL
918#define MMCR0_PMC1CE 0x00008000UL
919#define MMCR0_PMCnCE 0x00004000UL
920#define MMCR0_TRIGGER 0x00002000UL
921#define MMCR0_PMC1SEL 0x00001fc0UL
922#define MMCR0_PMC2SEL 0x0000003fUL
923
924#define SPRN_MMCR1 956
925#define MMCR1_PMC3SEL 0xf8000000UL
926#define MMCR1_PMC4SEL 0x07c00000UL
927#define MMCR1_PMC5SEL 0x003e0000UL
928#define MMCR1_PMC6SEL 0x0001f800UL
929#define SPRN_MMCR2 944
930#define SPRN_PMC1 953
931#define SPRN_PMC2 954
932#define SPRN_PMC3 957
933#define SPRN_PMC4 958
934#define SPRN_PMC5 945
935#define SPRN_PMC6 946
936
937#define SPRN_SIAR 955
938
939
940#define MMCR0_PMC1_CYCLES (1 << 7)
941#define MMCR0_PMC1_ICACHEMISS (5 << 7)
942#define MMCR0_PMC1_DTLB (6 << 7)
943#define MMCR0_PMC2_DCACHEMISS 0x6
944#define MMCR0_PMC2_CYCLES 0x1
945#define MMCR0_PMC2_ITLB 0x7
946#define MMCR0_PMC2_LOADMISSTIME 0x5
947#endif
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1013#ifdef CONFIG_PPC64
1014#define SPRN_SPRG_PACA SPRN_SPRG1
1015#else
1016#define SPRN_SPRG_THREAD SPRN_SPRG3
1017#endif
1018
1019#ifdef CONFIG_PPC_BOOK3S_64
1020#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
1021#define SPRN_SPRG_HPACA SPRN_HSPRG0
1022#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
1023#define SPRN_SPRG_VDSO_READ SPRN_USPRG3
1024#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
1025
1026#define GET_PACA(rX) \
1027 BEGIN_FTR_SECTION_NESTED(66); \
1028 mfspr rX,SPRN_SPRG_PACA; \
1029 FTR_SECTION_ELSE_NESTED(66); \
1030 mfspr rX,SPRN_SPRG_HPACA; \
1031 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1032
1033#define SET_PACA(rX) \
1034 BEGIN_FTR_SECTION_NESTED(66); \
1035 mtspr SPRN_SPRG_PACA,rX; \
1036 FTR_SECTION_ELSE_NESTED(66); \
1037 mtspr SPRN_SPRG_HPACA,rX; \
1038 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1039
1040#define GET_SCRATCH0(rX) \
1041 BEGIN_FTR_SECTION_NESTED(66); \
1042 mfspr rX,SPRN_SPRG_SCRATCH0; \
1043 FTR_SECTION_ELSE_NESTED(66); \
1044 mfspr rX,SPRN_SPRG_HSCRATCH0; \
1045 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1046
1047#define SET_SCRATCH0(rX) \
1048 BEGIN_FTR_SECTION_NESTED(66); \
1049 mtspr SPRN_SPRG_SCRATCH0,rX; \
1050 FTR_SECTION_ELSE_NESTED(66); \
1051 mtspr SPRN_SPRG_HSCRATCH0,rX; \
1052 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1053
1054#else
1055#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
1056#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
1057
1058#endif
1059
1060#ifdef CONFIG_PPC_BOOK3E_64
1061#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
1062#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
1063#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
1064#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
1065#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
1066#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
1067#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1068#define SPRN_SPRG_VDSO_READ SPRN_USPRG7
1069#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
1070
1071#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
1072#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
1073
1074#endif
1075
1076#ifdef CONFIG_PPC_BOOK3S_32
1077#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1078#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1079#define SPRN_SPRG_RTAS SPRN_SPRG2
1080#define SPRN_SPRG_603_LRU SPRN_SPRG4
1081#endif
1082
1083#ifdef CONFIG_40x
1084#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1085#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1086#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1087#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
1088#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
1089#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
1090#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
1091#endif
1092
1093#ifdef CONFIG_BOOKE
1094#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
1095#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
1096#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
1097#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
1098#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1099#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1100#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
1101#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
1102#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
1103#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1104#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
1105#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
1106#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
1107#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
1108#ifdef CONFIG_E200
1109#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
1110#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
1111#else
1112#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
1113#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
1114#endif
1115#endif
1116
1117#ifdef CONFIG_8xx
1118#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1119#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1120#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1121#endif
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131#ifdef CONFIG_PPC64
1132#define MTFSF_L(REG) \
1133 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1134#else
1135#define MTFSF_L(REG) mtfsf 0xff, (REG)
1136#endif
1137
1138
1139
1140#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
1141#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF)
1142
1143#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1144
1145
1146
1147
1148
1149
1150#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF)
1151#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF)
1152#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF)
1153#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF)
1154#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF)
1155#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF)
1156
1157
1158
1159#define PVR_403GA 0x00200000
1160#define PVR_403GB 0x00200100
1161#define PVR_403GC 0x00200200
1162#define PVR_403GCX 0x00201400
1163#define PVR_405GP 0x40110000
1164#define PVR_476 0x11a52000
1165#define PVR_476FPE 0x7ff50000
1166#define PVR_STB03XXX 0x40310000
1167#define PVR_NP405H 0x41410000
1168#define PVR_NP405L 0x41610000
1169#define PVR_601 0x00010000
1170#define PVR_602 0x00050000
1171#define PVR_603 0x00030000
1172#define PVR_603e 0x00060000
1173#define PVR_603ev 0x00070000
1174#define PVR_603r 0x00071000
1175#define PVR_604 0x00040000
1176#define PVR_604e 0x00090000
1177#define PVR_604r 0x000A0000
1178#define PVR_620 0x00140000
1179#define PVR_740 0x00080000
1180#define PVR_750 PVR_740
1181#define PVR_740P 0x10080000
1182#define PVR_750P PVR_740P
1183#define PVR_7400 0x000C0000
1184#define PVR_7410 0x800C0000
1185#define PVR_7450 0x80000000
1186#define PVR_8540 0x80200000
1187#define PVR_8560 0x80200000
1188#define PVR_VER_E500V1 0x8020
1189#define PVR_VER_E500V2 0x8021
1190#define PVR_VER_E500MC 0x8023
1191#define PVR_VER_E5500 0x8024
1192#define PVR_VER_E6500 0x8040
1193
1194
1195
1196
1197
1198
1199
1200#define PVR_821 0x00500000
1201#define PVR_823 PVR_821
1202#define PVR_850 PVR_821
1203#define PVR_860 PVR_821
1204#define PVR_8240 0x00810100
1205#define PVR_8245 0x80811014
1206#define PVR_8260 PVR_8240
1207
1208
1209#define PVR_476_ISS 0x00052000
1210
1211
1212#define PVR_NORTHSTAR 0x0033
1213#define PVR_PULSAR 0x0034
1214#define PVR_POWER4 0x0035
1215#define PVR_ICESTAR 0x0036
1216#define PVR_SSTAR 0x0037
1217#define PVR_POWER4p 0x0038
1218#define PVR_970 0x0039
1219#define PVR_POWER5 0x003A
1220#define PVR_POWER5p 0x003B
1221#define PVR_970FX 0x003C
1222#define PVR_POWER6 0x003E
1223#define PVR_POWER7 0x003F
1224#define PVR_630 0x0040
1225#define PVR_630p 0x0041
1226#define PVR_970MP 0x0044
1227#define PVR_970GX 0x0045
1228#define PVR_POWER7p 0x004A
1229#define PVR_POWER8E 0x004B
1230#define PVR_POWER8NVL 0x004C
1231#define PVR_POWER8 0x004D
1232#define PVR_POWER9 0x004E
1233#define PVR_BE 0x0070
1234#define PVR_PA6T 0x0090
1235
1236
1237#define PVR_ARCH_204 0x0f000001
1238#define PVR_ARCH_205 0x0f000002
1239#define PVR_ARCH_206 0x0f000003
1240#define PVR_ARCH_206p 0x0f100003
1241#define PVR_ARCH_207 0x0f000004
1242#define PVR_ARCH_300 0x0f000005
1243
1244
1245#ifndef __ASSEMBLY__
1246#define mfmsr() ({unsigned long rval; \
1247 asm volatile("mfmsr %0" : "=r" (rval) : \
1248 : "memory"); rval;})
1249#ifdef CONFIG_PPC_BOOK3S_64
1250#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1251 : : "r" (v) : "memory")
1252#define mtmsr(v) __mtmsrd((v), 0)
1253#define __MTMSR "mtmsrd"
1254#else
1255#define mtmsr(v) asm volatile("mtmsr %0" : \
1256 : "r" ((unsigned long)(v)) \
1257 : "memory")
1258#define __MTMSR "mtmsr"
1259#endif
1260
1261static inline void mtmsr_isync(unsigned long val)
1262{
1263 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1264 "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1265}
1266
1267#define mfspr(rn) ({unsigned long rval; \
1268 asm volatile("mfspr %0," __stringify(rn) \
1269 : "=r" (rval)); rval;})
1270#ifndef mtspr
1271#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1272 : "r" ((unsigned long)(v)) \
1273 : "memory")
1274#endif
1275#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \
1276 : : "memory")
1277
1278extern unsigned long msr_check_and_set(unsigned long bits);
1279extern bool strict_msr_control;
1280extern void __msr_check_and_clear(unsigned long bits);
1281static inline void msr_check_and_clear(unsigned long bits)
1282{
1283 if (strict_msr_control)
1284 __msr_check_and_clear(bits);
1285}
1286
1287#ifdef __powerpc64__
1288#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1289#define mftb() ({unsigned long rval; \
1290 asm volatile( \
1291 "90: mfspr %0, %2;\n" \
1292 "97: cmpwi %0,0;\n" \
1293 " beq- 90b;\n" \
1294 "99:\n" \
1295 ".section __ftr_fixup,\"a\"\n" \
1296 ".align 3\n" \
1297 "98:\n" \
1298 " .llong %1\n" \
1299 " .llong %1\n" \
1300 " .llong 97b-98b\n" \
1301 " .llong 99b-98b\n" \
1302 " .llong 0\n" \
1303 " .llong 0\n" \
1304 ".previous" \
1305 : "=r" (rval) \
1306 : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
1307 rval;})
1308#else
1309#define mftb() ({unsigned long rval; \
1310 asm volatile("mfspr %0, %1" : \
1311 "=r" (rval) : "i" (SPRN_TBRL)); rval;})
1312#endif
1313
1314#else
1315
1316#if defined(CONFIG_8xx)
1317#define mftbl() ({unsigned long rval; \
1318 asm volatile("mftbl %0" : "=r" (rval)); rval;})
1319#define mftbu() ({unsigned long rval; \
1320 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1321#else
1322#define mftbl() ({unsigned long rval; \
1323 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1324 "i" (SPRN_TBRL)); rval;})
1325#define mftbu() ({unsigned long rval; \
1326 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1327 "i" (SPRN_TBRU)); rval;})
1328#endif
1329#define mftb() mftbl()
1330#endif
1331
1332#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
1333#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
1334
1335#ifdef CONFIG_PPC32
1336#define mfsrin(v) ({unsigned int rval; \
1337 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1338 rval;})
1339#endif
1340
1341#define proc_trap() asm volatile("trap")
1342
1343extern unsigned long current_stack_pointer(void);
1344
1345extern unsigned long scom970_read(unsigned int address);
1346extern void scom970_write(unsigned int address, unsigned long value);
1347
1348struct pt_regs;
1349
1350extern void ppc_save_regs(struct pt_regs *regs);
1351
1352static inline void update_power8_hid0(unsigned long hid0)
1353{
1354
1355
1356
1357
1358
1359 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
1360}
1361#endif
1362#endif
1363#endif
1364