LXR linux/arch/powerpc/kernel/dma.c

   1/*
   2 * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation
   3 *
   4 * Provide default implementations of the DMA mapping callbacks for
   5 * directly mapped busses.
   6 */
   7
   8#include <linux/device.h>
   9#include <linux/dma-mapping.h>
  10#include <linux/dma-debug.h>
  11#include <linux/gfp.h>
  12#include <linux/memblock.h>
  13#include <linux/export.h>
  14#include <linux/pci.h>
  15#include <asm/vio.h>
  16#include <asm/bug.h>
  17#include <asm/machdep.h>
  18#include <asm/swiotlb.h>
  19#include <asm/iommu.h>
  20
  21/*
  22 * Generic direct DMA implementation
  23 *
  24 * This implementation supports a per-device offset that can be applied if
  25 * the address at which memory is visible to devices is not 0. Platform code
  26 * can set archdata.dma_data to an unsigned long holding the offset. By
  27 * default the offset is PCI_DRAM_OFFSET.
  28 */
  29
  30static u64 __maybe_unused get_pfn_limit(struct device *dev)
  31{
  32        u64 pfn = (dev->coherent_dma_mask >> PAGE_SHIFT) + 1;
  33        struct dev_archdata __maybe_unused *sd = &dev->archdata;
  34
  35#ifdef CONFIG_SWIOTLB
  36        if (sd->max_direct_dma_addr && dev->dma_ops == &swiotlb_dma_ops)
  37                pfn = min_t(u64, pfn, sd->max_direct_dma_addr >> PAGE_SHIFT);
  38#endif
  39
  40        return pfn;
  41}
  42
  43static int dma_direct_dma_supported(struct device *dev, u64 mask)
  44{
  45#ifdef CONFIG_PPC64
  46        u64 limit = get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
  47
  48        /* Limit fits in the mask, we are good */
  49        if (mask >= limit)
  50                return 1;
  51
  52#ifdef CONFIG_FSL_SOC
  53        /* Freescale gets another chance via ZONE_DMA/ZONE_DMA32, however
  54         * that will have to be refined if/when they support iommus
  55         */
  56        return 1;
  57#endif
  58        /* Sorry ... */
  59        return 0;
  60#else
  61        return 1;
  62#endif
  63}
  64
  65void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
  66                                  dma_addr_t *dma_handle, gfp_t flag,
  67                                  unsigned long attrs)
  68{
  69        void *ret;
  70#ifdef CONFIG_NOT_COHERENT_CACHE
  71        ret = __dma_alloc_coherent(dev, size, dma_handle, flag);
  72        if (ret == NULL)
  73                return NULL;
  74        *dma_handle += get_dma_offset(dev);
  75        return ret;
  76#else
  77        struct page *page;
  78        int node = dev_to_node(dev);
  79#ifdef CONFIG_FSL_SOC
  80        u64 pfn = get_pfn_limit(dev);
  81        int zone;
  82
  83        /*
  84         * This code should be OK on other platforms, but we have drivers that
  85         * don't set coherent_dma_mask. As a workaround we just ifdef it. This
  86         * whole routine needs some serious cleanup.
  87         */
  88
  89        zone = dma_pfn_limit_to_zone(pfn);
  90        if (zone < 0) {
  91                dev_err(dev, "%s: No suitable zone for pfn %#llx\n",
  92                        __func__, pfn);
  93                return NULL;
  94        }
  95
  96        switch (zone) {
  97        case ZONE_DMA:
  98                flag |= GFP_DMA;
  99                break;
 100#ifdef CONFIG_ZONE_DMA32
 101        case ZONE_DMA32:
 102                flag |= GFP_DMA32;
 103                break;
 104#endif
 105        };
 106#endif /* CONFIG_FSL_SOC */
 107
 108        /* ignore region specifiers */
 109        flag  &= ~(__GFP_HIGHMEM);
 110
 111        page = alloc_pages_node(node, flag, get_order(size));
 112        if (page == NULL)
 113                return NULL;
 114        ret = page_address(page);
 115        memset(ret, 0, size);
 116        *dma_handle = __pa(ret) + get_dma_offset(dev);
 117
 118        return ret;
 119#endif
 120}
 121
 122void __dma_direct_free_coherent(struct device *dev, size_t size,
 123                                void *vaddr, dma_addr_t dma_handle,
 124                                unsigned long attrs)
 125{
 126#ifdef CONFIG_NOT_COHERENT_CACHE
 127        __dma_free_coherent(size, vaddr);
 128#else
 129        free_pages((unsigned long)vaddr, get_order(size));
 130#endif
 131}
 132
 133static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
 134                                       dma_addr_t *dma_handle, gfp_t flag,
 135                                       unsigned long attrs)
 136{
 137        struct iommu_table *iommu;
 138
 139        /* The coherent mask may be smaller than the real mask, check if
 140         * we can really use the direct ops
 141         */
 142        if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
 143                return __dma_direct_alloc_coherent(dev, size, dma_handle,
 144                                                   flag, attrs);
 145
 146        /* Ok we can't ... do we have an iommu ? If not, fail */
 147        iommu = get_iommu_table_base(dev);
 148        if (!iommu)
 149                return NULL;
 150
 151        /* Try to use the iommu */
 152        return iommu_alloc_coherent(dev, iommu, size, dma_handle,
 153                                    dev->coherent_dma_mask, flag,
 154                                    dev_to_node(dev));
 155}
 156
 157static void dma_direct_free_coherent(struct device *dev, size_t size,
 158                                     void *vaddr, dma_addr_t dma_handle,
 159                                     unsigned long attrs)
 160{
 161        struct iommu_table *iommu;
 162
 163        /* See comments in dma_direct_alloc_coherent() */
 164        if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
 165                return __dma_direct_free_coherent(dev, size, vaddr, dma_handle,
 166                                                  attrs);
 167        /* Maybe we used an iommu ... */
 168        iommu = get_iommu_table_base(dev);
 169
 170        /* If we hit that we should have never allocated in the first
 171         * place so how come we are freeing ?
 172         */
 173        if (WARN_ON(!iommu))
 174                return;
 175        iommu_free_coherent(iommu, size, vaddr, dma_handle);
 176}
 177
 178int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
 179                             void *cpu_addr, dma_addr_t handle, size_t size,
 180                             unsigned long attrs)
 181{
 182        unsigned long pfn;
 183
 184#ifdef CONFIG_NOT_COHERENT_CACHE
 185        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 186        pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
 187#else
 188        pfn = page_to_pfn(virt_to_page(cpu_addr));
 189#endif
 190        return remap_pfn_range(vma, vma->vm_start,
 191                               pfn + vma->vm_pgoff,
 192                               vma->vm_end - vma->vm_start,
 193                               vma->vm_page_prot);
 194}
 195
 196static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
 197                             int nents, enum dma_data_direction direction,
 198                             unsigned long attrs)
 199{
 200        struct scatterlist *sg;
 201        int i;
 202
 203        for_each_sg(sgl, sg, nents, i) {
 204                sg->dma_address = sg_phys(sg) + get_dma_offset(dev);
 205                sg->dma_length = sg->length;
 206
 207                if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
 208                        continue;
 209
 210                __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
 211        }
 212
 213        return nents;
 214}
 215
 216static void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sg,
 217                                int nents, enum dma_data_direction direction,
 218                                unsigned long attrs)
 219{
 220}
 221
 222static u64 dma_direct_get_required_mask(struct device *dev)
 223{
 224        u64 end, mask;
 225
 226        end = memblock_end_of_DRAM() + get_dma_offset(dev);
 227
 228        mask = 1ULL << (fls64(end) - 1);
 229        mask += mask - 1;
 230
 231        return mask;
 232}
 233
 234static inline dma_addr_t dma_direct_map_page(struct device *dev,
 235                                             struct page *page,
 236                                             unsigned long offset,
 237                                             size_t size,
 238                                             enum dma_data_direction dir,
 239                                             unsigned long attrs)
 240{
 241        BUG_ON(dir == DMA_NONE);
 242
 243        if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
 244                __dma_sync_page(page, offset, size, dir);
 245
 246        return page_to_phys(page) + offset + get_dma_offset(dev);
 247}
 248
 249static inline void dma_direct_unmap_page(struct device *dev,
 250                                         dma_addr_t dma_address,
 251                                         size_t size,
 252                                         enum dma_data_direction direction,
 253                                         unsigned long attrs)
 254{
 255}
 256
 257#ifdef CONFIG_NOT_COHERENT_CACHE
 258static inline void dma_direct_sync_sg(struct device *dev,
 259                struct scatterlist *sgl, int nents,
 260                enum dma_data_direction direction)
 261{
 262        struct scatterlist *sg;
 263        int i;
 264
 265        for_each_sg(sgl, sg, nents, i)
 266                __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
 267}
 268
 269static inline void dma_direct_sync_single(struct device *dev,
 270                                          dma_addr_t dma_handle, size_t size,
 271                                          enum dma_data_direction direction)
 272{
 273        __dma_sync(bus_to_virt(dma_handle), size, direction);
 274}
 275#endif
 276
 277const struct dma_map_ops dma_direct_ops = {
 278        .alloc                          = dma_direct_alloc_coherent,
 279        .free                           = dma_direct_free_coherent,
 280        .mmap                           = dma_direct_mmap_coherent,
 281        .map_sg                         = dma_direct_map_sg,
 282        .unmap_sg                       = dma_direct_unmap_sg,
 283        .dma_supported                  = dma_direct_dma_supported,
 284        .map_page                       = dma_direct_map_page,
 285        .unmap_page                     = dma_direct_unmap_page,
 286        .get_required_mask              = dma_direct_get_required_mask,
 287#ifdef CONFIG_NOT_COHERENT_CACHE
 288        .sync_single_for_cpu            = dma_direct_sync_single,
 289        .sync_single_for_device         = dma_direct_sync_single,
 290        .sync_sg_for_cpu                = dma_direct_sync_sg,
 291        .sync_sg_for_device             = dma_direct_sync_sg,
 292#endif
 293};
 294EXPORT_SYMBOL(dma_direct_ops);
 295
 296int dma_set_coherent_mask(struct device *dev, u64 mask)
 297{
 298        if (!dma_supported(dev, mask)) {
 299                /*
 300                 * We need to special case the direct DMA ops which can
 301                 * support a fallback for coherent allocations. There
 302                 * is no dma_op->set_coherent_mask() so we have to do
 303                 * things the hard way:
 304                 */
 305                if (get_dma_ops(dev) != &dma_direct_ops ||
 306                    get_iommu_table_base(dev) == NULL ||
 307                    !dma_iommu_dma_supported(dev, mask))
 308                        return -EIO;
 309        }
 310        dev->coherent_dma_mask = mask;
 311        return 0;
 312}
 313EXPORT_SYMBOL(dma_set_coherent_mask);
 314
 315#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
 316
 317int dma_set_mask(struct device *dev, u64 dma_mask)
 318{
 319        if (ppc_md.dma_set_mask)
 320                return ppc_md.dma_set_mask(dev, dma_mask);
 321
 322        if (dev_is_pci(dev)) {
 323                struct pci_dev *pdev = to_pci_dev(dev);
 324                struct pci_controller *phb = pci_bus_to_host(pdev->bus);
 325                if (phb->controller_ops.dma_set_mask)
 326                        return phb->controller_ops.dma_set_mask(pdev, dma_mask);
 327        }
 328
 329        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
 330                return -EIO;
 331        *dev->dma_mask = dma_mask;
 332        return 0;
 333}
 334EXPORT_SYMBOL(dma_set_mask);
 335
 336u64 __dma_get_required_mask(struct device *dev)
 337{
 338        const struct dma_map_ops *dma_ops = get_dma_ops(dev);
 339
 340        if (unlikely(dma_ops == NULL))
 341                return 0;
 342
 343        if (dma_ops->get_required_mask)
 344                return dma_ops->get_required_mask(dev);
 345
 346        return DMA_BIT_MASK(8 * sizeof(dma_addr_t));
 347}
 348
 349u64 dma_get_required_mask(struct device *dev)
 350{
 351        if (ppc_md.dma_get_required_mask)
 352                return ppc_md.dma_get_required_mask(dev);
 353
 354        if (dev_is_pci(dev)) {
 355                struct pci_dev *pdev = to_pci_dev(dev);
 356                struct pci_controller *phb = pci_bus_to_host(pdev->bus);
 357                if (phb->controller_ops.dma_get_required_mask)
 358                        return phb->controller_ops.dma_get_required_mask(pdev);
 359        }
 360
 361        return __dma_get_required_mask(dev);
 362}
 363EXPORT_SYMBOL_GPL(dma_get_required_mask);
 364
 365static int __init dma_init(void)
 366{
 367        dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
 368#ifdef CONFIG_PCI
 369        dma_debug_add_bus(&pci_bus_type);
 370#endif
 371#ifdef CONFIG_IBMVIO
 372        dma_debug_add_bus(&vio_bus_type);
 373#endif
 374
 375       return 0;
 376}
 377fs_initcall(dma_init);
 378
 379