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17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/seq_file.h>
28#include <linux/initrd.h>
29#include <linux/interrupt.h>
30#include <linux/fsl_devices.h>
31#include <linux/of_platform.h>
32
33#include <asm/pgtable.h>
34#include <asm/page.h>
35#include <linux/atomic.h>
36#include <asm/time.h>
37#include <asm/io.h>
38#include <asm/machdep.h>
39#include <asm/ipic.h>
40#include <asm/pci-bridge.h>
41#include <asm/irq.h>
42#include <mm/mmu_decl.h>
43#include <asm/prom.h>
44#include <asm/udbg.h>
45#include <asm/mpic.h>
46
47#include <sysdev/fsl_soc.h>
48#include <sysdev/fsl_pci.h>
49
50#include "mpc85xx.h"
51
52static int sbc_rev;
53
54static void __init sbc8548_pic_init(void)
55{
56 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
57 0, 256, " OpenPIC ");
58 BUG_ON(mpic == NULL);
59 mpic_init(mpic);
60}
61
62
63static int __init sbc8548_hw_rev(void)
64{
65 struct device_node *np;
66 struct resource res;
67 unsigned int *rev;
68 int board_rev = 0;
69
70 np = of_find_compatible_node(NULL, NULL, "hw-rev");
71 if (np == NULL) {
72 printk("No HW-REV found in DTB.\n");
73 return -ENODEV;
74 }
75
76 of_address_to_resource(np, 0, &res);
77 of_node_put(np);
78
79 rev = ioremap(res.start,sizeof(unsigned int));
80 board_rev = (*rev) >> 28;
81 iounmap(rev);
82
83 return board_rev;
84}
85
86
87
88
89static void __init sbc8548_setup_arch(void)
90{
91 if (ppc_md.progress)
92 ppc_md.progress("sbc8548_setup_arch()", 0);
93
94 fsl_pci_assign_primary();
95
96 sbc_rev = sbc8548_hw_rev();
97}
98
99static void sbc8548_show_cpuinfo(struct seq_file *m)
100{
101 uint pvid, svid, phid1;
102
103 pvid = mfspr(SPRN_PVR);
104 svid = mfspr(SPRN_SVR);
105
106 seq_printf(m, "Vendor\t\t: Wind River\n");
107 seq_printf(m, "Machine\t\t: SBC8548 v%d\n", sbc_rev);
108 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
109 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
110
111
112 phid1 = mfspr(SPRN_HID1);
113 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
114}
115
116machine_arch_initcall(sbc8548, mpc85xx_common_publish_devices);
117
118
119
120
121static int __init sbc8548_probe(void)
122{
123 return of_machine_is_compatible("SBC8548");
124}
125
126define_machine(sbc8548) {
127 .name = "SBC8548",
128 .probe = sbc8548_probe,
129 .setup_arch = sbc8548_setup_arch,
130 .init_IRQ = sbc8548_pic_init,
131 .show_cpuinfo = sbc8548_show_cpuinfo,
132 .get_irq = mpic_get_irq,
133#ifdef CONFIG_PCI
134 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
135 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
136#endif
137 .calibrate_decr = generic_calibrate_decr,
138 .progress = udbg_progress,
139};
140