LXR linux/arch/sparc/include/asm/mbus.h

   1/*
   2 * mbus.h:  Various defines for MBUS modules.
   3 *
   4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5 */
   6
   7#ifndef _SPARC_MBUS_H
   8#define _SPARC_MBUS_H
   9
  10#include <asm/ross.h>    /* HyperSparc stuff */
  11#include <asm/viking.h>  /* Ugh, bug city... */
  12
  13enum mbus_module {
  14        HyperSparc        = 0,
  15        Swift_ok          = 4,
  16        Swift_bad_c       = 5,
  17        Swift_lots_o_bugs = 6,
  18        Tsunami           = 7,
  19        Viking_12         = 8,
  20        Viking_2x         = 9,
  21        Viking_30         = 10,
  22        Viking_35         = 11,
  23        Viking_new        = 12,
  24        TurboSparc        = 13,
  25        SRMMU_INVAL_MOD   = 14,
  26};
  27
  28extern enum mbus_module srmmu_modtype;
  29extern unsigned int viking_rev, swift_rev, cypress_rev;
  30
  31/* HW Mbus module bugs we have to deal with */
  32#define HWBUG_COPYBACK_BROKEN        0x00000001
  33#define HWBUG_ASIFLUSH_BROKEN        0x00000002
  34#define HWBUG_VACFLUSH_BITROT        0x00000004
  35#define HWBUG_KERN_ACCBROKEN         0x00000008
  36#define HWBUG_KERN_CBITBROKEN        0x00000010
  37#define HWBUG_MODIFIED_BITROT        0x00000020
  38#define HWBUG_PC_BADFAULT_ADDR       0x00000040
  39#define HWBUG_SUPERSCALAR_BAD        0x00000080
  40#define HWBUG_PACINIT_BITROT         0x00000100
  41
  42/* First the module type values. To find out which you have, just load
  43 * the mmu control register from ASI_M_MMUREG alternate address space and
  44 * shift the value right 28 bits.
  45 */
  46/* IMPL field means the company which produced the chip. */
  47#define MBUS_VIKING        0x4   /* bleech, Texas Instruments Module */
  48#define MBUS_LSI           0x3   /* LSI Logics */
  49#define MBUS_ROSS          0x1   /* Ross is nice */
  50#define MBUS_FMI           0x0   /* Fujitsu Microelectronics/Swift */
  51
  52/* Ross Module versions */
  53#define ROSS_604_REV_CDE        0x0   /* revisions c, d, and e */
  54#define ROSS_604_REV_F          0x1   /* revision f */
  55#define ROSS_605                0xf   /* revision a, a.1, and a.2 */
  56#define ROSS_605_REV_B          0xe   /* revision b */
  57
  58/* TI Viking Module versions */
  59#define VIKING_REV_12           0x1   /* Version 1.2 or SPARCclassic's CPU */
  60#define VIKING_REV_2            0x2   /* Version 2.1, 2.2, 2.3, and 2.4 */
  61#define VIKING_REV_30           0x3   /* Version 3.0 */
  62#define VIKING_REV_35           0x4   /* Version 3.5 */
  63
  64/* LSI Logics. */
  65#define LSI_L64815              0x0
  66
  67/* Fujitsu */
  68#define FMI_AURORA              0x4   /* MB8690x, a Swift module... */
  69#define FMI_TURBO               0x5   /* MB86907, a TurboSparc module... */
  70
  71/* For multiprocessor support we need to be able to obtain the CPU id and
  72 * the MBUS Module id.
  73 */
  74
  75/* The CPU ID is encoded in the trap base register, 20 bits to the left of
  76 * bit zero, with 2 bits being significant.
  77 */
  78#define TBR_ID_SHIFT            20
  79
  80static inline int get_cpuid(void)
  81{
  82        register int retval;
  83        __asm__ __volatile__("rd %%tbr, %0\n\t"
  84                             "srl %0, %1, %0\n\t" :
  85                             "=r" (retval) :
  86                             "i" (TBR_ID_SHIFT));
  87        return (retval & 3);
  88}
  89
  90static inline int get_modid(void)
  91{
  92        return (get_cpuid() | 0x8);
  93}
  94
  95        
  96#endif /* !(_SPARC_MBUS_H) */
  97