LXR linux/arch/x86/include/asm/pci

   1/*
   2 *      Low-Level PCI Access for i386 machines.
   3 *
   4 *      (c) 1999 Martin Mares <mj@ucw.cz>
   5 */
   6
   7#include <linux/ioport.h>
   8
   9#undef DEBUG
  10
  11#ifdef DEBUG
  12#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
  13#else
  14#define DBG(fmt, ...)                           \
  15do {                                            \
  16        if (0)                                  \
  17                printk(fmt, ##__VA_ARGS__);     \
  18} while (0)
  19#endif
  20
  21#define PCI_PROBE_BIOS          0x0001
  22#define PCI_PROBE_CONF1         0x0002
  23#define PCI_PROBE_CONF2         0x0004
  24#define PCI_PROBE_MMCONF        0x0008
  25#define PCI_PROBE_MASK          0x000f
  26#define PCI_PROBE_NOEARLY       0x0010
  27
  28#define PCI_NO_CHECKS           0x0400
  29#define PCI_USE_PIRQ_MASK       0x0800
  30#define PCI_ASSIGN_ROMS         0x1000
  31#define PCI_BIOS_IRQ_SCAN       0x2000
  32#define PCI_ASSIGN_ALL_BUSSES   0x4000
  33#define PCI_CAN_SKIP_ISA_ALIGN  0x8000
  34#define PCI_USE__CRS            0x10000
  35#define PCI_CHECK_ENABLE_AMD_MMCONF     0x20000
  36#define PCI_HAS_IO_ECS          0x40000
  37#define PCI_NOASSIGN_ROMS       0x80000
  38#define PCI_ROOT_NO_CRS         0x100000
  39#define PCI_NOASSIGN_BARS       0x200000
  40
  41extern unsigned int pci_probe;
  42extern unsigned long pirq_table_addr;
  43
  44enum pci_bf_sort_state {
  45        pci_bf_sort_default,
  46        pci_force_nobf,
  47        pci_force_bf,
  48        pci_dmi_bf,
  49};
  50
  51/* pci-i386.c */
  52
  53void pcibios_resource_survey(void);
  54void pcibios_set_cache_line_size(void);
  55
  56/* pci-pc.c */
  57
  58extern int pcibios_last_bus;
  59extern struct pci_ops pci_root_ops;
  60
  61void pcibios_scan_specific_bus(int busn);
  62
  63/* pci-irq.c */
  64
  65struct irq_info {
  66        u8 bus, devfn;                  /* Bus, device and function */
  67        struct {
  68                u8 link;                /* IRQ line ID, chipset dependent,
  69                                           0 = not routed */
  70                u16 bitmap;             /* Available IRQs */
  71        } __attribute__((packed)) irq[4];
  72        u8 slot;                        /* Slot number, 0=onboard */
  73        u8 rfu;
  74} __attribute__((packed));
  75
  76struct irq_routing_table {
  77        u32 signature;                  /* PIRQ_SIGNATURE should be here */
  78        u16 version;                    /* PIRQ_VERSION */
  79        u16 size;                       /* Table size in bytes */
  80        u8 rtr_bus, rtr_devfn;          /* Where the interrupt router lies */
  81        u16 exclusive_irqs;             /* IRQs devoted exclusively to
  82                                           PCI usage */
  83        u16 rtr_vendor, rtr_device;     /* Vendor and device ID of
  84                                           interrupt router */
  85        u32 miniport_data;              /* Crap */
  86        u8 rfu[11];
  87        u8 checksum;                    /* Modulo 256 checksum must give 0 */
  88        struct irq_info slots[0];
  89} __attribute__((packed));
  90
  91extern unsigned int pcibios_irq_mask;
  92
  93extern raw_spinlock_t pci_config_lock;
  94
  95extern int (*pcibios_enable_irq)(struct pci_dev *dev);
  96extern void (*pcibios_disable_irq)(struct pci_dev *dev);
  97
  98extern bool mp_should_keep_irq(struct device *dev);
  99
 100struct pci_raw_ops {
 101        int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
 102                                                int reg, int len, u32 *val);
 103        int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
 104                                                int reg, int len, u32 val);
 105};
 106
 107extern const struct pci_raw_ops *raw_pci_ops;
 108extern const struct pci_raw_ops *raw_pci_ext_ops;
 109
 110extern const struct pci_raw_ops pci_mmcfg;
 111extern const struct pci_raw_ops pci_direct_conf1;
 112extern bool port_cf9_safe;
 113
 114/* arch_initcall level */
 115extern int pci_direct_probe(void);
 116extern void pci_direct_init(int type);
 117extern void pci_pcbios_init(void);
 118extern void __init dmi_check_pciprobe(void);
 119extern void __init dmi_check_skip_isa_align(void);
 120
 121/* some common used subsys_initcalls */
 122extern int __init pci_acpi_init(void);
 123extern void __init pcibios_irq_init(void);
 124extern int __init pcibios_init(void);
 125extern int pci_legacy_init(void);
 126extern void pcibios_fixup_irqs(void);
 127
 128/* pci-mmconfig.c */
 129
 130/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
 131#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
 132
 133struct pci_mmcfg_region {
 134        struct list_head list;
 135        struct resource res;
 136        u64 address;
 137        char __iomem *virt;
 138        u16 segment;
 139        u8 start_bus;
 140        u8 end_bus;
 141        char name[PCI_MMCFG_RESOURCE_NAME_LEN];
 142};
 143
 144extern int __init pci_mmcfg_arch_init(void);
 145extern void __init pci_mmcfg_arch_free(void);
 146extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
 147extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
 148extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
 149                               phys_addr_t addr);
 150extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
 151extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
 152
 153extern struct list_head pci_mmcfg_list;
 154
 155#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)
 156
 157/*
 158 * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
 159 * %eax.  No other source or target registers may be used.  The following
 160 * mmio_config_* accessors enforce this.  See "BIOS and Kernel Developer's
 161 * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
 162 * "MMIO Configuration Coding Requirements".
 163 */
 164static inline unsigned char mmio_config_readb(void __iomem *pos)
 165{
 166        u8 val;
 167        asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
 168        return val;
 169}
 170
 171static inline unsigned short mmio_config_readw(void __iomem *pos)
 172{
 173        u16 val;
 174        asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
 175        return val;
 176}
 177
 178static inline unsigned int mmio_config_readl(void __iomem *pos)
 179{
 180        u32 val;
 181        asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
 182        return val;
 183}
 184
 185static inline void mmio_config_writeb(void __iomem *pos, u8 val)
 186{
 187        asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
 188}
 189
 190static inline void mmio_config_writew(void __iomem *pos, u16 val)
 191{
 192        asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
 193}
 194
 195static inline void mmio_config_writel(void __iomem *pos, u32 val)
 196{
 197        asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
 198}
 199
 200#ifdef CONFIG_PCI
 201# ifdef CONFIG_ACPI
 202#  define x86_default_pci_init          pci_acpi_init
 203# else
 204#  define x86_default_pci_init          pci_legacy_init
 205# endif
 206# define x86_default_pci_init_irq       pcibios_irq_init
 207# define x86_default_pci_fixup_irqs     pcibios_fixup_irqs
 208#else
 209# define x86_default_pci_init           NULL
 210# define x86_default_pci_init_irq       NULL
 211# define x86_default_pci_fixup_irqs     NULL
 212#endif
 213