1#ifndef _ASM_X86_SPECIAL_INSNS_H
2#define _ASM_X86_SPECIAL_INSNS_H
3
4
5#ifdef __KERNEL__
6
7#include <asm/nops.h>
8
9
10
11
12
13
14
15
16extern unsigned long __force_order;
17
18static inline unsigned long native_read_cr0(void)
19{
20 unsigned long val;
21 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
22 return val;
23}
24
25static inline void native_write_cr0(unsigned long val)
26{
27 asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
28}
29
30static inline unsigned long native_read_cr2(void)
31{
32 unsigned long val;
33 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
34 return val;
35}
36
37static inline void native_write_cr2(unsigned long val)
38{
39 asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
40}
41
42static inline unsigned long __native_read_cr3(void)
43{
44 unsigned long val;
45 asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
46 return val;
47}
48
49static inline void native_write_cr3(unsigned long val)
50{
51 asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
52}
53
54static inline unsigned long native_read_cr4(void)
55{
56 unsigned long val;
57#ifdef CONFIG_X86_32
58
59
60
61
62
63 asm volatile("1: mov %%cr4, %0\n"
64 "2:\n"
65 _ASM_EXTABLE(1b, 2b)
66 : "=r" (val), "=m" (__force_order) : "0" (0));
67#else
68
69 asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
70#endif
71 return val;
72}
73
74static inline void native_write_cr4(unsigned long val)
75{
76 asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
77}
78
79#ifdef CONFIG_X86_64
80static inline unsigned long native_read_cr8(void)
81{
82 unsigned long cr8;
83 asm volatile("movq %%cr8,%0" : "=r" (cr8));
84 return cr8;
85}
86
87static inline void native_write_cr8(unsigned long val)
88{
89 asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
90}
91#endif
92
93#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
94static inline u32 __read_pkru(void)
95{
96 u32 ecx = 0;
97 u32 edx, pkru;
98
99
100
101
102
103 asm volatile(".byte 0x0f,0x01,0xee\n\t"
104 : "=a" (pkru), "=d" (edx)
105 : "c" (ecx));
106 return pkru;
107}
108
109static inline void __write_pkru(u32 pkru)
110{
111 u32 ecx = 0, edx = 0;
112
113
114
115
116
117 asm volatile(".byte 0x0f,0x01,0xef\n\t"
118 : : "a" (pkru), "c"(ecx), "d"(edx));
119}
120#else
121static inline u32 __read_pkru(void)
122{
123 return 0;
124}
125
126static inline void __write_pkru(u32 pkru)
127{
128}
129#endif
130
131static inline void native_wbinvd(void)
132{
133 asm volatile("wbinvd": : :"memory");
134}
135
136extern asmlinkage void native_load_gs_index(unsigned);
137
138#ifdef CONFIG_PARAVIRT
139#include <asm/paravirt.h>
140#else
141
142static inline unsigned long read_cr0(void)
143{
144 return native_read_cr0();
145}
146
147static inline void write_cr0(unsigned long x)
148{
149 native_write_cr0(x);
150}
151
152static inline unsigned long read_cr2(void)
153{
154 return native_read_cr2();
155}
156
157static inline void write_cr2(unsigned long x)
158{
159 native_write_cr2(x);
160}
161
162
163
164
165
166static inline unsigned long __read_cr3(void)
167{
168 return __native_read_cr3();
169}
170
171static inline void write_cr3(unsigned long x)
172{
173 native_write_cr3(x);
174}
175
176static inline unsigned long __read_cr4(void)
177{
178 return native_read_cr4();
179}
180
181static inline void __write_cr4(unsigned long x)
182{
183 native_write_cr4(x);
184}
185
186static inline void wbinvd(void)
187{
188 native_wbinvd();
189}
190
191#ifdef CONFIG_X86_64
192
193static inline unsigned long read_cr8(void)
194{
195 return native_read_cr8();
196}
197
198static inline void write_cr8(unsigned long x)
199{
200 native_write_cr8(x);
201}
202
203static inline void load_gs_index(unsigned selector)
204{
205 native_load_gs_index(selector);
206}
207
208#endif
209
210#endif
211
212static inline void clflush(volatile void *__p)
213{
214 asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
215}
216
217static inline void clflushopt(volatile void *__p)
218{
219 alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
220 ".byte 0x66; clflush %P0",
221 X86_FEATURE_CLFLUSHOPT,
222 "+m" (*(volatile char __force *)__p));
223}
224
225static inline void clwb(volatile void *__p)
226{
227 volatile struct { char x[64]; } *p = __p;
228
229 asm volatile(ALTERNATIVE_2(
230 ".byte " __stringify(NOP_DS_PREFIX) "; clflush (%[pax])",
231 ".byte 0x66; clflush (%[pax])",
232 X86_FEATURE_CLFLUSHOPT,
233 ".byte 0x66, 0x0f, 0xae, 0x30",
234 X86_FEATURE_CLWB)
235 : [p] "+m" (*p)
236 : [pax] "a" (p));
237}
238
239#define nop() asm volatile ("nop")
240
241
242#endif
243
244#endif
245