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24#ifndef VMX_H
25#define VMX_H
26
27
28#include <linux/bitops.h>
29#include <linux/types.h>
30#include <uapi/asm/vmx.h>
31
32
33
34
35#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
36#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
37#define CPU_BASED_HLT_EXITING 0x00000080
38#define CPU_BASED_INVLPG_EXITING 0x00000200
39#define CPU_BASED_MWAIT_EXITING 0x00000400
40#define CPU_BASED_RDPMC_EXITING 0x00000800
41#define CPU_BASED_RDTSC_EXITING 0x00001000
42#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
43#define CPU_BASED_CR3_STORE_EXITING 0x00010000
44#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
45#define CPU_BASED_CR8_STORE_EXITING 0x00100000
46#define CPU_BASED_TPR_SHADOW 0x00200000
47#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
48#define CPU_BASED_MOV_DR_EXITING 0x00800000
49#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
50#define CPU_BASED_USE_IO_BITMAPS 0x02000000
51#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
52#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
53#define CPU_BASED_MONITOR_EXITING 0x20000000
54#define CPU_BASED_PAUSE_EXITING 0x40000000
55#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
56
57#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
58
59
60
61
62#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
63#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
64#define SECONDARY_EXEC_DESC 0x00000004
65#define SECONDARY_EXEC_RDTSCP 0x00000008
66#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
67#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
68#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
69#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
70#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
71#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
72#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
73#define SECONDARY_EXEC_RDRAND 0x00000800
74#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
75#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
76#define SECONDARY_EXEC_RDSEED 0x00010000
77#define SECONDARY_EXEC_ENABLE_PML 0x00020000
78#define SECONDARY_EXEC_XSAVES 0x00100000
79#define SECONDARY_EXEC_TSC_SCALING 0x02000000
80
81#define PIN_BASED_EXT_INTR_MASK 0x00000001
82#define PIN_BASED_NMI_EXITING 0x00000008
83#define PIN_BASED_VIRTUAL_NMIS 0x00000020
84#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
85#define PIN_BASED_POSTED_INTR 0x00000080
86
87#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
88
89#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
90#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
91#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
92#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
93#define VM_EXIT_SAVE_IA32_PAT 0x00040000
94#define VM_EXIT_LOAD_IA32_PAT 0x00080000
95#define VM_EXIT_SAVE_IA32_EFER 0x00100000
96#define VM_EXIT_LOAD_IA32_EFER 0x00200000
97#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
98#define VM_EXIT_CLEAR_BNDCFGS 0x00800000
99
100#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
101
102#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
103#define VM_ENTRY_IA32E_MODE 0x00000200
104#define VM_ENTRY_SMM 0x00000400
105#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
106#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
107#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
108#define VM_ENTRY_LOAD_IA32_EFER 0x00008000
109#define VM_ENTRY_LOAD_BNDCFGS 0x00010000
110
111#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
112
113#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
114#define VMX_MISC_SAVE_EFER_LMA 0x00000020
115#define VMX_MISC_ACTIVITY_HLT 0x00000040
116
117static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
118{
119 return vmx_basic & GENMASK_ULL(30, 0);
120}
121
122static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
123{
124 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
125}
126
127static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
128{
129 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
130}
131
132static inline int vmx_misc_cr3_count(u64 vmx_misc)
133{
134 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
135}
136
137static inline int vmx_misc_max_msr(u64 vmx_misc)
138{
139 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
140}
141
142static inline int vmx_misc_mseg_revid(u64 vmx_misc)
143{
144 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
145}
146
147
148enum vmcs_field {
149 VIRTUAL_PROCESSOR_ID = 0x00000000,
150 POSTED_INTR_NV = 0x00000002,
151 GUEST_ES_SELECTOR = 0x00000800,
152 GUEST_CS_SELECTOR = 0x00000802,
153 GUEST_SS_SELECTOR = 0x00000804,
154 GUEST_DS_SELECTOR = 0x00000806,
155 GUEST_FS_SELECTOR = 0x00000808,
156 GUEST_GS_SELECTOR = 0x0000080a,
157 GUEST_LDTR_SELECTOR = 0x0000080c,
158 GUEST_TR_SELECTOR = 0x0000080e,
159 GUEST_INTR_STATUS = 0x00000810,
160 GUEST_PML_INDEX = 0x00000812,
161 HOST_ES_SELECTOR = 0x00000c00,
162 HOST_CS_SELECTOR = 0x00000c02,
163 HOST_SS_SELECTOR = 0x00000c04,
164 HOST_DS_SELECTOR = 0x00000c06,
165 HOST_FS_SELECTOR = 0x00000c08,
166 HOST_GS_SELECTOR = 0x00000c0a,
167 HOST_TR_SELECTOR = 0x00000c0c,
168 IO_BITMAP_A = 0x00002000,
169 IO_BITMAP_A_HIGH = 0x00002001,
170 IO_BITMAP_B = 0x00002002,
171 IO_BITMAP_B_HIGH = 0x00002003,
172 MSR_BITMAP = 0x00002004,
173 MSR_BITMAP_HIGH = 0x00002005,
174 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
175 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
176 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
177 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
178 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
179 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
180 PML_ADDRESS = 0x0000200e,
181 PML_ADDRESS_HIGH = 0x0000200f,
182 TSC_OFFSET = 0x00002010,
183 TSC_OFFSET_HIGH = 0x00002011,
184 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
185 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
186 APIC_ACCESS_ADDR = 0x00002014,
187 APIC_ACCESS_ADDR_HIGH = 0x00002015,
188 POSTED_INTR_DESC_ADDR = 0x00002016,
189 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
190 EPT_POINTER = 0x0000201a,
191 EPT_POINTER_HIGH = 0x0000201b,
192 EOI_EXIT_BITMAP0 = 0x0000201c,
193 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
194 EOI_EXIT_BITMAP1 = 0x0000201e,
195 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
196 EOI_EXIT_BITMAP2 = 0x00002020,
197 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
198 EOI_EXIT_BITMAP3 = 0x00002022,
199 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
200 VMREAD_BITMAP = 0x00002026,
201 VMWRITE_BITMAP = 0x00002028,
202 XSS_EXIT_BITMAP = 0x0000202C,
203 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
204 TSC_MULTIPLIER = 0x00002032,
205 TSC_MULTIPLIER_HIGH = 0x00002033,
206 GUEST_PHYSICAL_ADDRESS = 0x00002400,
207 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
208 VMCS_LINK_POINTER = 0x00002800,
209 VMCS_LINK_POINTER_HIGH = 0x00002801,
210 GUEST_IA32_DEBUGCTL = 0x00002802,
211 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
212 GUEST_IA32_PAT = 0x00002804,
213 GUEST_IA32_PAT_HIGH = 0x00002805,
214 GUEST_IA32_EFER = 0x00002806,
215 GUEST_IA32_EFER_HIGH = 0x00002807,
216 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
217 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
218 GUEST_PDPTR0 = 0x0000280a,
219 GUEST_PDPTR0_HIGH = 0x0000280b,
220 GUEST_PDPTR1 = 0x0000280c,
221 GUEST_PDPTR1_HIGH = 0x0000280d,
222 GUEST_PDPTR2 = 0x0000280e,
223 GUEST_PDPTR2_HIGH = 0x0000280f,
224 GUEST_PDPTR3 = 0x00002810,
225 GUEST_PDPTR3_HIGH = 0x00002811,
226 GUEST_BNDCFGS = 0x00002812,
227 GUEST_BNDCFGS_HIGH = 0x00002813,
228 HOST_IA32_PAT = 0x00002c00,
229 HOST_IA32_PAT_HIGH = 0x00002c01,
230 HOST_IA32_EFER = 0x00002c02,
231 HOST_IA32_EFER_HIGH = 0x00002c03,
232 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
233 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
234 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
235 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
236 EXCEPTION_BITMAP = 0x00004004,
237 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
238 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
239 CR3_TARGET_COUNT = 0x0000400a,
240 VM_EXIT_CONTROLS = 0x0000400c,
241 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
242 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
243 VM_ENTRY_CONTROLS = 0x00004012,
244 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
245 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
246 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
247 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
248 TPR_THRESHOLD = 0x0000401c,
249 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
250 PLE_GAP = 0x00004020,
251 PLE_WINDOW = 0x00004022,
252 VM_INSTRUCTION_ERROR = 0x00004400,
253 VM_EXIT_REASON = 0x00004402,
254 VM_EXIT_INTR_INFO = 0x00004404,
255 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
256 IDT_VECTORING_INFO_FIELD = 0x00004408,
257 IDT_VECTORING_ERROR_CODE = 0x0000440a,
258 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
259 VMX_INSTRUCTION_INFO = 0x0000440e,
260 GUEST_ES_LIMIT = 0x00004800,
261 GUEST_CS_LIMIT = 0x00004802,
262 GUEST_SS_LIMIT = 0x00004804,
263 GUEST_DS_LIMIT = 0x00004806,
264 GUEST_FS_LIMIT = 0x00004808,
265 GUEST_GS_LIMIT = 0x0000480a,
266 GUEST_LDTR_LIMIT = 0x0000480c,
267 GUEST_TR_LIMIT = 0x0000480e,
268 GUEST_GDTR_LIMIT = 0x00004810,
269 GUEST_IDTR_LIMIT = 0x00004812,
270 GUEST_ES_AR_BYTES = 0x00004814,
271 GUEST_CS_AR_BYTES = 0x00004816,
272 GUEST_SS_AR_BYTES = 0x00004818,
273 GUEST_DS_AR_BYTES = 0x0000481a,
274 GUEST_FS_AR_BYTES = 0x0000481c,
275 GUEST_GS_AR_BYTES = 0x0000481e,
276 GUEST_LDTR_AR_BYTES = 0x00004820,
277 GUEST_TR_AR_BYTES = 0x00004822,
278 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
279 GUEST_ACTIVITY_STATE = 0X00004826,
280 GUEST_SYSENTER_CS = 0x0000482A,
281 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
282 HOST_IA32_SYSENTER_CS = 0x00004c00,
283 CR0_GUEST_HOST_MASK = 0x00006000,
284 CR4_GUEST_HOST_MASK = 0x00006002,
285 CR0_READ_SHADOW = 0x00006004,
286 CR4_READ_SHADOW = 0x00006006,
287 CR3_TARGET_VALUE0 = 0x00006008,
288 CR3_TARGET_VALUE1 = 0x0000600a,
289 CR3_TARGET_VALUE2 = 0x0000600c,
290 CR3_TARGET_VALUE3 = 0x0000600e,
291 EXIT_QUALIFICATION = 0x00006400,
292 GUEST_LINEAR_ADDRESS = 0x0000640a,
293 GUEST_CR0 = 0x00006800,
294 GUEST_CR3 = 0x00006802,
295 GUEST_CR4 = 0x00006804,
296 GUEST_ES_BASE = 0x00006806,
297 GUEST_CS_BASE = 0x00006808,
298 GUEST_SS_BASE = 0x0000680a,
299 GUEST_DS_BASE = 0x0000680c,
300 GUEST_FS_BASE = 0x0000680e,
301 GUEST_GS_BASE = 0x00006810,
302 GUEST_LDTR_BASE = 0x00006812,
303 GUEST_TR_BASE = 0x00006814,
304 GUEST_GDTR_BASE = 0x00006816,
305 GUEST_IDTR_BASE = 0x00006818,
306 GUEST_DR7 = 0x0000681a,
307 GUEST_RSP = 0x0000681c,
308 GUEST_RIP = 0x0000681e,
309 GUEST_RFLAGS = 0x00006820,
310 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
311 GUEST_SYSENTER_ESP = 0x00006824,
312 GUEST_SYSENTER_EIP = 0x00006826,
313 HOST_CR0 = 0x00006c00,
314 HOST_CR3 = 0x00006c02,
315 HOST_CR4 = 0x00006c04,
316 HOST_FS_BASE = 0x00006c06,
317 HOST_GS_BASE = 0x00006c08,
318 HOST_TR_BASE = 0x00006c0a,
319 HOST_GDTR_BASE = 0x00006c0c,
320 HOST_IDTR_BASE = 0x00006c0e,
321 HOST_IA32_SYSENTER_ESP = 0x00006c10,
322 HOST_IA32_SYSENTER_EIP = 0x00006c12,
323 HOST_RSP = 0x00006c14,
324 HOST_RIP = 0x00006c16,
325};
326
327
328
329
330#define INTR_INFO_VECTOR_MASK 0xff
331#define INTR_INFO_INTR_TYPE_MASK 0x700
332#define INTR_INFO_DELIVER_CODE_MASK 0x800
333#define INTR_INFO_UNBLOCK_NMI 0x1000
334#define INTR_INFO_VALID_MASK 0x80000000
335#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
336
337#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
338#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
339#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
340#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
341
342#define INTR_TYPE_EXT_INTR (0 << 8)
343#define INTR_TYPE_NMI_INTR (2 << 8)
344#define INTR_TYPE_HARD_EXCEPTION (3 << 8)
345#define INTR_TYPE_SOFT_INTR (4 << 8)
346#define INTR_TYPE_SOFT_EXCEPTION (6 << 8)
347
348
349#define GUEST_INTR_STATE_STI 0x00000001
350#define GUEST_INTR_STATE_MOV_SS 0x00000002
351#define GUEST_INTR_STATE_SMI 0x00000004
352#define GUEST_INTR_STATE_NMI 0x00000008
353
354
355#define GUEST_ACTIVITY_ACTIVE 0
356#define GUEST_ACTIVITY_HLT 1
357#define GUEST_ACTIVITY_SHUTDOWN 2
358#define GUEST_ACTIVITY_WAIT_SIPI 3
359
360
361
362
363#define CONTROL_REG_ACCESS_NUM 0x7
364#define CONTROL_REG_ACCESS_TYPE 0x30
365#define CONTROL_REG_ACCESS_REG 0xf00
366#define LMSW_SOURCE_DATA_SHIFT 16
367#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT)
368#define REG_EAX (0 << 8)
369#define REG_ECX (1 << 8)
370#define REG_EDX (2 << 8)
371#define REG_EBX (3 << 8)
372#define REG_ESP (4 << 8)
373#define REG_EBP (5 << 8)
374#define REG_ESI (6 << 8)
375#define REG_EDI (7 << 8)
376#define REG_R8 (8 << 8)
377#define REG_R9 (9 << 8)
378#define REG_R10 (10 << 8)
379#define REG_R11 (11 << 8)
380#define REG_R12 (12 << 8)
381#define REG_R13 (13 << 8)
382#define REG_R14 (14 << 8)
383#define REG_R15 (15 << 8)
384
385
386
387
388#define DEBUG_REG_ACCESS_NUM 0x7
389#define DEBUG_REG_ACCESS_TYPE 0x10
390#define TYPE_MOV_TO_DR (0 << 4)
391#define TYPE_MOV_FROM_DR (1 << 4)
392#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf)
393
394
395
396
397
398#define APIC_ACCESS_OFFSET 0xfff
399#define APIC_ACCESS_TYPE 0xf000
400#define TYPE_LINEAR_APIC_INST_READ (0 << 12)
401#define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
402#define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
403#define TYPE_LINEAR_APIC_EVENT (3 << 12)
404#define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
405#define TYPE_PHYSICAL_APIC_INST (15 << 12)
406
407
408#define VMX_SEGMENT_AR_L_MASK (1 << 13)
409
410#define VMX_AR_TYPE_ACCESSES_MASK 1
411#define VMX_AR_TYPE_READABLE_MASK (1 << 1)
412#define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
413#define VMX_AR_TYPE_CODE_MASK (1 << 3)
414#define VMX_AR_TYPE_MASK 0x0f
415#define VMX_AR_TYPE_BUSY_64_TSS 11
416#define VMX_AR_TYPE_BUSY_32_TSS 11
417#define VMX_AR_TYPE_BUSY_16_TSS 3
418#define VMX_AR_TYPE_LDT 2
419
420#define VMX_AR_UNUSABLE_MASK (1 << 16)
421#define VMX_AR_S_MASK (1 << 4)
422#define VMX_AR_P_MASK (1 << 7)
423#define VMX_AR_L_MASK (1 << 13)
424#define VMX_AR_DB_MASK (1 << 14)
425#define VMX_AR_G_MASK (1 << 15)
426#define VMX_AR_DPL_SHIFT 5
427#define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
428
429#define VMX_AR_RESERVD_MASK 0xfffe0f00
430
431#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
432#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
433#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
434
435#define VMX_NR_VPIDS (1 << 16)
436#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
437#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
438#define VMX_VPID_EXTENT_ALL_CONTEXT 2
439#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
440
441#define VMX_EPT_EXTENT_CONTEXT 1
442#define VMX_EPT_EXTENT_GLOBAL 2
443#define VMX_EPT_EXTENT_SHIFT 24
444
445#define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
446#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
447#define VMX_EPTP_UC_BIT (1ull << 8)
448#define VMX_EPTP_WB_BIT (1ull << 14)
449#define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
450#define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
451#define VMX_EPT_INVEPT_BIT (1ull << 20)
452#define VMX_EPT_AD_BIT (1ull << 21)
453#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
454#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
455
456#define VMX_VPID_INVVPID_BIT (1ull << 0)
457#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8)
458#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9)
459#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10)
460#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11)
461
462#define VMX_EPT_DEFAULT_GAW 3
463#define VMX_EPT_MAX_GAW 0x4
464#define VMX_EPT_MT_EPTE_SHIFT 3
465#define VMX_EPT_GAW_EPTP_SHIFT 3
466#define VMX_EPT_AD_ENABLE_BIT (1ull << 6)
467#define VMX_EPT_DEFAULT_MT 0x6ull
468#define VMX_EPT_READABLE_MASK 0x1ull
469#define VMX_EPT_WRITABLE_MASK 0x2ull
470#define VMX_EPT_EXECUTABLE_MASK 0x4ull
471#define VMX_EPT_IPAT_BIT (1ull << 6)
472#define VMX_EPT_ACCESS_BIT (1ull << 8)
473#define VMX_EPT_DIRTY_BIT (1ull << 9)
474#define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
475 VMX_EPT_WRITABLE_MASK | \
476 VMX_EPT_EXECUTABLE_MASK)
477#define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
478
479
480#define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
481 VMX_EPT_EXECUTABLE_MASK)
482
483#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
484
485
486#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
487#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
488#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
489#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
490#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
491#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
492#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
493#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
494#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
495#define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
496#define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
497
498struct vmx_msr_entry {
499 u32 index;
500 u32 reserved;
501 u64 value;
502} __aligned(16);
503
504
505
506
507#define ENTRY_FAIL_DEFAULT 0
508#define ENTRY_FAIL_PDPTE 2
509#define ENTRY_FAIL_NMI 3
510#define ENTRY_FAIL_VMCS_LINK_PTR 4
511
512
513
514
515#define EPT_VIOLATION_ACC_READ_BIT 0
516#define EPT_VIOLATION_ACC_WRITE_BIT 1
517#define EPT_VIOLATION_ACC_INSTR_BIT 2
518#define EPT_VIOLATION_READABLE_BIT 3
519#define EPT_VIOLATION_WRITABLE_BIT 4
520#define EPT_VIOLATION_EXECUTABLE_BIT 5
521#define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
522#define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
523#define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
524#define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
525#define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT)
526#define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT)
527#define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT)
528#define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
529
530
531
532
533enum vm_instruction_error_number {
534 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
535 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
536 VMXERR_VMCLEAR_VMXON_POINTER = 3,
537 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
538 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
539 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
540 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
541 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
542 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
543 VMXERR_VMPTRLD_VMXON_POINTER = 10,
544 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
545 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
546 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
547 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
548 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
549 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
550 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
551 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
552 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
553 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
554 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
555 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
556 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
557 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
558 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
559};
560
561#endif
562
