1#include <linux/export.h>
2#include <linux/bitops.h>
3#include <linux/elf.h>
4#include <linux/mm.h>
5
6#include <linux/io.h>
7#include <linux/sched.h>
8#include <linux/sched/clock.h>
9#include <linux/random.h>
10#include <asm/processor.h>
11#include <asm/apic.h>
12#include <asm/cpu.h>
13#include <asm/smp.h>
14#include <asm/pci-direct.h>
15#include <asm/delay.h>
16
17#ifdef CONFIG_X86_64
18# include <asm/mmconfig.h>
19# include <asm/set_memory.h>
20#endif
21
22#include "cpu.h"
23
24static const int amd_erratum_383[];
25static const int amd_erratum_400[];
26static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
27
28
29
30
31
32
33static u32 nodes_per_socket = 1;
34
35static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
36{
37 u32 gprs[8] = { 0 };
38 int err;
39
40 WARN_ONCE((boot_cpu_data.x86 != 0xf),
41 "%s should only be used on K8!\n", __func__);
42
43 gprs[1] = msr;
44 gprs[7] = 0x9c5a203a;
45
46 err = rdmsr_safe_regs(gprs);
47
48 *p = gprs[0] | ((u64)gprs[2] << 32);
49
50 return err;
51}
52
53static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
54{
55 u32 gprs[8] = { 0 };
56
57 WARN_ONCE((boot_cpu_data.x86 != 0xf),
58 "%s should only be used on K8!\n", __func__);
59
60 gprs[0] = (u32)val;
61 gprs[1] = msr;
62 gprs[2] = val >> 32;
63 gprs[7] = 0x9c5a203a;
64
65 return wrmsr_safe_regs(gprs);
66}
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82extern __visible void vide(void);
83__asm__(".globl vide\n"
84 ".type vide, @function\n"
85 ".align 4\n"
86 "vide: ret\n");
87
88static void init_amd_k5(struct cpuinfo_x86 *c)
89{
90#ifdef CONFIG_X86_32
91
92
93
94
95
96
97#define CBAR (0xfffc)
98#define CBAR_ENB (0x80000000)
99#define CBAR_KEY (0X000000CB)
100 if (c->x86_model == 9 || c->x86_model == 10) {
101 if (inl(CBAR) & CBAR_ENB)
102 outl(0 | CBAR_KEY, CBAR);
103 }
104#endif
105}
106
107static void init_amd_k6(struct cpuinfo_x86 *c)
108{
109#ifdef CONFIG_X86_32
110 u32 l, h;
111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
112
113 if (c->x86_model < 6) {
114
115 if (c->x86_model == 0) {
116 clear_cpu_cap(c, X86_FEATURE_APIC);
117 set_cpu_cap(c, X86_FEATURE_PGE);
118 }
119 return;
120 }
121
122 if (c->x86_model == 6 && c->x86_mask == 1) {
123 const int K6_BUG_LOOP = 1000000;
124 int n;
125 void (*f_vide)(void);
126 u64 d, d2;
127
128 pr_info("AMD K6 stepping B detected - ");
129
130
131
132
133
134
135 n = K6_BUG_LOOP;
136 f_vide = vide;
137 OPTIMIZER_HIDE_VAR(f_vide);
138 d = rdtsc();
139 while (n--)
140 f_vide();
141 d2 = rdtsc();
142 d = d2-d;
143
144 if (d > 20*K6_BUG_LOOP)
145 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
146 else
147 pr_cont("probably OK (after B9730xxxx).\n");
148 }
149
150
151 if (c->x86_model < 8 ||
152 (c->x86_model == 8 && c->x86_mask < 8)) {
153
154 if (mbytes > 508)
155 mbytes = 508;
156
157 rdmsr(MSR_K6_WHCR, l, h);
158 if ((l&0x0000FFFF) == 0) {
159 unsigned long flags;
160 l = (1<<0)|((mbytes/4)<<1);
161 local_irq_save(flags);
162 wbinvd();
163 wrmsr(MSR_K6_WHCR, l, h);
164 local_irq_restore(flags);
165 pr_info("Enabling old style K6 write allocation for %d Mb\n",
166 mbytes);
167 }
168 return;
169 }
170
171 if ((c->x86_model == 8 && c->x86_mask > 7) ||
172 c->x86_model == 9 || c->x86_model == 13) {
173
174
175 if (mbytes > 4092)
176 mbytes = 4092;
177
178 rdmsr(MSR_K6_WHCR, l, h);
179 if ((l&0xFFFF0000) == 0) {
180 unsigned long flags;
181 l = ((mbytes>>2)<<22)|(1<<16);
182 local_irq_save(flags);
183 wbinvd();
184 wrmsr(MSR_K6_WHCR, l, h);
185 local_irq_restore(flags);
186 pr_info("Enabling new style K6 write allocation for %d Mb\n",
187 mbytes);
188 }
189
190 return;
191 }
192
193 if (c->x86_model == 10) {
194
195
196 return;
197 }
198#endif
199}
200
201static void init_amd_k7(struct cpuinfo_x86 *c)
202{
203#ifdef CONFIG_X86_32
204 u32 l, h;
205
206
207
208
209
210
211 if (c->x86_model >= 6 && c->x86_model <= 10) {
212 if (!cpu_has(c, X86_FEATURE_XMM)) {
213 pr_info("Enabling disabled K7/SSE Support.\n");
214 msr_clear_bit(MSR_K7_HWCR, 15);
215 set_cpu_cap(c, X86_FEATURE_XMM);
216 }
217 }
218
219
220
221
222
223
224 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
225 rdmsr(MSR_K7_CLK_CTL, l, h);
226 if ((l & 0xfff00000) != 0x20000000) {
227 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
228 l, ((l & 0x000fffff)|0x20000000));
229 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
230 }
231 }
232
233 set_cpu_cap(c, X86_FEATURE_K7);
234
235
236 if (!c->cpu_index)
237 return;
238
239
240
241
242
243
244 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
245 (c->x86_mask == 1)))
246 return;
247
248
249 if ((c->x86_model == 7) && (c->x86_mask == 0))
250 return;
251
252
253
254
255
256
257
258
259 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
260 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
261 (c->x86_model > 7))
262 if (cpu_has(c, X86_FEATURE_MP))
263 return;
264
265
266
267
268
269
270
271 WARN_ONCE(1, "WARNING: This combination of AMD"
272 " processors is not suitable for SMP.\n");
273 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
274#endif
275}
276
277#ifdef CONFIG_NUMA
278
279
280
281
282static int nearby_node(int apicid)
283{
284 int i, node;
285
286 for (i = apicid - 1; i >= 0; i--) {
287 node = __apicid_to_node[i];
288 if (node != NUMA_NO_NODE && node_online(node))
289 return node;
290 }
291 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
292 node = __apicid_to_node[i];
293 if (node != NUMA_NO_NODE && node_online(node))
294 return node;
295 }
296 return first_node(node_online_map);
297}
298#endif
299
300
301
302
303
304
305
306#ifdef CONFIG_SMP
307static void amd_get_topology(struct cpuinfo_x86 *c)
308{
309 u8 node_id;
310 int cpu = smp_processor_id();
311
312
313 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
314 u32 eax, ebx, ecx, edx;
315
316 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
317
318 node_id = ecx & 0xff;
319 smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
320
321 if (c->x86 == 0x15)
322 c->cu_id = ebx & 0xff;
323
324 if (c->x86 >= 0x17) {
325 c->cpu_core_id = ebx & 0xff;
326
327 if (smp_num_siblings > 1)
328 c->x86_max_cores /= smp_num_siblings;
329 }
330
331
332
333
334
335 if (cpuid_edx(0x80000006)) {
336 if (c->x86 == 0x17) {
337
338
339
340
341 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
342 } else {
343
344 per_cpu(cpu_llc_id, cpu) = node_id;
345 }
346 }
347 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
348 u64 value;
349
350 rdmsrl(MSR_FAM10H_NODE_ID, value);
351 node_id = value & 7;
352
353 per_cpu(cpu_llc_id, cpu) = node_id;
354 } else
355 return;
356
357
358 if (nodes_per_socket > 1) {
359 u32 cus_per_node;
360
361 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
362 cus_per_node = c->x86_max_cores / nodes_per_socket;
363
364
365 c->cpu_core_id %= cus_per_node;
366 }
367}
368#endif
369
370
371
372
373
374static void amd_detect_cmp(struct cpuinfo_x86 *c)
375{
376#ifdef CONFIG_SMP
377 unsigned bits;
378 int cpu = smp_processor_id();
379
380 bits = c->x86_coreid_bits;
381
382 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
383
384 c->phys_proc_id = c->initial_apicid >> bits;
385
386 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
387 amd_get_topology(c);
388#endif
389}
390
391u16 amd_get_nb_id(int cpu)
392{
393 u16 id = 0;
394#ifdef CONFIG_SMP
395 id = per_cpu(cpu_llc_id, cpu);
396#endif
397 return id;
398}
399EXPORT_SYMBOL_GPL(amd_get_nb_id);
400
401u32 amd_get_nodes_per_socket(void)
402{
403 return nodes_per_socket;
404}
405EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
406
407static void srat_detect_node(struct cpuinfo_x86 *c)
408{
409#ifdef CONFIG_NUMA
410 int cpu = smp_processor_id();
411 int node;
412 unsigned apicid = c->apicid;
413
414 node = numa_cpu_node(cpu);
415 if (node == NUMA_NO_NODE)
416 node = per_cpu(cpu_llc_id, cpu);
417
418
419
420
421
422
423 if (x86_cpuinit.fixup_cpu_id)
424 x86_cpuinit.fixup_cpu_id(c, node);
425
426 if (!node_online(node)) {
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446 int ht_nodeid = c->initial_apicid;
447
448 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
449 node = __apicid_to_node[ht_nodeid];
450
451 if (!node_online(node))
452 node = nearby_node(apicid);
453 }
454 numa_set_node(cpu, node);
455#endif
456}
457
458static void early_init_amd_mc(struct cpuinfo_x86 *c)
459{
460#ifdef CONFIG_SMP
461 unsigned bits, ecx;
462
463
464 if (c->extended_cpuid_level < 0x80000008)
465 return;
466
467 ecx = cpuid_ecx(0x80000008);
468
469 c->x86_max_cores = (ecx & 0xff) + 1;
470
471
472 bits = (ecx >> 12) & 0xF;
473
474
475 if (bits == 0) {
476 while ((1 << bits) < c->x86_max_cores)
477 bits++;
478 }
479
480 c->x86_coreid_bits = bits;
481#endif
482}
483
484static void bsp_init_amd(struct cpuinfo_x86 *c)
485{
486
487#ifdef CONFIG_X86_64
488 if (c->x86 >= 0xf) {
489 unsigned long long tseg;
490
491
492
493
494
495
496 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
497 unsigned long pfn = tseg >> PAGE_SHIFT;
498
499 pr_debug("tseg: %010llx\n", tseg);
500 if (pfn_range_is_mapped(pfn, pfn + 1))
501 set_memory_4k((unsigned long)__va(tseg), 1);
502 }
503 }
504#endif
505
506 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
507
508 if (c->x86 > 0x10 ||
509 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
510 u64 val;
511
512 rdmsrl(MSR_K7_HWCR, val);
513 if (!(val & BIT(24)))
514 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
515 }
516 }
517
518 if (c->x86 == 0x15) {
519 unsigned long upperbit;
520 u32 cpuid, assoc;
521
522 cpuid = cpuid_edx(0x80000005);
523 assoc = cpuid >> 16 & 0xff;
524 upperbit = ((cpuid >> 24) << 10) / assoc;
525
526 va_align.mask = (upperbit - 1) & PAGE_MASK;
527 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
528
529
530 va_align.bits = get_random_int() & va_align.mask;
531 }
532
533 if (cpu_has(c, X86_FEATURE_MWAITX))
534 use_mwaitx_delay();
535
536 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
537 u32 ecx;
538
539 ecx = cpuid_ecx(0x8000001e);
540 nodes_per_socket = ((ecx >> 8) & 7) + 1;
541 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
542 u64 value;
543
544 rdmsrl(MSR_FAM10H_NODE_ID, value);
545 nodes_per_socket = ((value >> 3) & 7) + 1;
546 }
547}
548
549static void early_init_amd(struct cpuinfo_x86 *c)
550{
551 early_init_amd_mc(c);
552
553
554
555
556
557 if (c->x86_power & (1 << 8)) {
558 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
559 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
560 }
561
562
563 if (c->x86_power & BIT(12))
564 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
565
566#ifdef CONFIG_X86_64
567 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
568#else
569
570 if (c->x86 == 5)
571 if (c->x86_model == 13 || c->x86_model == 9 ||
572 (c->x86_model == 8 && c->x86_mask >= 8))
573 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
574#endif
575#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
576
577
578
579
580
581
582 if (boot_cpu_has(X86_FEATURE_APIC)) {
583 if (c->x86 > 0x16)
584 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
585 else if (c->x86 >= 0xf) {
586
587 unsigned int val;
588
589 val = read_pci_config(0, 24, 0, 0x68);
590 if ((val >> 17 & 0x3) == 0x3)
591 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
592 }
593 }
594#endif
595
596
597
598
599
600
601 set_cpu_cap(c, X86_FEATURE_VMMCALL);
602
603
604 if (c->x86 == 0x16 && c->x86_model <= 0xf)
605 msr_set_bit(MSR_AMD64_LS_CFG, 15);
606
607
608
609
610
611
612
613 if (cpu_has_amd_erratum(c, amd_erratum_400))
614 set_cpu_bug(c, X86_BUG_AMD_E400);
615}
616
617static void init_amd_k8(struct cpuinfo_x86 *c)
618{
619 u32 level;
620 u64 value;
621
622
623 level = cpuid_eax(1);
624 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
625 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
626
627
628
629
630
631
632 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
633 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
634 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
635 value &= ~BIT_64(32);
636 wrmsrl_amd_safe(0xc001100d, value);
637 }
638 }
639
640 if (!c->x86_model_id[0])
641 strcpy(c->x86_model_id, "Hammer");
642
643#ifdef CONFIG_SMP
644
645
646
647
648
649
650
651 msr_set_bit(MSR_K7_HWCR, 6);
652#endif
653 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
654}
655
656static void init_amd_gh(struct cpuinfo_x86 *c)
657{
658#ifdef CONFIG_X86_64
659
660 if (c == &boot_cpu_data)
661 check_enable_amd_mmconf_dmi();
662
663 fam10h_check_enable_mmcfg();
664#endif
665
666
667
668
669
670
671
672
673
674 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
675
676
677
678
679
680
681
682
683
684
685 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
686
687 if (cpu_has_amd_erratum(c, amd_erratum_383))
688 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
689}
690
691#define MSR_AMD64_DE_CFG 0xC0011029
692
693static void init_amd_ln(struct cpuinfo_x86 *c)
694{
695
696
697
698
699 msr_set_bit(MSR_AMD64_DE_CFG, 31);
700}
701
702static void init_amd_bd(struct cpuinfo_x86 *c)
703{
704 u64 value;
705
706
707 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
708 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
709
710 if (msr_set_bit(0xc0011005, 54) > 0) {
711 rdmsrl(0xc0011005, value);
712 if (value & BIT_64(54)) {
713 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
714 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
715 }
716 }
717 }
718
719
720
721
722
723 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
724 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
725 value |= 0x1E;
726 wrmsrl_safe(MSR_F15H_IC_CFG, value);
727 }
728 }
729}
730
731static void init_amd(struct cpuinfo_x86 *c)
732{
733 u32 dummy;
734
735 early_init_amd(c);
736
737
738
739
740
741 clear_cpu_cap(c, 0*32+31);
742
743 if (c->x86 >= 0x10)
744 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
745
746
747 c->apicid = hard_smp_processor_id();
748
749
750 if (c->x86 < 6)
751 clear_cpu_cap(c, X86_FEATURE_MCE);
752
753 switch (c->x86) {
754 case 4: init_amd_k5(c); break;
755 case 5: init_amd_k6(c); break;
756 case 6: init_amd_k7(c); break;
757 case 0xf: init_amd_k8(c); break;
758 case 0x10: init_amd_gh(c); break;
759 case 0x12: init_amd_ln(c); break;
760 case 0x15: init_amd_bd(c); break;
761 }
762
763
764 if (c->x86 >= 6)
765 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
766
767 cpu_detect_cache_sizes(c);
768
769
770 if (c->extended_cpuid_level >= 0x80000008) {
771 amd_detect_cmp(c);
772 srat_detect_node(c);
773 }
774
775#ifdef CONFIG_X86_32
776 detect_ht(c);
777#endif
778
779 init_amd_cacheinfo(c);
780
781 if (c->x86 >= 0xf)
782 set_cpu_cap(c, X86_FEATURE_K8);
783
784 if (cpu_has(c, X86_FEATURE_XMM2)) {
785
786 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
787 }
788
789
790
791
792
793 if (c->x86 > 0x11)
794 set_cpu_cap(c, X86_FEATURE_ARAT);
795
796 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
797
798
799 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
800 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
801 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
802
803
804 if (!cpu_has(c, X86_FEATURE_XENPV))
805 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
806}
807
808#ifdef CONFIG_X86_32
809static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
810{
811
812 if ((c->x86 == 6)) {
813
814 if (c->x86_model == 3 && c->x86_mask == 0)
815 size = 64;
816
817 if (c->x86_model == 4 &&
818 (c->x86_mask == 0 || c->x86_mask == 1))
819 size = 256;
820 }
821 return size;
822}
823#endif
824
825static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
826{
827 u32 ebx, eax, ecx, edx;
828 u16 mask = 0xfff;
829
830 if (c->x86 < 0xf)
831 return;
832
833 if (c->extended_cpuid_level < 0x80000006)
834 return;
835
836 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
837
838 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
839 tlb_lli_4k[ENTRIES] = ebx & mask;
840
841
842
843
844
845 if (c->x86 == 0xf) {
846 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
847 mask = 0xff;
848 }
849
850
851 if (!((eax >> 16) & mask))
852 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
853 else
854 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
855
856
857 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
858
859
860 if (!(eax & mask)) {
861
862 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
863 tlb_lli_2m[ENTRIES] = 1024;
864 } else {
865 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
866 tlb_lli_2m[ENTRIES] = eax & 0xff;
867 }
868 } else
869 tlb_lli_2m[ENTRIES] = eax & mask;
870
871 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
872}
873
874static const struct cpu_dev amd_cpu_dev = {
875 .c_vendor = "AMD",
876 .c_ident = { "AuthenticAMD" },
877#ifdef CONFIG_X86_32
878 .legacy_models = {
879 { .family = 4, .model_names =
880 {
881 [3] = "486 DX/2",
882 [7] = "486 DX/2-WB",
883 [8] = "486 DX/4",
884 [9] = "486 DX/4-WB",
885 [14] = "Am5x86-WT",
886 [15] = "Am5x86-WB"
887 }
888 },
889 },
890 .legacy_cache_size = amd_size_cache,
891#endif
892 .c_early_init = early_init_amd,
893 .c_detect_tlb = cpu_detect_tlb_amd,
894 .c_bsp_init = bsp_init_amd,
895 .c_init = init_amd,
896 .c_x86_vendor = X86_VENDOR_AMD,
897};
898
899cpu_dev_register(amd_cpu_dev);
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
919#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
920#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
921 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
922#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
923#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
924#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
925
926static const int amd_erratum_400[] =
927 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
928 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
929
930static const int amd_erratum_383[] =
931 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
932
933
934static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
935{
936 int osvw_id = *erratum++;
937 u32 range;
938 u32 ms;
939
940 if (osvw_id >= 0 && osvw_id < 65536 &&
941 cpu_has(cpu, X86_FEATURE_OSVW)) {
942 u64 osvw_len;
943
944 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
945 if (osvw_id < osvw_len) {
946 u64 osvw_bits;
947
948 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
949 osvw_bits);
950 return osvw_bits & (1ULL << (osvw_id & 0x3f));
951 }
952 }
953
954
955 ms = (cpu->x86_model << 4) | cpu->x86_mask;
956 while ((range = *erratum++))
957 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
958 (ms >= AMD_MODEL_RANGE_START(range)) &&
959 (ms <= AMD_MODEL_RANGE_END(range)))
960 return true;
961
962 return false;
963}
964
965void set_dr_addr_mask(unsigned long mask, int dr)
966{
967 if (!boot_cpu_has(X86_FEATURE_BPEXT))
968 return;
969
970 switch (dr) {
971 case 0:
972 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
973 break;
974 case 1:
975 case 2:
976 case 3:
977 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
978 break;
979 default:
980 break;
981 }
982}
983