LXR linux/arch/x86/kernel/cpu/mcheck/mce-internal.h

   1#include <linux/device.h>
   2#include <asm/mce.h>
   3
   4enum severity_level {
   5        MCE_NO_SEVERITY,
   6        MCE_DEFERRED_SEVERITY,
   7        MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY,
   8        MCE_KEEP_SEVERITY,
   9        MCE_SOME_SEVERITY,
  10        MCE_AO_SEVERITY,
  11        MCE_UC_SEVERITY,
  12        MCE_AR_SEVERITY,
  13        MCE_PANIC_SEVERITY,
  14};
  15
  16extern struct blocking_notifier_head x86_mce_decoder_chain;
  17
  18#define ATTR_LEN                16
  19#define INITIAL_CHECK_INTERVAL  5 * 60 /* 5 minutes */
  20
  21/* One object for each MCE bank, shared by all CPUs */
  22struct mce_bank {
  23        u64                     ctl;                    /* subevents to enable */
  24        unsigned char init;                             /* initialise bank? */
  25        struct device_attribute attr;                   /* device attribute */
  26        char                    attrname[ATTR_LEN];     /* attribute name */
  27};
  28
  29struct mce_evt_llist {
  30        struct llist_node llnode;
  31        struct mce mce;
  32};
  33
  34void mce_gen_pool_process(struct work_struct *__unused);
  35bool mce_gen_pool_empty(void);
  36int mce_gen_pool_add(struct mce *mce);
  37int mce_gen_pool_init(void);
  38struct llist_node *mce_gen_pool_prepare_records(void);
  39
  40extern int (*mce_severity)(struct mce *a, int tolerant, char **msg, bool is_excp);
  41struct dentry *mce_get_debugfs_dir(void);
  42
  43extern struct mce_bank *mce_banks;
  44extern mce_banks_t mce_banks_ce_disabled;
  45
  46#ifdef CONFIG_X86_MCE_INTEL
  47unsigned long cmci_intel_adjust_timer(unsigned long interval);
  48bool mce_intel_cmci_poll(void);
  49void mce_intel_hcpu_update(unsigned long cpu);
  50void cmci_disable_bank(int bank);
  51#else
  52# define cmci_intel_adjust_timer mce_adjust_timer_default
  53static inline bool mce_intel_cmci_poll(void) { return false; }
  54static inline void mce_intel_hcpu_update(unsigned long cpu) { }
  55static inline void cmci_disable_bank(int bank) { }
  56#endif
  57
  58void mce_timer_kick(unsigned long interval);
  59
  60#ifdef CONFIG_ACPI_APEI
  61int apei_write_mce(struct mce *m);
  62ssize_t apei_read_mce(struct mce *m, u64 *record_id);
  63int apei_check_mce(void);
  64int apei_clear_mce(u64 record_id);
  65#else
  66static inline int apei_write_mce(struct mce *m)
  67{
  68        return -EINVAL;
  69}
  70static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id)
  71{
  72        return 0;
  73}
  74static inline int apei_check_mce(void)
  75{
  76        return 0;
  77}
  78static inline int apei_clear_mce(u64 record_id)
  79{
  80        return -EINVAL;
  81}
  82#endif
  83
  84void mce_inject_log(struct mce *m);
  85
  86/*
  87 * We consider records to be equivalent if bank+status+addr+misc all match.
  88 * This is only used when the system is going down because of a fatal error
  89 * to avoid cluttering the console log with essentially repeated information.
  90 * In normal processing all errors seen are logged.
  91 */
  92static inline bool mce_cmp(struct mce *m1, struct mce *m2)
  93{
  94        return m1->bank != m2->bank ||
  95                m1->status != m2->status ||
  96                m1->addr != m2->addr ||
  97                m1->misc != m2->misc;
  98}
  99
 100extern struct device_attribute dev_attr_trigger;
 101
 102#ifdef CONFIG_X86_MCELOG_LEGACY
 103void mce_work_trigger(void);
 104void mce_register_injector_chain(struct notifier_block *nb);
 105void mce_unregister_injector_chain(struct notifier_block *nb);
 106#else
 107static inline void mce_work_trigger(void)       { }
 108static inline void mce_register_injector_chain(struct notifier_block *nb)       { }
 109static inline void mce_unregister_injector_chain(struct notifier_block *nb)     { }
 110#endif
 111