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24
25#define pr_fmt(fmt) "Calgary: " fmt
26
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/slab.h>
31#include <linux/mm.h>
32#include <linux/spinlock.h>
33#include <linux/string.h>
34#include <linux/crash_dump.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitmap.h>
37#include <linux/pci_ids.h>
38#include <linux/pci.h>
39#include <linux/delay.h>
40#include <linux/scatterlist.h>
41#include <linux/iommu-helper.h>
42
43#include <asm/iommu.h>
44#include <asm/calgary.h>
45#include <asm/tce.h>
46#include <asm/pci-direct.h>
47#include <asm/dma.h>
48#include <asm/rio.h>
49#include <asm/bios_ebda.h>
50#include <asm/x86_init.h>
51#include <asm/iommu_table.h>
52
53#define CALGARY_MAPPING_ERROR 0
54
55#ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
56int use_calgary __read_mostly = 1;
57#else
58int use_calgary __read_mostly = 0;
59#endif
60
61#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
62#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
63
64
65#define CALGARY_CONFIG_REG 0x0108
66#define PHB_CSR_OFFSET 0x0110
67#define PHB_PLSSR_OFFSET 0x0120
68#define PHB_CONFIG_RW_OFFSET 0x0160
69#define PHB_IOBASE_BAR_LOW 0x0170
70#define PHB_IOBASE_BAR_HIGH 0x0180
71#define PHB_MEM_1_LOW 0x0190
72#define PHB_MEM_1_HIGH 0x01A0
73#define PHB_IO_ADDR_SIZE 0x01B0
74#define PHB_MEM_1_SIZE 0x01C0
75#define PHB_MEM_ST_OFFSET 0x01D0
76#define PHB_AER_OFFSET 0x0200
77#define PHB_CONFIG_0_HIGH 0x0220
78#define PHB_CONFIG_0_LOW 0x0230
79#define PHB_CONFIG_0_END 0x0240
80#define PHB_MEM_2_LOW 0x02B0
81#define PHB_MEM_2_HIGH 0x02C0
82#define PHB_MEM_2_SIZE_HIGH 0x02D0
83#define PHB_MEM_2_SIZE_LOW 0x02E0
84#define PHB_DOSHOLE_OFFSET 0x08E0
85
86
87#define PHB_SAVIOR_L2 0x0DB0
88#define PHB_PAGE_MIG_CTRL 0x0DA8
89#define PHB_PAGE_MIG_DEBUG 0x0DA0
90#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
91
92
93#define PHB_TCE_ENABLE 0x20000000
94#define PHB_SLOT_DISABLE 0x1C000000
95#define PHB_DAC_DISABLE 0x01000000
96#define PHB_MEM2_ENABLE 0x00400000
97#define PHB_MCSR_ENABLE 0x00100000
98
99#define TAR_SW_BITS 0x0000ffffffff800fUL
100#define TAR_VALID 0x0000000000000008UL
101
102#define CSR_AGENT_MASK 0xffe0ffff
103
104#define CCR_2SEC_TIMEOUT 0x000000000000000EUL
105
106#define PMR_SOFTSTOP 0x80000000
107#define PMR_SOFTSTOPFAULT 0x40000000
108#define PMR_HARDSTOP 0x20000000
109
110
111
112
113
114
115
116
117#define MAX_PHB_BUS_NUM 256
118
119#define PHBS_PER_CALGARY 4
120
121
122static const unsigned long tar_offsets[] = {
123 0x0580 ,
124 0x0588 ,
125 0x0590 ,
126 0x0598
127};
128
129static const unsigned long split_queue_offsets[] = {
130 0x4870 ,
131 0x5870 ,
132 0x6870 ,
133 0x7870
134};
135
136static const unsigned long phb_offsets[] = {
137 0x8000 ,
138 0x9000 ,
139 0xA000 ,
140 0xB000
141};
142
143
144
145static const unsigned long phb_debug_offsets[] = {
146 0x4000 ,
147 0x5000 ,
148 0x6000 ,
149 0x7000
150};
151
152
153
154
155
156
157#define PHB_DEBUG_STUFF_OFFSET 0x0020
158
159#define EMERGENCY_PAGES 32
160
161unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
162static int translate_empty_slots __read_mostly = 0;
163static int calgary_detected __read_mostly = 0;
164
165static struct rio_table_hdr *rio_table_hdr __initdata;
166static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
167static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
168
169struct calgary_bus_info {
170 void *tce_space;
171 unsigned char translation_disabled;
172 signed char phbid;
173 void __iomem *bbar;
174};
175
176static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
177static void calgary_tce_cache_blast(struct iommu_table *tbl);
178static void calgary_dump_error_regs(struct iommu_table *tbl);
179static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
180static void calioc2_tce_cache_blast(struct iommu_table *tbl);
181static void calioc2_dump_error_regs(struct iommu_table *tbl);
182static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
183static void get_tce_space_from_tar(void);
184
185static const struct cal_chipset_ops calgary_chip_ops = {
186 .handle_quirks = calgary_handle_quirks,
187 .tce_cache_blast = calgary_tce_cache_blast,
188 .dump_error_regs = calgary_dump_error_regs
189};
190
191static const struct cal_chipset_ops calioc2_chip_ops = {
192 .handle_quirks = calioc2_handle_quirks,
193 .tce_cache_blast = calioc2_tce_cache_blast,
194 .dump_error_regs = calioc2_dump_error_regs
195};
196
197static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
198
199static inline int translation_enabled(struct iommu_table *tbl)
200{
201
202 return (tbl != NULL);
203}
204
205static void iommu_range_reserve(struct iommu_table *tbl,
206 unsigned long start_addr, unsigned int npages)
207{
208 unsigned long index;
209 unsigned long end;
210 unsigned long flags;
211
212 index = start_addr >> PAGE_SHIFT;
213
214
215 if (index >= tbl->it_size)
216 return;
217
218 end = index + npages;
219 if (end > tbl->it_size)
220 end = tbl->it_size;
221
222 spin_lock_irqsave(&tbl->it_lock, flags);
223
224 bitmap_set(tbl->it_map, index, npages);
225
226 spin_unlock_irqrestore(&tbl->it_lock, flags);
227}
228
229static unsigned long iommu_range_alloc(struct device *dev,
230 struct iommu_table *tbl,
231 unsigned int npages)
232{
233 unsigned long flags;
234 unsigned long offset;
235 unsigned long boundary_size;
236
237 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
238 PAGE_SIZE) >> PAGE_SHIFT;
239
240 BUG_ON(npages == 0);
241
242 spin_lock_irqsave(&tbl->it_lock, flags);
243
244 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
245 npages, 0, boundary_size, 0);
246 if (offset == ~0UL) {
247 tbl->chip_ops->tce_cache_blast(tbl);
248
249 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
250 npages, 0, boundary_size, 0);
251 if (offset == ~0UL) {
252 pr_warn("IOMMU full\n");
253 spin_unlock_irqrestore(&tbl->it_lock, flags);
254 if (panic_on_overflow)
255 panic("Calgary: fix the allocator.\n");
256 else
257 return CALGARY_MAPPING_ERROR;
258 }
259 }
260
261 tbl->it_hint = offset + npages;
262 BUG_ON(tbl->it_hint > tbl->it_size);
263
264 spin_unlock_irqrestore(&tbl->it_lock, flags);
265
266 return offset;
267}
268
269static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
270 void *vaddr, unsigned int npages, int direction)
271{
272 unsigned long entry;
273 dma_addr_t ret;
274
275 entry = iommu_range_alloc(dev, tbl, npages);
276
277 if (unlikely(entry == CALGARY_MAPPING_ERROR)) {
278 pr_warn("failed to allocate %u pages in iommu %p\n",
279 npages, tbl);
280 return CALGARY_MAPPING_ERROR;
281 }
282
283
284 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
285
286
287 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
288 direction);
289 return ret;
290}
291
292static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
293 unsigned int npages)
294{
295 unsigned long entry;
296 unsigned long badend;
297 unsigned long flags;
298
299
300 badend = CALGARY_MAPPING_ERROR + (EMERGENCY_PAGES * PAGE_SIZE);
301 if (unlikely(dma_addr < badend)) {
302 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
303 "address 0x%Lx\n", dma_addr);
304 return;
305 }
306
307 entry = dma_addr >> PAGE_SHIFT;
308
309 BUG_ON(entry + npages > tbl->it_size);
310
311 tce_free(tbl, entry, npages);
312
313 spin_lock_irqsave(&tbl->it_lock, flags);
314
315 bitmap_clear(tbl->it_map, entry, npages);
316
317 spin_unlock_irqrestore(&tbl->it_lock, flags);
318}
319
320static inline struct iommu_table *find_iommu_table(struct device *dev)
321{
322 struct pci_dev *pdev;
323 struct pci_bus *pbus;
324 struct iommu_table *tbl;
325
326 pdev = to_pci_dev(dev);
327
328
329 pbus = pdev->bus;
330 do {
331 tbl = pci_iommu(pbus);
332 if (tbl && tbl->it_busno == pbus->number)
333 break;
334 tbl = NULL;
335 pbus = pbus->parent;
336 } while (pbus);
337
338 BUG_ON(tbl && (tbl->it_busno != pbus->number));
339
340 return tbl;
341}
342
343static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
344 int nelems,enum dma_data_direction dir,
345 unsigned long attrs)
346{
347 struct iommu_table *tbl = find_iommu_table(dev);
348 struct scatterlist *s;
349 int i;
350
351 if (!translation_enabled(tbl))
352 return;
353
354 for_each_sg(sglist, s, nelems, i) {
355 unsigned int npages;
356 dma_addr_t dma = s->dma_address;
357 unsigned int dmalen = s->dma_length;
358
359 if (dmalen == 0)
360 break;
361
362 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
363 iommu_free(tbl, dma, npages);
364 }
365}
366
367static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
368 int nelems, enum dma_data_direction dir,
369 unsigned long attrs)
370{
371 struct iommu_table *tbl = find_iommu_table(dev);
372 struct scatterlist *s;
373 unsigned long vaddr;
374 unsigned int npages;
375 unsigned long entry;
376 int i;
377
378 for_each_sg(sg, s, nelems, i) {
379 BUG_ON(!sg_page(s));
380
381 vaddr = (unsigned long) sg_virt(s);
382 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
383
384 entry = iommu_range_alloc(dev, tbl, npages);
385 if (entry == CALGARY_MAPPING_ERROR) {
386
387 s->dma_length = 0;
388 goto error;
389 }
390
391 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
392
393
394 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
395
396 s->dma_length = s->length;
397 }
398
399 return nelems;
400error:
401 calgary_unmap_sg(dev, sg, nelems, dir, 0);
402 for_each_sg(sg, s, nelems, i) {
403 sg->dma_address = CALGARY_MAPPING_ERROR;
404 sg->dma_length = 0;
405 }
406 return 0;
407}
408
409static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
410 unsigned long offset, size_t size,
411 enum dma_data_direction dir,
412 unsigned long attrs)
413{
414 void *vaddr = page_address(page) + offset;
415 unsigned long uaddr;
416 unsigned int npages;
417 struct iommu_table *tbl = find_iommu_table(dev);
418
419 uaddr = (unsigned long)vaddr;
420 npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
421
422 return iommu_alloc(dev, tbl, vaddr, npages, dir);
423}
424
425static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
426 size_t size, enum dma_data_direction dir,
427 unsigned long attrs)
428{
429 struct iommu_table *tbl = find_iommu_table(dev);
430 unsigned int npages;
431
432 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
433 iommu_free(tbl, dma_addr, npages);
434}
435
436static void* calgary_alloc_coherent(struct device *dev, size_t size,
437 dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs)
438{
439 void *ret = NULL;
440 dma_addr_t mapping;
441 unsigned int npages, order;
442 struct iommu_table *tbl = find_iommu_table(dev);
443
444 size = PAGE_ALIGN(size);
445 npages = size >> PAGE_SHIFT;
446 order = get_order(size);
447
448 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
449
450
451 ret = (void *)__get_free_pages(flag, order);
452 if (!ret)
453 goto error;
454 memset(ret, 0, size);
455
456
457 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
458 if (mapping == CALGARY_MAPPING_ERROR)
459 goto free;
460 *dma_handle = mapping;
461 return ret;
462free:
463 free_pages((unsigned long)ret, get_order(size));
464 ret = NULL;
465error:
466 return ret;
467}
468
469static void calgary_free_coherent(struct device *dev, size_t size,
470 void *vaddr, dma_addr_t dma_handle,
471 unsigned long attrs)
472{
473 unsigned int npages;
474 struct iommu_table *tbl = find_iommu_table(dev);
475
476 size = PAGE_ALIGN(size);
477 npages = size >> PAGE_SHIFT;
478
479 iommu_free(tbl, dma_handle, npages);
480 free_pages((unsigned long)vaddr, get_order(size));
481}
482
483static int calgary_mapping_error(struct device *dev, dma_addr_t dma_addr)
484{
485 return dma_addr == CALGARY_MAPPING_ERROR;
486}
487
488static const struct dma_map_ops calgary_dma_ops = {
489 .alloc = calgary_alloc_coherent,
490 .free = calgary_free_coherent,
491 .map_sg = calgary_map_sg,
492 .unmap_sg = calgary_unmap_sg,
493 .map_page = calgary_map_page,
494 .unmap_page = calgary_unmap_page,
495 .mapping_error = calgary_mapping_error,
496 .dma_supported = x86_dma_supported,
497};
498
499static inline void __iomem * busno_to_bbar(unsigned char num)
500{
501 return bus_info[num].bbar;
502}
503
504static inline int busno_to_phbid(unsigned char num)
505{
506 return bus_info[num].phbid;
507}
508
509static inline unsigned long split_queue_offset(unsigned char num)
510{
511 size_t idx = busno_to_phbid(num);
512
513 return split_queue_offsets[idx];
514}
515
516static inline unsigned long tar_offset(unsigned char num)
517{
518 size_t idx = busno_to_phbid(num);
519
520 return tar_offsets[idx];
521}
522
523static inline unsigned long phb_offset(unsigned char num)
524{
525 size_t idx = busno_to_phbid(num);
526
527 return phb_offsets[idx];
528}
529
530static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
531{
532 unsigned long target = ((unsigned long)bar) | offset;
533 return (void __iomem*)target;
534}
535
536static inline int is_calioc2(unsigned short device)
537{
538 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
539}
540
541static inline int is_calgary(unsigned short device)
542{
543 return (device == PCI_DEVICE_ID_IBM_CALGARY);
544}
545
546static inline int is_cal_pci_dev(unsigned short device)
547{
548 return (is_calgary(device) || is_calioc2(device));
549}
550
551static void calgary_tce_cache_blast(struct iommu_table *tbl)
552{
553 u64 val;
554 u32 aer;
555 int i = 0;
556 void __iomem *bbar = tbl->bbar;
557 void __iomem *target;
558
559
560 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
561 aer = readl(target);
562 writel(0, target);
563
564
565 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
566 val = readl(target);
567
568
569 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
570 do {
571 val = readq(target);
572 i++;
573 } while ((val & 0xff) != 0xff && i < 100);
574 if (i == 100)
575 pr_warn("PCI bus not quiesced, continuing anyway\n");
576
577
578 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
579 writeq(tbl->tar_val, target);
580
581
582 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
583 writel(aer, target);
584 (void)readl(target);
585}
586
587static void calioc2_tce_cache_blast(struct iommu_table *tbl)
588{
589 void __iomem *bbar = tbl->bbar;
590 void __iomem *target;
591 u64 val64;
592 u32 val;
593 int i = 0;
594 int count = 1;
595 unsigned char bus = tbl->it_busno;
596
597begin:
598 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
599 "sequence - count %d\n", bus, count);
600
601
602 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
603 val = be32_to_cpu(readl(target));
604 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
605 val |= PMR_SOFTSTOP;
606 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
607 writel(cpu_to_be32(val), target);
608
609
610 printk(KERN_DEBUG "2a. starting to poll split queues\n");
611 target = calgary_reg(bbar, split_queue_offset(bus));
612 do {
613 val64 = readq(target);
614 i++;
615 } while ((val64 & 0xff) != 0xff && i < 100);
616 if (i == 100)
617 pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
618
619
620 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
621 val = be32_to_cpu(readl(target));
622 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
623
624
625 if (val & PMR_SOFTSTOPFAULT) {
626 if (++count < 100)
627 goto begin;
628 else {
629 pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
630 return;
631 }
632 }
633
634
635 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
636 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
637 val = be32_to_cpu(readl(target));
638 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
639 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
640 val = be32_to_cpu(readl(target));
641 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
642
643
644 printk(KERN_DEBUG "6. invalidating TCE cache\n");
645 target = calgary_reg(bbar, tar_offset(bus));
646 writeq(tbl->tar_val, target);
647
648
649 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
650 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
651 val = be32_to_cpu(readl(target));
652 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
653
654
655 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
656 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
657 val = 0;
658 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
659 writel(cpu_to_be32(val), target);
660 val = be32_to_cpu(readl(target));
661 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
662}
663
664static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
665 u64 limit)
666{
667 unsigned int numpages;
668
669 limit = limit | 0xfffff;
670 limit++;
671
672 numpages = ((limit - start) >> PAGE_SHIFT);
673 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
674}
675
676static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
677{
678 void __iomem *target;
679 u64 low, high, sizelow;
680 u64 start, limit;
681 struct iommu_table *tbl = pci_iommu(dev->bus);
682 unsigned char busnum = dev->bus->number;
683 void __iomem *bbar = tbl->bbar;
684
685
686 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
687 low = be32_to_cpu(readl(target));
688 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
689 high = be32_to_cpu(readl(target));
690 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
691 sizelow = be32_to_cpu(readl(target));
692
693 start = (high << 32) | low;
694 limit = sizelow;
695
696 calgary_reserve_mem_region(dev, start, limit);
697}
698
699static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
700{
701 void __iomem *target;
702 u32 val32;
703 u64 low, high, sizelow, sizehigh;
704 u64 start, limit;
705 struct iommu_table *tbl = pci_iommu(dev->bus);
706 unsigned char busnum = dev->bus->number;
707 void __iomem *bbar = tbl->bbar;
708
709
710 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
711 val32 = be32_to_cpu(readl(target));
712 if (!(val32 & PHB_MEM2_ENABLE))
713 return;
714
715 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
716 low = be32_to_cpu(readl(target));
717 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
718 high = be32_to_cpu(readl(target));
719 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
720 sizelow = be32_to_cpu(readl(target));
721 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
722 sizehigh = be32_to_cpu(readl(target));
723
724 start = (high << 32) | low;
725 limit = (sizehigh << 32) | sizelow;
726
727 calgary_reserve_mem_region(dev, start, limit);
728}
729
730
731
732
733
734
735
736
737static void __init calgary_reserve_regions(struct pci_dev *dev)
738{
739 unsigned int npages;
740 u64 start;
741 struct iommu_table *tbl = pci_iommu(dev->bus);
742
743
744 iommu_range_reserve(tbl, CALGARY_MAPPING_ERROR, EMERGENCY_PAGES);
745
746
747
748 if (is_calgary(dev->device)) {
749 start = (640 * 1024);
750 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
751 } else {
752 start = 0;
753 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
754 }
755 iommu_range_reserve(tbl, start, npages);
756
757
758 calgary_reserve_peripheral_mem_1(dev);
759 calgary_reserve_peripheral_mem_2(dev);
760}
761
762static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
763{
764 u64 val64;
765 u64 table_phys;
766 void __iomem *target;
767 int ret;
768 struct iommu_table *tbl;
769
770
771 ret = build_tce_table(dev, bbar);
772 if (ret)
773 return ret;
774
775 tbl = pci_iommu(dev->bus);
776 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
777
778 if (is_kdump_kernel())
779 calgary_init_bitmap_from_tce_table(tbl);
780 else
781 tce_free(tbl, 0, tbl->it_size);
782
783 if (is_calgary(dev->device))
784 tbl->chip_ops = &calgary_chip_ops;
785 else if (is_calioc2(dev->device))
786 tbl->chip_ops = &calioc2_chip_ops;
787 else
788 BUG();
789
790 calgary_reserve_regions(dev);
791
792
793 target = calgary_reg(bbar, tar_offset(dev->bus->number));
794 val64 = be64_to_cpu(readq(target));
795
796
797 val64 &= ~TAR_SW_BITS;
798 table_phys = (u64)__pa(tbl->it_base);
799
800 val64 |= table_phys;
801
802 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
803 val64 |= (u64) specified_table_size;
804
805 tbl->tar_val = cpu_to_be64(val64);
806
807 writeq(tbl->tar_val, target);
808 readq(target);
809
810 return 0;
811}
812
813static void __init calgary_free_bus(struct pci_dev *dev)
814{
815 u64 val64;
816 struct iommu_table *tbl = pci_iommu(dev->bus);
817 void __iomem *target;
818 unsigned int bitmapsz;
819
820 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
821 val64 = be64_to_cpu(readq(target));
822 val64 &= ~TAR_SW_BITS;
823 writeq(cpu_to_be64(val64), target);
824 readq(target);
825
826 bitmapsz = tbl->it_size / BITS_PER_BYTE;
827 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
828 tbl->it_map = NULL;
829
830 kfree(tbl);
831
832 set_pci_iommu(dev->bus, NULL);
833
834
835 bus_info[dev->bus->number].tce_space = NULL;
836}
837
838static void calgary_dump_error_regs(struct iommu_table *tbl)
839{
840 void __iomem *bbar = tbl->bbar;
841 void __iomem *target;
842 u32 csr, plssr;
843
844 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
845 csr = be32_to_cpu(readl(target));
846
847 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
848 plssr = be32_to_cpu(readl(target));
849
850
851 pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
852 tbl->it_busno, csr, plssr);
853}
854
855static void calioc2_dump_error_regs(struct iommu_table *tbl)
856{
857 void __iomem *bbar = tbl->bbar;
858 u32 csr, csmr, plssr, mck, rcstat;
859 void __iomem *target;
860 unsigned long phboff = phb_offset(tbl->it_busno);
861 unsigned long erroff;
862 u32 errregs[7];
863 int i;
864
865
866 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
867 csr = be32_to_cpu(readl(target));
868
869 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
870 plssr = be32_to_cpu(readl(target));
871
872 target = calgary_reg(bbar, phboff | 0x290);
873 csmr = be32_to_cpu(readl(target));
874
875 target = calgary_reg(bbar, phboff | 0x800);
876 mck = be32_to_cpu(readl(target));
877
878 pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
879
880 pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
881 csr, plssr, csmr, mck);
882
883
884 pr_emerg("");
885 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
886
887 erroff = (0x810 + (i * 0x10));
888 target = calgary_reg(bbar, phboff | erroff);
889 errregs[i] = be32_to_cpu(readl(target));
890 pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
891 }
892 pr_cont("\n");
893
894
895 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
896 rcstat = be32_to_cpu(readl(target));
897 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
898 PHB_ROOT_COMPLEX_STATUS);
899}
900
901static void calgary_watchdog(unsigned long data)
902{
903 struct pci_dev *dev = (struct pci_dev *)data;
904 struct iommu_table *tbl = pci_iommu(dev->bus);
905 void __iomem *bbar = tbl->bbar;
906 u32 val32;
907 void __iomem *target;
908
909 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
910 val32 = be32_to_cpu(readl(target));
911
912
913 if (val32 & CSR_AGENT_MASK) {
914 tbl->chip_ops->dump_error_regs(tbl);
915
916
917 writel(0, target);
918
919
920 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
921 PHB_CONFIG_RW_OFFSET);
922 val32 = be32_to_cpu(readl(target));
923 val32 |= PHB_SLOT_DISABLE;
924 writel(cpu_to_be32(val32), target);
925 readl(target);
926 } else {
927
928 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
929 }
930}
931
932static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
933 unsigned char busnum, unsigned long timeout)
934{
935 u64 val64;
936 void __iomem *target;
937 unsigned int phb_shift = ~0;
938 u64 mask;
939
940 switch (busno_to_phbid(busnum)) {
941 case 0: phb_shift = (63 - 19);
942 break;
943 case 1: phb_shift = (63 - 23);
944 break;
945 case 2: phb_shift = (63 - 27);
946 break;
947 case 3: phb_shift = (63 - 35);
948 break;
949 default:
950 BUG_ON(busno_to_phbid(busnum));
951 }
952
953 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
954 val64 = be64_to_cpu(readq(target));
955
956
957 mask = ~(0xFUL << phb_shift);
958 val64 &= mask;
959 val64 |= (timeout << phb_shift);
960 writeq(cpu_to_be64(val64), target);
961 readq(target);
962}
963
964static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
965{
966 unsigned char busnum = dev->bus->number;
967 void __iomem *bbar = tbl->bbar;
968 void __iomem *target;
969 u32 val;
970
971
972
973
974 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
975 val = cpu_to_be32(readl(target));
976 val |= 0x00800000;
977 writel(cpu_to_be32(val), target);
978}
979
980static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
981{
982 unsigned char busnum = dev->bus->number;
983
984
985
986
987
988 if (is_calgary(dev->device) && (busnum == 1))
989 calgary_set_split_completion_timeout(tbl->bbar, busnum,
990 CCR_2SEC_TIMEOUT);
991}
992
993static void __init calgary_enable_translation(struct pci_dev *dev)
994{
995 u32 val32;
996 unsigned char busnum;
997 void __iomem *target;
998 void __iomem *bbar;
999 struct iommu_table *tbl;
1000
1001 busnum = dev->bus->number;
1002 tbl = pci_iommu(dev->bus);
1003 bbar = tbl->bbar;
1004
1005
1006 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1007 val32 = be32_to_cpu(readl(target));
1008 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1009
1010 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1011 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1012 "Calgary" : "CalIOC2", busnum);
1013 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1014 "bus.\n");
1015
1016 writel(cpu_to_be32(val32), target);
1017 readl(target);
1018
1019 setup_timer(&tbl->watchdog_timer, &calgary_watchdog,
1020 (unsigned long)dev);
1021 mod_timer(&tbl->watchdog_timer, jiffies);
1022}
1023
1024static void __init calgary_disable_translation(struct pci_dev *dev)
1025{
1026 u32 val32;
1027 unsigned char busnum;
1028 void __iomem *target;
1029 void __iomem *bbar;
1030 struct iommu_table *tbl;
1031
1032 busnum = dev->bus->number;
1033 tbl = pci_iommu(dev->bus);
1034 bbar = tbl->bbar;
1035
1036
1037 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1038 val32 = be32_to_cpu(readl(target));
1039 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1040
1041 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1042 writel(cpu_to_be32(val32), target);
1043 readl(target);
1044
1045 del_timer_sync(&tbl->watchdog_timer);
1046}
1047
1048static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1049{
1050 pci_dev_get(dev);
1051 set_pci_iommu(dev->bus, NULL);
1052
1053
1054 if (dev->bus->parent)
1055 dev->bus->parent->self = dev;
1056 else
1057 dev->bus->self = dev;
1058}
1059
1060static int __init calgary_init_one(struct pci_dev *dev)
1061{
1062 void __iomem *bbar;
1063 struct iommu_table *tbl;
1064 int ret;
1065
1066 bbar = busno_to_bbar(dev->bus->number);
1067 ret = calgary_setup_tar(dev, bbar);
1068 if (ret)
1069 goto done;
1070
1071 pci_dev_get(dev);
1072
1073 if (dev->bus->parent) {
1074 if (dev->bus->parent->self)
1075 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1076 "bus->parent->self!\n", dev);
1077 dev->bus->parent->self = dev;
1078 } else
1079 dev->bus->self = dev;
1080
1081 tbl = pci_iommu(dev->bus);
1082 tbl->chip_ops->handle_quirks(tbl, dev);
1083
1084 calgary_enable_translation(dev);
1085
1086 return 0;
1087
1088done:
1089 return ret;
1090}
1091
1092static int __init calgary_locate_bbars(void)
1093{
1094 int ret;
1095 int rioidx, phb, bus;
1096 void __iomem *bbar;
1097 void __iomem *target;
1098 unsigned long offset;
1099 u8 start_bus, end_bus;
1100 u32 val;
1101
1102 ret = -ENODATA;
1103 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1104 struct rio_detail *rio = rio_devs[rioidx];
1105
1106 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1107 continue;
1108
1109
1110 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1111 if (!bbar)
1112 goto error;
1113
1114 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1115 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1116 target = calgary_reg(bbar, offset);
1117
1118 val = be32_to_cpu(readl(target));
1119
1120 start_bus = (u8)((val & 0x00FF0000) >> 16);
1121 end_bus = (u8)((val & 0x0000FF00) >> 8);
1122
1123 if (end_bus) {
1124 for (bus = start_bus; bus <= end_bus; bus++) {
1125 bus_info[bus].bbar = bbar;
1126 bus_info[bus].phbid = phb;
1127 }
1128 } else {
1129 bus_info[start_bus].bbar = bbar;
1130 bus_info[start_bus].phbid = phb;
1131 }
1132 }
1133 }
1134
1135 return 0;
1136
1137error:
1138
1139 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1140 if (bus_info[bus].bbar)
1141 iounmap(bus_info[bus].bbar);
1142
1143 return ret;
1144}
1145
1146static int __init calgary_init(void)
1147{
1148 int ret;
1149 struct pci_dev *dev = NULL;
1150 struct calgary_bus_info *info;
1151
1152 ret = calgary_locate_bbars();
1153 if (ret)
1154 return ret;
1155
1156
1157 if (is_kdump_kernel())
1158 get_tce_space_from_tar();
1159
1160 do {
1161 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1162 if (!dev)
1163 break;
1164 if (!is_cal_pci_dev(dev->device))
1165 continue;
1166
1167 info = &bus_info[dev->bus->number];
1168 if (info->translation_disabled) {
1169 calgary_init_one_nontraslated(dev);
1170 continue;
1171 }
1172
1173 if (!info->tce_space && !translate_empty_slots)
1174 continue;
1175
1176 ret = calgary_init_one(dev);
1177 if (ret)
1178 goto error;
1179 } while (1);
1180
1181 dev = NULL;
1182 for_each_pci_dev(dev) {
1183 struct iommu_table *tbl;
1184
1185 tbl = find_iommu_table(&dev->dev);
1186
1187 if (translation_enabled(tbl))
1188 dev->dev.dma_ops = &calgary_dma_ops;
1189 }
1190
1191 return ret;
1192
1193error:
1194 do {
1195 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1196 if (!dev)
1197 break;
1198 if (!is_cal_pci_dev(dev->device))
1199 continue;
1200
1201 info = &bus_info[dev->bus->number];
1202 if (info->translation_disabled) {
1203 pci_dev_put(dev);
1204 continue;
1205 }
1206 if (!info->tce_space && !translate_empty_slots)
1207 continue;
1208
1209 calgary_disable_translation(dev);
1210 calgary_free_bus(dev);
1211 pci_dev_put(dev);
1212 dev->dev.dma_ops = NULL;
1213 } while (1);
1214
1215 return ret;
1216}
1217
1218static inline int __init determine_tce_table_size(void)
1219{
1220 int ret;
1221
1222 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1223 return specified_table_size;
1224
1225 if (is_kdump_kernel() && saved_max_pfn) {
1226
1227
1228
1229
1230
1231
1232
1233 ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
1234 if (ret > TCE_TABLE_SIZE_8M)
1235 ret = TCE_TABLE_SIZE_8M;
1236 } else {
1237
1238
1239
1240
1241 ret = TCE_TABLE_SIZE_8M;
1242 }
1243
1244 return ret;
1245}
1246
1247static int __init build_detail_arrays(void)
1248{
1249 unsigned long ptr;
1250 unsigned numnodes, i;
1251 int scal_detail_size, rio_detail_size;
1252
1253 numnodes = rio_table_hdr->num_scal_dev;
1254 if (numnodes > MAX_NUMNODES){
1255 printk(KERN_WARNING
1256 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1257 "but system has %d nodes.\n",
1258 MAX_NUMNODES, numnodes);
1259 return -ENODEV;
1260 }
1261
1262 switch (rio_table_hdr->version){
1263 case 2:
1264 scal_detail_size = 11;
1265 rio_detail_size = 13;
1266 break;
1267 case 3:
1268 scal_detail_size = 12;
1269 rio_detail_size = 15;
1270 break;
1271 default:
1272 printk(KERN_WARNING
1273 "Calgary: Invalid Rio Grande Table Version: %d\n",
1274 rio_table_hdr->version);
1275 return -EPROTO;
1276 }
1277
1278 ptr = ((unsigned long)rio_table_hdr) + 3;
1279 for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1280 scal_devs[i] = (struct scal_detail *)ptr;
1281
1282 for (i = 0; i < rio_table_hdr->num_rio_dev;
1283 i++, ptr += rio_detail_size)
1284 rio_devs[i] = (struct rio_detail *)ptr;
1285
1286 return 0;
1287}
1288
1289static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1290{
1291 int dev;
1292 u32 val;
1293
1294 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1295
1296
1297
1298
1299 return 1;
1300 }
1301
1302 for (dev = 1; dev < 8; dev++) {
1303 val = read_pci_config(bus, dev, 0, 0);
1304 if (val != 0xffffffff)
1305 break;
1306 }
1307 return (val != 0xffffffff);
1308}
1309
1310
1311
1312
1313
1314
1315static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1316{
1317 u64 *tp;
1318 unsigned int index;
1319 tp = ((u64 *)tbl->it_base);
1320 for (index = 0 ; index < tbl->it_size; index++) {
1321 if (*tp != 0x0)
1322 set_bit(index, tbl->it_map);
1323 tp++;
1324 }
1325}
1326
1327
1328
1329
1330
1331
1332static void __init get_tce_space_from_tar(void)
1333{
1334 int bus;
1335 void __iomem *target;
1336 unsigned long tce_space;
1337
1338 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1339 struct calgary_bus_info *info = &bus_info[bus];
1340 unsigned short pci_device;
1341 u32 val;
1342
1343 val = read_pci_config(bus, 0, 0, 0);
1344 pci_device = (val & 0xFFFF0000) >> 16;
1345
1346 if (!is_cal_pci_dev(pci_device))
1347 continue;
1348 if (info->translation_disabled)
1349 continue;
1350
1351 if (calgary_bus_has_devices(bus, pci_device) ||
1352 translate_empty_slots) {
1353 target = calgary_reg(bus_info[bus].bbar,
1354 tar_offset(bus));
1355 tce_space = be64_to_cpu(readq(target));
1356 tce_space = tce_space & TAR_SW_BITS;
1357
1358 tce_space = tce_space & (~specified_table_size);
1359 info->tce_space = (u64 *)__va(tce_space);
1360 }
1361 }
1362 return;
1363}
1364
1365static int __init calgary_iommu_init(void)
1366{
1367 int ret;
1368
1369
1370 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1371
1372 ret = calgary_init();
1373 if (ret) {
1374 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1375 "falling back to no_iommu\n", ret);
1376 return ret;
1377 }
1378
1379 return 0;
1380}
1381
1382int __init detect_calgary(void)
1383{
1384 int bus;
1385 void *tbl;
1386 int calgary_found = 0;
1387 unsigned long ptr;
1388 unsigned int offset, prev_offset;
1389 int ret;
1390
1391
1392
1393
1394
1395 if (no_iommu || iommu_detected)
1396 return -ENODEV;
1397
1398 if (!use_calgary)
1399 return -ENODEV;
1400
1401 if (!early_pci_allowed())
1402 return -ENODEV;
1403
1404 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1405
1406 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1407
1408 rio_table_hdr = NULL;
1409 prev_offset = 0;
1410 offset = 0x180;
1411
1412
1413
1414
1415 while (offset > prev_offset) {
1416
1417 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1418
1419 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1420 break;
1421 }
1422 prev_offset = offset;
1423 offset = *((unsigned short *)(ptr + offset));
1424 }
1425 if (!rio_table_hdr) {
1426 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1427 "in EBDA - bailing!\n");
1428 return -ENODEV;
1429 }
1430
1431 ret = build_detail_arrays();
1432 if (ret) {
1433 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1434 return -ENOMEM;
1435 }
1436
1437 specified_table_size = determine_tce_table_size();
1438
1439 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1440 struct calgary_bus_info *info = &bus_info[bus];
1441 unsigned short pci_device;
1442 u32 val;
1443
1444 val = read_pci_config(bus, 0, 0, 0);
1445 pci_device = (val & 0xFFFF0000) >> 16;
1446
1447 if (!is_cal_pci_dev(pci_device))
1448 continue;
1449
1450 if (info->translation_disabled)
1451 continue;
1452
1453 if (calgary_bus_has_devices(bus, pci_device) ||
1454 translate_empty_slots) {
1455
1456
1457
1458
1459 if (!is_kdump_kernel()) {
1460 tbl = alloc_tce_table();
1461 if (!tbl)
1462 goto cleanup;
1463 info->tce_space = tbl;
1464 }
1465 calgary_found = 1;
1466 }
1467 }
1468
1469 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1470 calgary_found ? "found" : "not found");
1471
1472 if (calgary_found) {
1473 iommu_detected = 1;
1474 calgary_detected = 1;
1475 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1476 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1477 specified_table_size);
1478
1479 x86_init.iommu.iommu_init = calgary_iommu_init;
1480 }
1481 return calgary_found;
1482
1483cleanup:
1484 for (--bus; bus >= 0; --bus) {
1485 struct calgary_bus_info *info = &bus_info[bus];
1486
1487 if (info->tce_space)
1488 free_tce_table(info->tce_space);
1489 }
1490 return -ENOMEM;
1491}
1492
1493static int __init calgary_parse_options(char *p)
1494{
1495 unsigned int bridge;
1496 unsigned long val;
1497 size_t len;
1498 ssize_t ret;
1499
1500 while (*p) {
1501 if (!strncmp(p, "64k", 3))
1502 specified_table_size = TCE_TABLE_SIZE_64K;
1503 else if (!strncmp(p, "128k", 4))
1504 specified_table_size = TCE_TABLE_SIZE_128K;
1505 else if (!strncmp(p, "256k", 4))
1506 specified_table_size = TCE_TABLE_SIZE_256K;
1507 else if (!strncmp(p, "512k", 4))
1508 specified_table_size = TCE_TABLE_SIZE_512K;
1509 else if (!strncmp(p, "1M", 2))
1510 specified_table_size = TCE_TABLE_SIZE_1M;
1511 else if (!strncmp(p, "2M", 2))
1512 specified_table_size = TCE_TABLE_SIZE_2M;
1513 else if (!strncmp(p, "4M", 2))
1514 specified_table_size = TCE_TABLE_SIZE_4M;
1515 else if (!strncmp(p, "8M", 2))
1516 specified_table_size = TCE_TABLE_SIZE_8M;
1517
1518 len = strlen("translate_empty_slots");
1519 if (!strncmp(p, "translate_empty_slots", len))
1520 translate_empty_slots = 1;
1521
1522 len = strlen("disable");
1523 if (!strncmp(p, "disable", len)) {
1524 p += len;
1525 if (*p == '=')
1526 ++p;
1527 if (*p == '\0')
1528 break;
1529 ret = kstrtoul(p, 0, &val);
1530 if (ret)
1531 break;
1532
1533 bridge = val;
1534 if (bridge < MAX_PHB_BUS_NUM) {
1535 printk(KERN_INFO "Calgary: disabling "
1536 "translation for PHB %#x\n", bridge);
1537 bus_info[bridge].translation_disabled = 1;
1538 }
1539 }
1540
1541 p = strpbrk(p, ",");
1542 if (!p)
1543 break;
1544
1545 p++;
1546 }
1547 return 1;
1548}
1549__setup("calgary=", calgary_parse_options);
1550
1551static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1552{
1553 struct iommu_table *tbl;
1554 unsigned int npages;
1555 int i;
1556
1557 tbl = pci_iommu(dev->bus);
1558
1559 for (i = 0; i < 4; i++) {
1560 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1561
1562
1563 if (!(r->flags & IORESOURCE_MEM))
1564 continue;
1565
1566
1567 if (!r->start)
1568 continue;
1569
1570
1571 npages = resource_size(r) >> PAGE_SHIFT;
1572 npages++;
1573
1574 iommu_range_reserve(tbl, r->start, npages);
1575 }
1576}
1577
1578static int __init calgary_fixup_tce_spaces(void)
1579{
1580 struct pci_dev *dev = NULL;
1581 struct calgary_bus_info *info;
1582
1583 if (no_iommu || swiotlb || !calgary_detected)
1584 return -ENODEV;
1585
1586 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1587
1588 do {
1589 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1590 if (!dev)
1591 break;
1592 if (!is_cal_pci_dev(dev->device))
1593 continue;
1594
1595 info = &bus_info[dev->bus->number];
1596 if (info->translation_disabled)
1597 continue;
1598
1599 if (!info->tce_space)
1600 continue;
1601
1602 calgary_fixup_one_tce_space(dev);
1603
1604 } while (1);
1605
1606 return 0;
1607}
1608
1609
1610
1611
1612
1613rootfs_initcall(calgary_fixup_tce_spaces);
1614
1615IOMMU_INIT_POST(detect_calgary);
1616