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18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/mm.h>
21#include <linux/proc_fs.h>
22#include <linux/screen_info.h>
23#include <linux/bootmem.h>
24#include <linux/kernel.h>
25#include <linux/percpu.h>
26#include <linux/cpu.h>
27#include <linux/of.h>
28#include <linux/of_fdt.h>
29
30#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31# include <linux/console.h>
32#endif
33
34#ifdef CONFIG_PROC_FS
35# include <linux/seq_file.h>
36#endif
37
38#include <asm/bootparam.h>
39#include <asm/mmu_context.h>
40#include <asm/pgtable.h>
41#include <asm/processor.h>
42#include <asm/timex.h>
43#include <asm/platform.h>
44#include <asm/page.h>
45#include <asm/setup.h>
46#include <asm/param.h>
47#include <asm/smp.h>
48#include <asm/sysmem.h>
49
50#include <platform/hardware.h>
51
52#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
53struct screen_info screen_info = {
54 .orig_x = 0,
55 .orig_y = 24,
56 .orig_video_cols = 80,
57 .orig_video_lines = 24,
58 .orig_video_isVGA = 1,
59 .orig_video_points = 16,
60};
61#endif
62
63#ifdef CONFIG_BLK_DEV_INITRD
64extern unsigned long initrd_start;
65extern unsigned long initrd_end;
66int initrd_is_mapped = 0;
67extern int initrd_below_start_ok;
68#endif
69
70#ifdef CONFIG_OF
71void *dtb_start = __dtb_start;
72#endif
73
74extern unsigned long loops_per_jiffy;
75
76
77
78static char __initdata command_line[COMMAND_LINE_SIZE];
79
80#ifdef CONFIG_CMDLINE_BOOL
81static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
82#endif
83
84
85
86
87
88
89
90
91
92
93typedef struct tagtable {
94 u32 tag;
95 int (*parse)(const bp_tag_t*);
96} tagtable_t;
97
98#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
99 __attribute__((used, section(".taglist"))) = { tag, fn }
100
101
102
103static int __init parse_tag_mem(const bp_tag_t *tag)
104{
105 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
106
107 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
108 return -1;
109
110 return memblock_add(mi->start, mi->end - mi->start);
111}
112
113__tagtable(BP_TAG_MEMORY, parse_tag_mem);
114
115#ifdef CONFIG_BLK_DEV_INITRD
116
117static int __init parse_tag_initrd(const bp_tag_t* tag)
118{
119 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
120
121 initrd_start = (unsigned long)__va(mi->start);
122 initrd_end = (unsigned long)__va(mi->end);
123
124 return 0;
125}
126
127__tagtable(BP_TAG_INITRD, parse_tag_initrd);
128
129#endif
130
131#ifdef CONFIG_OF
132
133static int __init parse_tag_fdt(const bp_tag_t *tag)
134{
135 dtb_start = __va(tag->data[0]);
136 return 0;
137}
138
139__tagtable(BP_TAG_FDT, parse_tag_fdt);
140
141#endif
142
143static int __init parse_tag_cmdline(const bp_tag_t* tag)
144{
145 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
146 return 0;
147}
148
149__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
150
151static int __init parse_bootparam(const bp_tag_t* tag)
152{
153 extern tagtable_t __tagtable_begin, __tagtable_end;
154 tagtable_t *t;
155
156
157
158 if (tag->id != BP_TAG_FIRST) {
159 printk(KERN_WARNING "Invalid boot parameters!\n");
160 return 0;
161 }
162
163 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
164
165
166
167 while (tag != NULL && tag->id != BP_TAG_LAST) {
168 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
169 if (tag->id == t->tag) {
170 t->parse(tag);
171 break;
172 }
173 }
174 if (t == &__tagtable_end)
175 printk(KERN_WARNING "Ignoring tag "
176 "0x%08x\n", tag->id);
177 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
178 }
179
180 return 0;
181}
182
183#ifdef CONFIG_OF
184
185#if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
186unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
187EXPORT_SYMBOL(xtensa_kio_paddr);
188
189static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
190 int depth, void *data)
191{
192 const __be32 *ranges;
193 int len;
194
195 if (depth > 1)
196 return 0;
197
198 if (!of_flat_dt_is_compatible(node, "simple-bus"))
199 return 0;
200
201 ranges = of_get_flat_dt_prop(node, "ranges", &len);
202 if (!ranges)
203 return 1;
204 if (len == 0)
205 return 1;
206
207 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
208
209 xtensa_kio_paddr &= 0xf0000000;
210
211 return 1;
212}
213#else
214static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
215 int depth, void *data)
216{
217 return 1;
218}
219#endif
220
221void __init early_init_dt_add_memory_arch(u64 base, u64 size)
222{
223 size &= PAGE_MASK;
224 memblock_add(base, size);
225}
226
227void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
228{
229 return __alloc_bootmem(size, align, 0);
230}
231
232void __init early_init_devtree(void *params)
233{
234 early_init_dt_scan(params);
235 of_scan_flat_dt(xtensa_dt_io_area, NULL);
236
237 if (!command_line[0])
238 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
239}
240
241#endif
242
243
244
245
246
247void __init init_arch(bp_tag_t *bp_start)
248{
249
250
251 if (bp_start)
252 parse_bootparam(bp_start);
253
254#ifdef CONFIG_OF
255 early_init_devtree(dtb_start);
256#endif
257
258#ifdef CONFIG_CMDLINE_BOOL
259 if (!command_line[0])
260 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
261#endif
262
263
264
265 platform_init(bp_start);
266
267
268
269 init_mmu();
270}
271
272
273
274
275
276extern char _end;
277extern char _stext;
278extern char _WindowVectors_text_start;
279extern char _WindowVectors_text_end;
280extern char _DebugInterruptVector_literal_start;
281extern char _DebugInterruptVector_text_end;
282extern char _KernelExceptionVector_literal_start;
283extern char _KernelExceptionVector_text_end;
284extern char _UserExceptionVector_literal_start;
285extern char _UserExceptionVector_text_end;
286extern char _DoubleExceptionVector_literal_start;
287extern char _DoubleExceptionVector_text_end;
288#if XCHAL_EXCM_LEVEL >= 2
289extern char _Level2InterruptVector_text_start;
290extern char _Level2InterruptVector_text_end;
291#endif
292#if XCHAL_EXCM_LEVEL >= 3
293extern char _Level3InterruptVector_text_start;
294extern char _Level3InterruptVector_text_end;
295#endif
296#if XCHAL_EXCM_LEVEL >= 4
297extern char _Level4InterruptVector_text_start;
298extern char _Level4InterruptVector_text_end;
299#endif
300#if XCHAL_EXCM_LEVEL >= 5
301extern char _Level5InterruptVector_text_start;
302extern char _Level5InterruptVector_text_end;
303#endif
304#if XCHAL_EXCM_LEVEL >= 6
305extern char _Level6InterruptVector_text_start;
306extern char _Level6InterruptVector_text_end;
307#endif
308#ifdef CONFIG_SMP
309extern char _SecondaryResetVector_text_start;
310extern char _SecondaryResetVector_text_end;
311#endif
312
313static inline int mem_reserve(unsigned long start, unsigned long end)
314{
315 return memblock_reserve(start, end - start);
316}
317
318void __init setup_arch(char **cmdline_p)
319{
320 *cmdline_p = command_line;
321 platform_setup(cmdline_p);
322 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
323
324
325
326#ifdef CONFIG_BLK_DEV_INITRD
327 if (initrd_start < initrd_end) {
328 initrd_is_mapped = mem_reserve(__pa(initrd_start),
329 __pa(initrd_end)) == 0;
330 initrd_below_start_ok = 1;
331 } else {
332 initrd_start = 0;
333 }
334#endif
335
336 mem_reserve(__pa(&_stext), __pa(&_end));
337
338#ifdef CONFIG_VECTORS_OFFSET
339 mem_reserve(__pa(&_WindowVectors_text_start),
340 __pa(&_WindowVectors_text_end));
341
342 mem_reserve(__pa(&_DebugInterruptVector_literal_start),
343 __pa(&_DebugInterruptVector_text_end));
344
345 mem_reserve(__pa(&_KernelExceptionVector_literal_start),
346 __pa(&_KernelExceptionVector_text_end));
347
348 mem_reserve(__pa(&_UserExceptionVector_literal_start),
349 __pa(&_UserExceptionVector_text_end));
350
351 mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
352 __pa(&_DoubleExceptionVector_text_end));
353
354#if XCHAL_EXCM_LEVEL >= 2
355 mem_reserve(__pa(&_Level2InterruptVector_text_start),
356 __pa(&_Level2InterruptVector_text_end));
357#endif
358#if XCHAL_EXCM_LEVEL >= 3
359 mem_reserve(__pa(&_Level3InterruptVector_text_start),
360 __pa(&_Level3InterruptVector_text_end));
361#endif
362#if XCHAL_EXCM_LEVEL >= 4
363 mem_reserve(__pa(&_Level4InterruptVector_text_start),
364 __pa(&_Level4InterruptVector_text_end));
365#endif
366#if XCHAL_EXCM_LEVEL >= 5
367 mem_reserve(__pa(&_Level5InterruptVector_text_start),
368 __pa(&_Level5InterruptVector_text_end));
369#endif
370#if XCHAL_EXCM_LEVEL >= 6
371 mem_reserve(__pa(&_Level6InterruptVector_text_start),
372 __pa(&_Level6InterruptVector_text_end));
373#endif
374
375#endif
376
377#ifdef CONFIG_SMP
378 mem_reserve(__pa(&_SecondaryResetVector_text_start),
379 __pa(&_SecondaryResetVector_text_end));
380#endif
381 parse_early_param();
382 bootmem_init();
383
384 unflatten_and_copy_device_tree();
385
386#ifdef CONFIG_SMP
387 smp_init_cpus();
388#endif
389
390 paging_init();
391 zones_init();
392
393#ifdef CONFIG_VT
394# if defined(CONFIG_VGA_CONSOLE)
395 conswitchp = &vga_con;
396# elif defined(CONFIG_DUMMY_CONSOLE)
397 conswitchp = &dummy_con;
398# endif
399#endif
400
401#ifdef CONFIG_PCI
402 platform_pcibios_init();
403#endif
404}
405
406static DEFINE_PER_CPU(struct cpu, cpu_data);
407
408static int __init topology_init(void)
409{
410 int i;
411
412 for_each_possible_cpu(i) {
413 struct cpu *cpu = &per_cpu(cpu_data, i);
414 cpu->hotpluggable = !!i;
415 register_cpu(cpu, i);
416 }
417
418 return 0;
419}
420subsys_initcall(topology_init);
421
422void cpu_reset(void)
423{
424#if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
425 local_irq_disable();
426
427
428
429
430
431
432
433
434 local_flush_tlb_all();
435 invalidate_page_directory();
436#if XCHAL_HAVE_SPANNING_WAY
437
438 {
439 unsigned long vaddr = (unsigned long)cpu_reset;
440 unsigned long paddr = __pa(vaddr);
441 unsigned long tmpaddr = vaddr + SZ_512M;
442 unsigned long tmp0, tmp1, tmp2, tmp3;
443
444
445
446
447
448
449
450
451 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
452 tmpaddr += SZ_512M;
453
454
455 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
456 invalidate_itlb_entry(itlb_probe(tmpaddr));
457 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
458 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
459
460
461
462
463
464 write_itlb_entry(__pte((paddr & PAGE_MASK) |
465 _PAGE_HW_VALID |
466 _PAGE_HW_EXEC |
467 _PAGE_CA_BYPASS),
468 tmpaddr & PAGE_MASK);
469 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
470 _PAGE_HW_VALID |
471 _PAGE_HW_EXEC |
472 _PAGE_CA_BYPASS),
473 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
474
475
476 __asm__ __volatile__ ("movi %0, 1f\n\t"
477 "movi %3, 2f\n\t"
478 "add %0, %0, %4\n\t"
479 "add %3, %3, %5\n\t"
480 "jx %0\n"
481
482
483
484
485 "1:\n\t"
486
487 "movi %0, 0\n\t"
488 "wsr %0, itlbcfg\n\t"
489 "wsr %0, dtlbcfg\n\t"
490
491 "movi %0, 4\n\t"
492 "movi %1, 5\n"
493 "1:\n\t"
494 "iitlb %1\n\t"
495 "idtlb %1\n\t"
496 "add %1, %1, %6\n\t"
497 "addi %0, %0, -1\n\t"
498 "bnez %0, 1b\n\t"
499
500 "movi %0, 7\n\t"
501 "addi %1, %9, 3\n\t"
502 "addi %2, %9, 6\n"
503 "1:\n\t"
504 "witlb %1, %2\n\t"
505 "wdtlb %1, %2\n\t"
506 "add %1, %1, %7\n\t"
507 "add %2, %2, %7\n\t"
508 "addi %0, %0, -1\n\t"
509 "bnez %0, 1b\n\t"
510
511 "jx %3\n"
512 "2:\n\t"
513
514 "witlb %1, %2\n\t"
515 "wdtlb %1, %2\n\t"
516
517 "sub %0, %9, %7\n\t"
518 "iitlb %0\n\t"
519 "add %0, %0, %8\n\t"
520 "iitlb %0"
521 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
522 "=&a"(tmp3)
523 : "a"(tmpaddr - vaddr),
524 "a"(paddr - vaddr),
525 "a"(SZ_128M), "a"(SZ_512M),
526 "a"(PAGE_SIZE),
527 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
528 : "memory");
529 }
530#endif
531#endif
532 __asm__ __volatile__ ("movi a2, 0\n\t"
533 "wsr a2, icountlevel\n\t"
534 "movi a2, 0\n\t"
535 "wsr a2, icount\n\t"
536#if XCHAL_NUM_IBREAK > 0
537 "wsr a2, ibreakenable\n\t"
538#endif
539#if XCHAL_HAVE_LOOPS
540 "wsr a2, lcount\n\t"
541#endif
542 "movi a2, 0x1f\n\t"
543 "wsr a2, ps\n\t"
544 "isync\n\t"
545 "jx %0\n\t"
546 :
547 : "a" (XCHAL_RESET_VECTOR_VADDR)
548 : "a2");
549 for (;;)
550 ;
551}
552
553void machine_restart(char * cmd)
554{
555 platform_restart();
556}
557
558void machine_halt(void)
559{
560 platform_halt();
561 while (1);
562}
563
564void machine_power_off(void)
565{
566 platform_power_off();
567 while (1);
568}
569#ifdef CONFIG_PROC_FS
570
571
572
573
574
575static int
576c_show(struct seq_file *f, void *slot)
577{
578
579 seq_printf(f, "CPU count\t: %u\n"
580 "CPU list\t: %*pbl\n"
581 "vendor_id\t: Tensilica\n"
582 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
583 "core ID\t\t: " XCHAL_CORE_ID "\n"
584 "build ID\t: 0x%x\n"
585 "byte order\t: %s\n"
586 "cpu MHz\t\t: %lu.%02lu\n"
587 "bogomips\t: %lu.%02lu\n",
588 num_online_cpus(),
589 cpumask_pr_args(cpu_online_mask),
590 XCHAL_BUILD_UNIQUE_ID,
591 XCHAL_HAVE_BE ? "big" : "little",
592 ccount_freq/1000000,
593 (ccount_freq/10000) % 100,
594 loops_per_jiffy/(500000/HZ),
595 (loops_per_jiffy/(5000/HZ)) % 100);
596 seq_puts(f, "flags\t\t: "
597#if XCHAL_HAVE_NMI
598 "nmi "
599#endif
600#if XCHAL_HAVE_DEBUG
601 "debug "
602# if XCHAL_HAVE_OCD
603 "ocd "
604# endif
605#endif
606#if XCHAL_HAVE_DENSITY
607 "density "
608#endif
609#if XCHAL_HAVE_BOOLEANS
610 "boolean "
611#endif
612#if XCHAL_HAVE_LOOPS
613 "loop "
614#endif
615#if XCHAL_HAVE_NSA
616 "nsa "
617#endif
618#if XCHAL_HAVE_MINMAX
619 "minmax "
620#endif
621#if XCHAL_HAVE_SEXT
622 "sext "
623#endif
624#if XCHAL_HAVE_CLAMPS
625 "clamps "
626#endif
627#if XCHAL_HAVE_MAC16
628 "mac16 "
629#endif
630#if XCHAL_HAVE_MUL16
631 "mul16 "
632#endif
633#if XCHAL_HAVE_MUL32
634 "mul32 "
635#endif
636#if XCHAL_HAVE_MUL32_HIGH
637 "mul32h "
638#endif
639#if XCHAL_HAVE_FP
640 "fpu "
641#endif
642#if XCHAL_HAVE_S32C1I
643 "s32c1i "
644#endif
645 "\n");
646
647
648 seq_printf(f,"physical aregs\t: %d\n"
649 "misc regs\t: %d\n"
650 "ibreak\t\t: %d\n"
651 "dbreak\t\t: %d\n",
652 XCHAL_NUM_AREGS,
653 XCHAL_NUM_MISC_REGS,
654 XCHAL_NUM_IBREAK,
655 XCHAL_NUM_DBREAK);
656
657
658
659 seq_printf(f,"num ints\t: %d\n"
660 "ext ints\t: %d\n"
661 "int levels\t: %d\n"
662 "timers\t\t: %d\n"
663 "debug level\t: %d\n",
664 XCHAL_NUM_INTERRUPTS,
665 XCHAL_NUM_EXTINTERRUPTS,
666 XCHAL_NUM_INTLEVELS,
667 XCHAL_NUM_TIMERS,
668 XCHAL_DEBUGLEVEL);
669
670
671 seq_printf(f,"icache line size: %d\n"
672 "icache ways\t: %d\n"
673 "icache size\t: %d\n"
674 "icache flags\t: "
675#if XCHAL_ICACHE_LINE_LOCKABLE
676 "lock "
677#endif
678 "\n"
679 "dcache line size: %d\n"
680 "dcache ways\t: %d\n"
681 "dcache size\t: %d\n"
682 "dcache flags\t: "
683#if XCHAL_DCACHE_IS_WRITEBACK
684 "writeback "
685#endif
686#if XCHAL_DCACHE_LINE_LOCKABLE
687 "lock "
688#endif
689 "\n",
690 XCHAL_ICACHE_LINESIZE,
691 XCHAL_ICACHE_WAYS,
692 XCHAL_ICACHE_SIZE,
693 XCHAL_DCACHE_LINESIZE,
694 XCHAL_DCACHE_WAYS,
695 XCHAL_DCACHE_SIZE);
696
697 return 0;
698}
699
700
701
702
703static void *
704c_start(struct seq_file *f, loff_t *pos)
705{
706 return (*pos == 0) ? (void *)1 : NULL;
707}
708
709static void *
710c_next(struct seq_file *f, void *v, loff_t *pos)
711{
712 return NULL;
713}
714
715static void
716c_stop(struct seq_file *f, void *v)
717{
718}
719
720const struct seq_operations cpuinfo_op =
721{
722 .start = c_start,
723 .next = c_next,
724 .stop = c_stop,
725 .show = c_show,
726};
727
728#endif
729
