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26#include <linux/kernel.h>
27#include <linux/interrupt.h>
28#include <linux/module.h>
29#include <linux/mm.h>
30#include <linux/dma-mapping.h>
31#include <linux/raid/xor.h>
32#include <linux/async_tx.h>
33
34
35static __async_inline struct dma_async_tx_descriptor *
36do_async_xor(struct dma_chan *chan, struct dmaengine_unmap_data *unmap,
37 struct async_submit_ctl *submit)
38{
39 struct dma_device *dma = chan->device;
40 struct dma_async_tx_descriptor *tx = NULL;
41 dma_async_tx_callback cb_fn_orig = submit->cb_fn;
42 void *cb_param_orig = submit->cb_param;
43 enum async_tx_flags flags_orig = submit->flags;
44 enum dma_ctrl_flags dma_flags = 0;
45 int src_cnt = unmap->to_cnt;
46 int xor_src_cnt;
47 dma_addr_t dma_dest = unmap->addr[unmap->to_cnt];
48 dma_addr_t *src_list = unmap->addr;
49
50 while (src_cnt) {
51 dma_addr_t tmp;
52
53 submit->flags = flags_orig;
54 xor_src_cnt = min(src_cnt, (int)dma->max_xor);
55
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57
58 if (src_cnt > xor_src_cnt) {
59 submit->flags &= ~ASYNC_TX_ACK;
60 submit->flags |= ASYNC_TX_FENCE;
61 submit->cb_fn = NULL;
62 submit->cb_param = NULL;
63 } else {
64 submit->cb_fn = cb_fn_orig;
65 submit->cb_param = cb_param_orig;
66 }
67 if (submit->cb_fn)
68 dma_flags |= DMA_PREP_INTERRUPT;
69 if (submit->flags & ASYNC_TX_FENCE)
70 dma_flags |= DMA_PREP_FENCE;
71
72
73
74
75 tmp = src_list[0];
76 if (src_list > unmap->addr)
77 src_list[0] = dma_dest;
78 tx = dma->device_prep_dma_xor(chan, dma_dest, src_list,
79 xor_src_cnt, unmap->len,
80 dma_flags);
81
82 if (unlikely(!tx))
83 async_tx_quiesce(&submit->depend_tx);
84
85
86 while (unlikely(!tx)) {
87 dma_async_issue_pending(chan);
88 tx = dma->device_prep_dma_xor(chan, dma_dest,
89 src_list,
90 xor_src_cnt, unmap->len,
91 dma_flags);
92 }
93 src_list[0] = tmp;
94
95 dma_set_unmap(tx, unmap);
96 async_tx_submit(chan, tx, submit);
97 submit->depend_tx = tx;
98
99 if (src_cnt > xor_src_cnt) {
100
101 src_cnt -= xor_src_cnt;
102
103 src_cnt++;
104 src_list += xor_src_cnt - 1;
105 } else
106 break;
107 }
108
109 return tx;
110}
111
112static void
113do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset,
114 int src_cnt, size_t len, struct async_submit_ctl *submit)
115{
116 int i;
117 int xor_src_cnt = 0;
118 int src_off = 0;
119 void *dest_buf;
120 void **srcs;
121
122 if (submit->scribble)
123 srcs = submit->scribble;
124 else
125 srcs = (void **) src_list;
126
127
128 for (i = 0; i < src_cnt; i++)
129 if (src_list[i])
130 srcs[xor_src_cnt++] = page_address(src_list[i]) + offset;
131 src_cnt = xor_src_cnt;
132
133 dest_buf = page_address(dest) + offset;
134
135 if (submit->flags & ASYNC_TX_XOR_ZERO_DST)
136 memset(dest_buf, 0, len);
137
138 while (src_cnt > 0) {
139
140 xor_src_cnt = min(src_cnt, MAX_XOR_BLOCKS);
141 xor_blocks(xor_src_cnt, len, dest_buf, &srcs[src_off]);
142
143
144 src_cnt -= xor_src_cnt;
145 src_off += xor_src_cnt;
146 }
147
148 async_tx_sync_epilog(submit);
149}
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172struct dma_async_tx_descriptor *
173async_xor(struct page *dest, struct page **src_list, unsigned int offset,
174 int src_cnt, size_t len, struct async_submit_ctl *submit)
175{
176 struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR,
177 &dest, 1, src_list,
178 src_cnt, len);
179 struct dma_device *device = chan ? chan->device : NULL;
180 struct dmaengine_unmap_data *unmap = NULL;
181
182 BUG_ON(src_cnt <= 1);
183
184 if (device)
185 unmap = dmaengine_get_unmap_data(device->dev, src_cnt+1, GFP_NOWAIT);
186
187 if (unmap && is_dma_xor_aligned(device, offset, 0, len)) {
188 struct dma_async_tx_descriptor *tx;
189 int i, j;
190
191
192 pr_debug("%s (async): len: %zu\n", __func__, len);
193
194 unmap->len = len;
195 for (i = 0, j = 0; i < src_cnt; i++) {
196 if (!src_list[i])
197 continue;
198 unmap->to_cnt++;
199 unmap->addr[j++] = dma_map_page(device->dev, src_list[i],
200 offset, len, DMA_TO_DEVICE);
201 }
202
203
204 unmap->addr[j] = dma_map_page(device->dev, dest, offset, len,
205 DMA_BIDIRECTIONAL);
206 unmap->bidi_cnt = 1;
207
208 tx = do_async_xor(chan, unmap, submit);
209 dmaengine_unmap_put(unmap);
210 return tx;
211 } else {
212 dmaengine_unmap_put(unmap);
213
214 pr_debug("%s (sync): len: %zu\n", __func__, len);
215 WARN_ONCE(chan, "%s: no space for dma address conversion\n",
216 __func__);
217
218
219
220
221 if (submit->flags & ASYNC_TX_XOR_DROP_DST) {
222 src_cnt--;
223 src_list++;
224 }
225
226
227 async_tx_quiesce(&submit->depend_tx);
228
229 do_sync_xor(dest, src_list, offset, src_cnt, len, submit);
230
231 return NULL;
232 }
233}
234EXPORT_SYMBOL_GPL(async_xor);
235
236static int page_is_zero(struct page *p, unsigned int offset, size_t len)
237{
238 return !memchr_inv(page_address(p) + offset, 0, len);
239}
240
241static inline struct dma_chan *
242xor_val_chan(struct async_submit_ctl *submit, struct page *dest,
243 struct page **src_list, int src_cnt, size_t len)
244{
245 #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
246 return NULL;
247 #endif
248 return async_tx_find_channel(submit, DMA_XOR_VAL, &dest, 1, src_list,
249 src_cnt, len);
250}
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268struct dma_async_tx_descriptor *
269async_xor_val(struct page *dest, struct page **src_list, unsigned int offset,
270 int src_cnt, size_t len, enum sum_check_flags *result,
271 struct async_submit_ctl *submit)
272{
273 struct dma_chan *chan = xor_val_chan(submit, dest, src_list, src_cnt, len);
274 struct dma_device *device = chan ? chan->device : NULL;
275 struct dma_async_tx_descriptor *tx = NULL;
276 struct dmaengine_unmap_data *unmap = NULL;
277
278 BUG_ON(src_cnt <= 1);
279
280 if (device)
281 unmap = dmaengine_get_unmap_data(device->dev, src_cnt, GFP_NOWAIT);
282
283 if (unmap && src_cnt <= device->max_xor &&
284 is_dma_xor_aligned(device, offset, 0, len)) {
285 unsigned long dma_prep_flags = 0;
286 int i;
287
288 pr_debug("%s: (async) len: %zu\n", __func__, len);
289
290 if (submit->cb_fn)
291 dma_prep_flags |= DMA_PREP_INTERRUPT;
292 if (submit->flags & ASYNC_TX_FENCE)
293 dma_prep_flags |= DMA_PREP_FENCE;
294
295 for (i = 0; i < src_cnt; i++) {
296 unmap->addr[i] = dma_map_page(device->dev, src_list[i],
297 offset, len, DMA_TO_DEVICE);
298 unmap->to_cnt++;
299 }
300 unmap->len = len;
301
302 tx = device->device_prep_dma_xor_val(chan, unmap->addr, src_cnt,
303 len, result,
304 dma_prep_flags);
305 if (unlikely(!tx)) {
306 async_tx_quiesce(&submit->depend_tx);
307
308 while (!tx) {
309 dma_async_issue_pending(chan);
310 tx = device->device_prep_dma_xor_val(chan,
311 unmap->addr, src_cnt, len, result,
312 dma_prep_flags);
313 }
314 }
315 dma_set_unmap(tx, unmap);
316 async_tx_submit(chan, tx, submit);
317 } else {
318 enum async_tx_flags flags_orig = submit->flags;
319
320 pr_debug("%s: (sync) len: %zu\n", __func__, len);
321 WARN_ONCE(device && src_cnt <= device->max_xor,
322 "%s: no space for dma address conversion\n",
323 __func__);
324
325 submit->flags |= ASYNC_TX_XOR_DROP_DST;
326 submit->flags &= ~ASYNC_TX_ACK;
327
328 tx = async_xor(dest, src_list, offset, src_cnt, len, submit);
329
330 async_tx_quiesce(&tx);
331
332 *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P;
333
334 async_tx_sync_epilog(submit);
335 submit->flags = flags_orig;
336 }
337 dmaengine_unmap_put(unmap);
338
339 return tx;
340}
341EXPORT_SYMBOL_GPL(async_xor_val);
342
343MODULE_AUTHOR("Intel Corporation");
344MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api");
345MODULE_LICENSE("GPL");
346