LXR linux/drivers/clk/clk-gemini.c

   1/*
   2 * Cortina Gemini SoC Clock Controller driver
   3 * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
   4 */
   5
   6#define pr_fmt(fmt) "clk-gemini: " fmt
   7
   8#include <linux/init.h>
   9#include <linux/module.h>
  10#include <linux/platform_device.h>
  11#include <linux/slab.h>
  12#include <linux/err.h>
  13#include <linux/io.h>
  14#include <linux/clk-provider.h>
  15#include <linux/of.h>
  16#include <linux/of_address.h>
  17#include <linux/mfd/syscon.h>
  18#include <linux/regmap.h>
  19#include <linux/spinlock.h>
  20#include <linux/reset-controller.h>
  21#include <dt-bindings/reset/cortina,gemini-reset.h>
  22#include <dt-bindings/clock/cortina,gemini-clock.h>
  23
  24/* Globally visible clocks */
  25static DEFINE_SPINLOCK(gemini_clk_lock);
  26
  27#define GEMINI_GLOBAL_STATUS            0x04
  28#define PLL_OSC_SEL                     BIT(30)
  29#define AHBSPEED_SHIFT                  (15)
  30#define AHBSPEED_MASK                   0x07
  31#define CPU_AHB_RATIO_SHIFT             (18)
  32#define CPU_AHB_RATIO_MASK              0x03
  33
  34#define GEMINI_GLOBAL_PLL_CONTROL       0x08
  35
  36#define GEMINI_GLOBAL_SOFT_RESET        0x0c
  37
  38#define GEMINI_GLOBAL_MISC_CONTROL      0x30
  39#define PCI_CLK_66MHZ                   BIT(18)
  40#define PCI_CLK_OE                      BIT(17)
  41
  42#define GEMINI_GLOBAL_CLOCK_CONTROL     0x34
  43#define PCI_CLKRUN_EN                   BIT(16)
  44#define TVC_HALFDIV_SHIFT               (24)
  45#define TVC_HALFDIV_MASK                0x1f
  46#define SECURITY_CLK_SEL                BIT(29)
  47
  48#define GEMINI_GLOBAL_PCI_DLL_CONTROL   0x44
  49#define PCI_DLL_BYPASS                  BIT(31)
  50#define PCI_DLL_TAP_SEL_MASK            0x1f
  51
  52/**
  53 * struct gemini_data_data - Gemini gated clocks
  54 * @bit_idx: the bit used to gate this clock in the clock register
  55 * @name: the clock name
  56 * @parent_name: the name of the parent clock
  57 * @flags: standard clock framework flags
  58 */
  59struct gemini_gate_data {
  60        u8 bit_idx;
  61        const char *name;
  62        const char *parent_name;
  63        unsigned long flags;
  64};
  65
  66/**
  67 * struct clk_gemini_pci - Gemini PCI clock
  68 * @hw: corresponding clock hardware entry
  69 * @map: regmap to access the registers
  70 * @rate: current rate
  71 */
  72struct clk_gemini_pci {
  73        struct clk_hw hw;
  74        struct regmap *map;
  75        unsigned long rate;
  76};
  77
  78/**
  79 * struct gemini_reset - gemini reset controller
  80 * @map: regmap to access the containing system controller
  81 * @rcdev: reset controller device
  82 */
  83struct gemini_reset {
  84        struct regmap *map;
  85        struct reset_controller_dev rcdev;
  86};
  87
  88/* Keeps track of all clocks */
  89static struct clk_hw_onecell_data *gemini_clk_data;
  90
  91static const struct gemini_gate_data gemini_gates[] = {
  92        { 1, "security-gate", "secdiv", 0 },
  93        { 2, "gmac0-gate", "ahb", 0 },
  94        { 3, "gmac1-gate", "ahb", 0 },
  95        { 4, "sata0-gate", "ahb", 0 },
  96        { 5, "sata1-gate", "ahb", 0 },
  97        { 6, "usb0-gate", "ahb", 0 },
  98        { 7, "usb1-gate", "ahb", 0 },
  99        { 8, "ide-gate", "ahb", 0 },
 100        { 9, "pci-gate", "ahb", 0 },
 101        /*
 102         * The DDR controller may never have a driver, but certainly must
 103         * not be gated off.
 104         */
 105        { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
 106        /*
 107         * The flash controller must be on to access NOR flash through the
 108         * memory map.
 109         */
 110        { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
 111        { 12, "tvc-gate", "ahb", 0 },
 112        { 13, "boot-gate", "apb", 0 },
 113};
 114
 115#define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
 116
 117#define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
 118
 119static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
 120                                            unsigned long parent_rate)
 121{
 122        struct clk_gemini_pci *pciclk = to_pciclk(hw);
 123        u32 val;
 124
 125        regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
 126        if (val & PCI_CLK_66MHZ)
 127                return 66000000;
 128        return 33000000;
 129}
 130
 131static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
 132                                  unsigned long *prate)
 133{
 134        /* We support 33 and 66 MHz */
 135        if (rate < 48000000)
 136                return 33000000;
 137        return 66000000;
 138}
 139
 140static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
 141                               unsigned long parent_rate)
 142{
 143        struct clk_gemini_pci *pciclk = to_pciclk(hw);
 144
 145        if (rate == 33000000)
 146                return regmap_update_bits(pciclk->map,
 147                                          GEMINI_GLOBAL_MISC_CONTROL,
 148                                          PCI_CLK_66MHZ, 0);
 149        if (rate == 66000000)
 150                return regmap_update_bits(pciclk->map,
 151                                          GEMINI_GLOBAL_MISC_CONTROL,
 152                                          0, PCI_CLK_66MHZ);
 153        return -EINVAL;
 154}
 155
 156static int gemini_pci_enable(struct clk_hw *hw)
 157{
 158        struct clk_gemini_pci *pciclk = to_pciclk(hw);
 159
 160        regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
 161                           0, PCI_CLKRUN_EN);
 162        regmap_update_bits(pciclk->map,
 163                           GEMINI_GLOBAL_MISC_CONTROL,
 164                           0, PCI_CLK_OE);
 165        return 0;
 166}
 167
 168static void gemini_pci_disable(struct clk_hw *hw)
 169{
 170        struct clk_gemini_pci *pciclk = to_pciclk(hw);
 171
 172        regmap_update_bits(pciclk->map,
 173                           GEMINI_GLOBAL_MISC_CONTROL,
 174                           PCI_CLK_OE, 0);
 175        regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
 176                           PCI_CLKRUN_EN, 0);
 177}
 178
 179static int gemini_pci_is_enabled(struct clk_hw *hw)
 180{
 181        struct clk_gemini_pci *pciclk = to_pciclk(hw);
 182        unsigned int val;
 183
 184        regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
 185        return !!(val & PCI_CLKRUN_EN);
 186}
 187
 188static const struct clk_ops gemini_pci_clk_ops = {
 189        .recalc_rate = gemini_pci_recalc_rate,
 190        .round_rate = gemini_pci_round_rate,
 191        .set_rate = gemini_pci_set_rate,
 192        .enable = gemini_pci_enable,
 193        .disable = gemini_pci_disable,
 194        .is_enabled = gemini_pci_is_enabled,
 195};
 196
 197static struct clk_hw *gemini_pci_clk_setup(const char *name,
 198                                           const char *parent_name,
 199                                           struct regmap *map)
 200{
 201        struct clk_gemini_pci *pciclk;
 202        struct clk_init_data init;
 203        int ret;
 204
 205        pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
 206        if (!pciclk)
 207                return ERR_PTR(-ENOMEM);
 208
 209        init.name = name;
 210        init.ops = &gemini_pci_clk_ops;
 211        init.flags = 0;
 212        init.parent_names = &parent_name;
 213        init.num_parents = 1;
 214        pciclk->map = map;
 215        pciclk->hw.init = &init;
 216
 217        ret = clk_hw_register(NULL, &pciclk->hw);
 218        if (ret) {
 219                kfree(pciclk);
 220                return ERR_PTR(ret);
 221        }
 222
 223        return &pciclk->hw;
 224}
 225
 226/*
 227 * This is a self-deasserting reset controller.
 228 */
 229static int gemini_reset(struct reset_controller_dev *rcdev,
 230                        unsigned long id)
 231{
 232        struct gemini_reset *gr = to_gemini_reset(rcdev);
 233
 234        /* Manual says to always set BIT 30 (CPU1) to 1 */
 235        return regmap_write(gr->map,
 236                            GEMINI_GLOBAL_SOFT_RESET,
 237                            BIT(GEMINI_RESET_CPU1) | BIT(id));
 238}
 239
 240static int gemini_reset_assert(struct reset_controller_dev *rcdev,
 241                               unsigned long id)
 242{
 243        return 0;
 244}
 245
 246static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
 247                                 unsigned long id)
 248{
 249        return 0;
 250}
 251
 252static int gemini_reset_status(struct reset_controller_dev *rcdev,
 253                             unsigned long id)
 254{
 255        struct gemini_reset *gr = to_gemini_reset(rcdev);
 256        u32 val;
 257        int ret;
 258
 259        ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
 260        if (ret)
 261                return ret;
 262
 263        return !!(val & BIT(id));
 264}
 265
 266static const struct reset_control_ops gemini_reset_ops = {
 267        .reset = gemini_reset,
 268        .assert = gemini_reset_assert,
 269        .deassert = gemini_reset_deassert,
 270        .status = gemini_reset_status,
 271};
 272
 273static int gemini_clk_probe(struct platform_device *pdev)
 274{
 275        /* Gives the fracions 1x, 1.5x, 1.85x and 2x */
 276        unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
 277        unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
 278        void __iomem *base;
 279        struct gemini_reset *gr;
 280        struct regmap *map;
 281        struct clk_hw *hw;
 282        struct device *dev = &pdev->dev;
 283        struct device_node *np = dev->of_node;
 284        unsigned int mult, div;
 285        struct resource *res;
 286        u32 val;
 287        int ret;
 288        int i;
 289
 290        gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
 291        if (!gr)
 292                return -ENOMEM;
 293
 294        /* Remap the system controller for the exclusive register */
 295        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 296        base = devm_ioremap_resource(dev, res);
 297        if (IS_ERR(base))
 298                return PTR_ERR(base);
 299
 300        map = syscon_node_to_regmap(np);
 301        if (IS_ERR(map)) {
 302                dev_err(dev, "no syscon regmap\n");
 303                return PTR_ERR(map);
 304        }
 305
 306        gr->map = map;
 307        gr->rcdev.owner = THIS_MODULE;
 308        gr->rcdev.nr_resets = 32;
 309        gr->rcdev.ops = &gemini_reset_ops;
 310        gr->rcdev.of_node = np;
 311
 312        ret = devm_reset_controller_register(dev, &gr->rcdev);
 313        if (ret) {
 314                dev_err(dev, "could not register reset controller\n");
 315                return ret;
 316        }
 317
 318        /* RTC clock 32768 Hz */
 319        hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
 320        gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
 321
 322        /* CPU clock derived as a fixed ratio from the AHB clock */
 323        regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
 324        val >>= CPU_AHB_RATIO_SHIFT;
 325        val &= CPU_AHB_RATIO_MASK;
 326        hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
 327                                          cpu_ahb_mult[val],
 328                                          cpu_ahb_div[val]);
 329        gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
 330
 331        /* Security clock is 1:1 or 0.75 of APB */
 332        regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
 333        if (val & SECURITY_CLK_SEL) {
 334                mult = 1;
 335                div = 1;
 336        } else {
 337                mult = 3;
 338                div = 4;
 339        }
 340        hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
 341
 342        /*
 343         * These are the leaf gates, at boot no clocks are gated.
 344         */
 345        for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
 346                const struct gemini_gate_data *gd;
 347
 348                gd = &gemini_gates[i];
 349                gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
 350                        clk_hw_register_gate(NULL, gd->name,
 351                                             gd->parent_name,
 352                                             gd->flags,
 353                                             base + GEMINI_GLOBAL_CLOCK_CONTROL,
 354                                             gd->bit_idx,
 355                                             CLK_GATE_SET_TO_DISABLE,
 356                                             &gemini_clk_lock);
 357        }
 358
 359        /*
 360         * The TV Interface Controller has a 5-bit half divider register.
 361         * This clock is supposed to be 27MHz as this is an exact multiple
 362         * of PAL and NTSC frequencies. The register is undocumented :(
 363         * FIXME: figure out the parent and how the divider works.
 364         */
 365        mult = 1;
 366        div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
 367        dev_dbg(dev, "TVC half divider value = %d\n", div);
 368        div += 1;
 369        hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
 370        gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
 371
 372        /* FIXME: very unclear what the parent is */
 373        hw = gemini_pci_clk_setup("PCI", "xtal", map);
 374        gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
 375
 376        /* FIXME: very unclear what the parent is */
 377        hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
 378        gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
 379
 380        return 0;
 381}
 382
 383static const struct of_device_id gemini_clk_dt_ids[] = {
 384        { .compatible = "cortina,gemini-syscon", },
 385        { /* sentinel */ },
 386};
 387
 388static struct platform_driver gemini_clk_driver = {
 389        .probe  = gemini_clk_probe,
 390        .driver = {
 391                .name = "gemini-clk",
 392                .of_match_table = gemini_clk_dt_ids,
 393                .suppress_bind_attrs = true,
 394        },
 395};
 396builtin_platform_driver(gemini_clk_driver);
 397
 398static void __init gemini_cc_init(struct device_node *np)
 399{
 400        struct regmap *map;
 401        struct clk_hw *hw;
 402        unsigned long freq;
 403        unsigned int mult, div;
 404        u32 val;
 405        int ret;
 406        int i;
 407
 408        gemini_clk_data = kzalloc(sizeof(*gemini_clk_data) +
 409                        sizeof(*gemini_clk_data->hws) * GEMINI_NUM_CLKS,
 410                        GFP_KERNEL);
 411        if (!gemini_clk_data)
 412                return;
 413
 414        /*
 415         * This way all clock fetched before the platform device probes,
 416         * except those we assign here for early use, will be deferred.
 417         */
 418        for (i = 0; i < GEMINI_NUM_CLKS; i++)
 419                gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
 420
 421        map = syscon_node_to_regmap(np);
 422        if (IS_ERR(map)) {
 423                pr_err("no syscon regmap\n");
 424                return;
 425        }
 426        /*
 427         * We check that the regmap works on this very first access,
 428         * but as this is an MMIO-backed regmap, subsequent regmap
 429         * access is not going to fail and we skip error checks from
 430         * this point.
 431         */
 432        ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
 433        if (ret) {
 434                pr_err("failed to read global status register\n");
 435                return;
 436        }
 437
 438        /*
 439         * XTAL is the crystal oscillator, 60 or 30 MHz selected from
 440         * strap pin E6
 441         */
 442        if (val & PLL_OSC_SEL)
 443                freq = 30000000;
 444        else
 445                freq = 60000000;
 446        hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
 447        pr_debug("main crystal @%lu MHz\n", freq / 1000000);
 448
 449        /* VCO clock derived from the crystal */
 450        mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
 451        div = 2;
 452        /* If we run on 30 MHz crystal we have to multiply with two */
 453        if (val & PLL_OSC_SEL)
 454                mult *= 2;
 455        hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
 456
 457        /* The AHB clock is always 1/3 of the VCO */
 458        hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
 459        gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
 460
 461        /* The APB clock is always 1/6 of the AHB */
 462        hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
 463        gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
 464
 465        /* Register the clocks to be accessed by the device tree */
 466        gemini_clk_data->num = GEMINI_NUM_CLKS;
 467        of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
 468}
 469CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
 470