LXR linux/drivers/clk/mediatek/clk-mt6797-vdec.c

   1/*
   2 * Copyright (c) 2017 MediaTek Inc.
   3 * Author: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 */
  14
  15#include <linux/clk-provider.h>
  16#include <linux/platform_device.h>
  17
  18#include "clk-mtk.h"
  19#include "clk-gate.h"
  20
  21#include <dt-bindings/clock/mt6797-clk.h>
  22
  23static const struct mtk_gate_regs vdec0_cg_regs = {
  24        .set_ofs = 0x0000,
  25        .clr_ofs = 0x0004,
  26        .sta_ofs = 0x0000,
  27};
  28
  29static const struct mtk_gate_regs vdec1_cg_regs = {
  30        .set_ofs = 0x0008,
  31        .clr_ofs = 0x000c,
  32        .sta_ofs = 0x0008,
  33};
  34
  35#define GATE_VDEC0(_id, _name, _parent, _shift) {               \
  36        .id = _id,                                      \
  37        .name = _name,                                  \
  38        .parent_name = _parent,                         \
  39        .regs = &vdec0_cg_regs,                         \
  40        .shift = _shift,                                \
  41        .ops = &mtk_clk_gate_ops_setclr_inv,            \
  42}
  43
  44#define GATE_VDEC1(_id, _name, _parent, _shift) {               \
  45        .id = _id,                                      \
  46        .name = _name,                                  \
  47        .parent_name = _parent,                         \
  48        .regs = &vdec1_cg_regs,                         \
  49        .shift = _shift,                                \
  50        .ops = &mtk_clk_gate_ops_setclr_inv,            \
  51}
  52
  53static const struct mtk_gate vdec_clks[] = {
  54        GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),
  55        GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
  56        GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
  57        GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),
  58};
  59
  60static const struct of_device_id of_match_clk_mt6797_vdec[] = {
  61        { .compatible = "mediatek,mt6797-vdecsys", },
  62        {}
  63};
  64
  65static int clk_mt6797_vdec_probe(struct platform_device *pdev)
  66{
  67        struct clk_onecell_data *clk_data;
  68        int r;
  69        struct device_node *node = pdev->dev.of_node;
  70
  71        clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
  72
  73        mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
  74                               clk_data);
  75
  76        r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  77        if (r)
  78                dev_err(&pdev->dev,
  79                        "could not register clock provider: %s: %d\n",
  80                        pdev->name, r);
  81
  82        return r;
  83}
  84
  85static struct platform_driver clk_mt6797_vdec_drv = {
  86        .probe = clk_mt6797_vdec_probe,
  87        .driver = {
  88                .name = "clk-mt6797-vdec",
  89                .of_match_table = of_match_clk_mt6797_vdec,
  90        },
  91};
  92
  93builtin_platform_driver(clk_mt6797_vdec_drv);
  94