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24#ifndef __AMDGPU_IH_H__
25#define __AMDGPU_IH_H__
26
27struct amdgpu_device;
28
29
30
31enum amdgpu_ih_clientid
32{
33 AMDGPU_IH_CLIENTID_IH = 0x00,
34 AMDGPU_IH_CLIENTID_ACP = 0x01,
35 AMDGPU_IH_CLIENTID_ATHUB = 0x02,
36 AMDGPU_IH_CLIENTID_BIF = 0x03,
37 AMDGPU_IH_CLIENTID_DCE = 0x04,
38 AMDGPU_IH_CLIENTID_ISP = 0x05,
39 AMDGPU_IH_CLIENTID_PCIE0 = 0x06,
40 AMDGPU_IH_CLIENTID_RLC = 0x07,
41 AMDGPU_IH_CLIENTID_SDMA0 = 0x08,
42 AMDGPU_IH_CLIENTID_SDMA1 = 0x09,
43 AMDGPU_IH_CLIENTID_SE0SH = 0x0a,
44 AMDGPU_IH_CLIENTID_SE1SH = 0x0b,
45 AMDGPU_IH_CLIENTID_SE2SH = 0x0c,
46 AMDGPU_IH_CLIENTID_SE3SH = 0x0d,
47 AMDGPU_IH_CLIENTID_SYSHUB = 0x0e,
48 AMDGPU_IH_CLIENTID_THM = 0x0f,
49 AMDGPU_IH_CLIENTID_UVD = 0x10,
50 AMDGPU_IH_CLIENTID_VCE0 = 0x11,
51 AMDGPU_IH_CLIENTID_VMC = 0x12,
52 AMDGPU_IH_CLIENTID_XDMA = 0x13,
53 AMDGPU_IH_CLIENTID_GRBM_CP = 0x14,
54 AMDGPU_IH_CLIENTID_ATS = 0x15,
55 AMDGPU_IH_CLIENTID_ROM_SMUIO = 0x16,
56 AMDGPU_IH_CLIENTID_DF = 0x17,
57 AMDGPU_IH_CLIENTID_VCE1 = 0x18,
58 AMDGPU_IH_CLIENTID_PWR = 0x19,
59 AMDGPU_IH_CLIENTID_UTCL2 = 0x1b,
60 AMDGPU_IH_CLIENTID_EA = 0x1c,
61 AMDGPU_IH_CLIENTID_UTCL2LOG = 0x1d,
62 AMDGPU_IH_CLIENTID_MP0 = 0x1e,
63 AMDGPU_IH_CLIENTID_MP1 = 0x1f,
64
65 AMDGPU_IH_CLIENTID_MAX,
66
67 AMDGPU_IH_CLIENTID_VCN = AMDGPU_IH_CLIENTID_UVD
68};
69
70#define AMDGPU_IH_CLIENTID_LEGACY 0
71
72
73
74
75struct amdgpu_ih_ring {
76 struct amdgpu_bo *ring_obj;
77 volatile uint32_t *ring;
78 unsigned rptr;
79 unsigned ring_size;
80 uint64_t gpu_addr;
81 uint32_t ptr_mask;
82 atomic_t lock;
83 bool enabled;
84 unsigned wptr_offs;
85 unsigned rptr_offs;
86 u32 doorbell_index;
87 bool use_doorbell;
88 bool use_bus_addr;
89 dma_addr_t rb_dma_addr;
90};
91
92#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
93
94struct amdgpu_iv_entry {
95 unsigned client_id;
96 unsigned src_id;
97 unsigned ring_id;
98 unsigned vm_id;
99 unsigned vm_id_src;
100 uint64_t timestamp;
101 unsigned timestamp_src;
102 unsigned pas_id;
103 unsigned pasid_src;
104 unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
105 const uint32_t *iv_entry;
106};
107
108int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
109 bool use_bus_addr);
110void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
111int amdgpu_ih_process(struct amdgpu_device *adev);
112
113#endif
114