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24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "cikd.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
37#include "cik.h"
38#include "gmc_v7_0.h"
39#include "cik_ih.h"
40#include "dce_v8_0.h"
41#include "gfx_v7_0.h"
42#include "cik_sdma.h"
43#include "uvd_v4_2.h"
44#include "vce_v2_0.h"
45#include "cik_dpm.h"
46
47#include "uvd/uvd_4_2_d.h"
48
49#include "smu/smu_7_0_1_d.h"
50#include "smu/smu_7_0_1_sh_mask.h"
51
52#include "dce/dce_8_0_d.h"
53#include "dce/dce_8_0_sh_mask.h"
54
55#include "bif/bif_4_1_d.h"
56#include "bif/bif_4_1_sh_mask.h"
57
58#include "gca/gfx_7_2_d.h"
59#include "gca/gfx_7_2_enum.h"
60#include "gca/gfx_7_2_sh_mask.h"
61
62#include "gmc/gmc_7_1_d.h"
63#include "gmc/gmc_7_1_sh_mask.h"
64
65#include "oss/oss_2_0_d.h"
66#include "oss/oss_2_0_sh_mask.h"
67
68#include "amdgpu_amdkfd.h"
69#include "amdgpu_powerplay.h"
70#include "dce_virtual.h"
71
72
73
74
75static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)
76{
77 unsigned long flags;
78 u32 r;
79
80 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
81 WREG32(mmPCIE_INDEX, reg);
82 (void)RREG32(mmPCIE_INDEX);
83 r = RREG32(mmPCIE_DATA);
84 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
85 return r;
86}
87
88static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
89{
90 unsigned long flags;
91
92 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
93 WREG32(mmPCIE_INDEX, reg);
94 (void)RREG32(mmPCIE_INDEX);
95 WREG32(mmPCIE_DATA, v);
96 (void)RREG32(mmPCIE_DATA);
97 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
98}
99
100static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)
101{
102 unsigned long flags;
103 u32 r;
104
105 spin_lock_irqsave(&adev->smc_idx_lock, flags);
106 WREG32(mmSMC_IND_INDEX_0, (reg));
107 r = RREG32(mmSMC_IND_DATA_0);
108 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
109 return r;
110}
111
112static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
113{
114 unsigned long flags;
115
116 spin_lock_irqsave(&adev->smc_idx_lock, flags);
117 WREG32(mmSMC_IND_INDEX_0, (reg));
118 WREG32(mmSMC_IND_DATA_0, (v));
119 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
120}
121
122static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
123{
124 unsigned long flags;
125 u32 r;
126
127 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
128 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
129 r = RREG32(mmUVD_CTX_DATA);
130 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
131 return r;
132}
133
134static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
135{
136 unsigned long flags;
137
138 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
139 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
140 WREG32(mmUVD_CTX_DATA, (v));
141 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
142}
143
144static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)
145{
146 unsigned long flags;
147 u32 r;
148
149 spin_lock_irqsave(&adev->didt_idx_lock, flags);
150 WREG32(mmDIDT_IND_INDEX, (reg));
151 r = RREG32(mmDIDT_IND_DATA);
152 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
153 return r;
154}
155
156static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
157{
158 unsigned long flags;
159
160 spin_lock_irqsave(&adev->didt_idx_lock, flags);
161 WREG32(mmDIDT_IND_INDEX, (reg));
162 WREG32(mmDIDT_IND_DATA, (v));
163 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
164}
165
166static const u32 bonaire_golden_spm_registers[] =
167{
168 0xc200, 0xe0ffffff, 0xe0000000
169};
170
171static const u32 bonaire_golden_common_registers[] =
172{
173 0x31dc, 0xffffffff, 0x00000800,
174 0x31dd, 0xffffffff, 0x00000800,
175 0x31e6, 0xffffffff, 0x00007fbf,
176 0x31e7, 0xffffffff, 0x00007faf
177};
178
179static const u32 bonaire_golden_registers[] =
180{
181 0xcd5, 0x00000333, 0x00000333,
182 0xcd4, 0x000c0fc0, 0x00040200,
183 0x2684, 0x00010000, 0x00058208,
184 0xf000, 0xffff1fff, 0x00140000,
185 0xf080, 0xfdfc0fff, 0x00000100,
186 0xf08d, 0x40000000, 0x40000200,
187 0x260c, 0xffffffff, 0x00000000,
188 0x260d, 0xf00fffff, 0x00000400,
189 0x260e, 0x0002021c, 0x00020200,
190 0x31e, 0x00000080, 0x00000000,
191 0x16ec, 0x000000f0, 0x00000070,
192 0x16f0, 0xf0311fff, 0x80300000,
193 0x263e, 0x73773777, 0x12010001,
194 0xd43, 0x00810000, 0x408af000,
195 0x1c0c, 0x31000111, 0x00000011,
196 0xbd2, 0x73773777, 0x12010001,
197 0x883, 0x00007fb6, 0x0021a1b1,
198 0x884, 0x00007fb6, 0x002021b1,
199 0x860, 0x00007fb6, 0x00002191,
200 0x886, 0x00007fb6, 0x002121b1,
201 0x887, 0x00007fb6, 0x002021b1,
202 0x877, 0x00007fb6, 0x00002191,
203 0x878, 0x00007fb6, 0x00002191,
204 0xd8a, 0x0000003f, 0x0000000a,
205 0xd8b, 0x0000003f, 0x0000000a,
206 0xab9, 0x00073ffe, 0x000022a2,
207 0x903, 0x000007ff, 0x00000000,
208 0x2285, 0xf000003f, 0x00000007,
209 0x22fc, 0x00002001, 0x00000001,
210 0x22c9, 0xffffffff, 0x00ffffff,
211 0xc281, 0x0000ff0f, 0x00000000,
212 0xa293, 0x07ffffff, 0x06000000,
213 0x136, 0x00000fff, 0x00000100,
214 0xf9e, 0x00000001, 0x00000002,
215 0x2440, 0x03000000, 0x0362c688,
216 0x2300, 0x000000ff, 0x00000001,
217 0x390, 0x00001fff, 0x00001fff,
218 0x2418, 0x0000007f, 0x00000020,
219 0x2542, 0x00010000, 0x00010000,
220 0x2b05, 0x000003ff, 0x000000f3,
221 0x2b03, 0xffffffff, 0x00001032
222};
223
224static const u32 bonaire_mgcg_cgcg_init[] =
225{
226 0x3108, 0xffffffff, 0xfffffffc,
227 0xc200, 0xffffffff, 0xe0000000,
228 0xf0a8, 0xffffffff, 0x00000100,
229 0xf082, 0xffffffff, 0x00000100,
230 0xf0b0, 0xffffffff, 0xc0000100,
231 0xf0b2, 0xffffffff, 0xc0000100,
232 0xf0b1, 0xffffffff, 0xc0000100,
233 0x1579, 0xffffffff, 0x00600100,
234 0xf0a0, 0xffffffff, 0x00000100,
235 0xf085, 0xffffffff, 0x06000100,
236 0xf088, 0xffffffff, 0x00000100,
237 0xf086, 0xffffffff, 0x06000100,
238 0xf081, 0xffffffff, 0x00000100,
239 0xf0b8, 0xffffffff, 0x00000100,
240 0xf089, 0xffffffff, 0x00000100,
241 0xf080, 0xffffffff, 0x00000100,
242 0xf08c, 0xffffffff, 0x00000100,
243 0xf08d, 0xffffffff, 0x00000100,
244 0xf094, 0xffffffff, 0x00000100,
245 0xf095, 0xffffffff, 0x00000100,
246 0xf096, 0xffffffff, 0x00000100,
247 0xf097, 0xffffffff, 0x00000100,
248 0xf098, 0xffffffff, 0x00000100,
249 0xf09f, 0xffffffff, 0x00000100,
250 0xf09e, 0xffffffff, 0x00000100,
251 0xf084, 0xffffffff, 0x06000100,
252 0xf0a4, 0xffffffff, 0x00000100,
253 0xf09d, 0xffffffff, 0x00000100,
254 0xf0ad, 0xffffffff, 0x00000100,
255 0xf0ac, 0xffffffff, 0x00000100,
256 0xf09c, 0xffffffff, 0x00000100,
257 0xc200, 0xffffffff, 0xe0000000,
258 0xf008, 0xffffffff, 0x00010000,
259 0xf009, 0xffffffff, 0x00030002,
260 0xf00a, 0xffffffff, 0x00040007,
261 0xf00b, 0xffffffff, 0x00060005,
262 0xf00c, 0xffffffff, 0x00090008,
263 0xf00d, 0xffffffff, 0x00010000,
264 0xf00e, 0xffffffff, 0x00030002,
265 0xf00f, 0xffffffff, 0x00040007,
266 0xf010, 0xffffffff, 0x00060005,
267 0xf011, 0xffffffff, 0x00090008,
268 0xf012, 0xffffffff, 0x00010000,
269 0xf013, 0xffffffff, 0x00030002,
270 0xf014, 0xffffffff, 0x00040007,
271 0xf015, 0xffffffff, 0x00060005,
272 0xf016, 0xffffffff, 0x00090008,
273 0xf017, 0xffffffff, 0x00010000,
274 0xf018, 0xffffffff, 0x00030002,
275 0xf019, 0xffffffff, 0x00040007,
276 0xf01a, 0xffffffff, 0x00060005,
277 0xf01b, 0xffffffff, 0x00090008,
278 0xf01c, 0xffffffff, 0x00010000,
279 0xf01d, 0xffffffff, 0x00030002,
280 0xf01e, 0xffffffff, 0x00040007,
281 0xf01f, 0xffffffff, 0x00060005,
282 0xf020, 0xffffffff, 0x00090008,
283 0xf021, 0xffffffff, 0x00010000,
284 0xf022, 0xffffffff, 0x00030002,
285 0xf023, 0xffffffff, 0x00040007,
286 0xf024, 0xffffffff, 0x00060005,
287 0xf025, 0xffffffff, 0x00090008,
288 0xf026, 0xffffffff, 0x00010000,
289 0xf027, 0xffffffff, 0x00030002,
290 0xf028, 0xffffffff, 0x00040007,
291 0xf029, 0xffffffff, 0x00060005,
292 0xf02a, 0xffffffff, 0x00090008,
293 0xf000, 0xffffffff, 0x96e00200,
294 0x21c2, 0xffffffff, 0x00900100,
295 0x3109, 0xffffffff, 0x0020003f,
296 0xe, 0xffffffff, 0x0140001c,
297 0xf, 0x000f0000, 0x000f0000,
298 0x88, 0xffffffff, 0xc060000c,
299 0x89, 0xc0000fff, 0x00000100,
300 0x3e4, 0xffffffff, 0x00000100,
301 0x3e6, 0x00000101, 0x00000000,
302 0x82a, 0xffffffff, 0x00000104,
303 0x1579, 0xff000fff, 0x00000100,
304 0xc33, 0xc0000fff, 0x00000104,
305 0x3079, 0x00000001, 0x00000001,
306 0x3403, 0xff000ff0, 0x00000100,
307 0x3603, 0xff000ff0, 0x00000100
308};
309
310static const u32 spectre_golden_spm_registers[] =
311{
312 0xc200, 0xe0ffffff, 0xe0000000
313};
314
315static const u32 spectre_golden_common_registers[] =
316{
317 0x31dc, 0xffffffff, 0x00000800,
318 0x31dd, 0xffffffff, 0x00000800,
319 0x31e6, 0xffffffff, 0x00007fbf,
320 0x31e7, 0xffffffff, 0x00007faf
321};
322
323static const u32 spectre_golden_registers[] =
324{
325 0xf000, 0xffff1fff, 0x96940200,
326 0xf003, 0xffff0001, 0xff000000,
327 0xf080, 0xfffc0fff, 0x00000100,
328 0x1bb6, 0x00010101, 0x00010000,
329 0x260d, 0xf00fffff, 0x00000400,
330 0x260e, 0xfffffffc, 0x00020200,
331 0x16ec, 0x000000f0, 0x00000070,
332 0x16f0, 0xf0311fff, 0x80300000,
333 0x263e, 0x73773777, 0x12010001,
334 0x26df, 0x00ff0000, 0x00fc0000,
335 0xbd2, 0x73773777, 0x12010001,
336 0x2285, 0xf000003f, 0x00000007,
337 0x22c9, 0xffffffff, 0x00ffffff,
338 0xa0d4, 0x3f3f3fff, 0x00000082,
339 0xa0d5, 0x0000003f, 0x00000000,
340 0xf9e, 0x00000001, 0x00000002,
341 0x244f, 0xffff03df, 0x00000004,
342 0x31da, 0x00000008, 0x00000008,
343 0x2300, 0x000008ff, 0x00000800,
344 0x2542, 0x00010000, 0x00010000,
345 0x2b03, 0xffffffff, 0x54763210,
346 0x853e, 0x01ff01ff, 0x00000002,
347 0x8526, 0x007ff800, 0x00200000,
348 0x8057, 0xffffffff, 0x00000f40,
349 0xc24d, 0xffffffff, 0x00000001
350};
351
352static const u32 spectre_mgcg_cgcg_init[] =
353{
354 0x3108, 0xffffffff, 0xfffffffc,
355 0xc200, 0xffffffff, 0xe0000000,
356 0xf0a8, 0xffffffff, 0x00000100,
357 0xf082, 0xffffffff, 0x00000100,
358 0xf0b0, 0xffffffff, 0x00000100,
359 0xf0b2, 0xffffffff, 0x00000100,
360 0xf0b1, 0xffffffff, 0x00000100,
361 0x1579, 0xffffffff, 0x00600100,
362 0xf0a0, 0xffffffff, 0x00000100,
363 0xf085, 0xffffffff, 0x06000100,
364 0xf088, 0xffffffff, 0x00000100,
365 0xf086, 0xffffffff, 0x06000100,
366 0xf081, 0xffffffff, 0x00000100,
367 0xf0b8, 0xffffffff, 0x00000100,
368 0xf089, 0xffffffff, 0x00000100,
369 0xf080, 0xffffffff, 0x00000100,
370 0xf08c, 0xffffffff, 0x00000100,
371 0xf08d, 0xffffffff, 0x00000100,
372 0xf094, 0xffffffff, 0x00000100,
373 0xf095, 0xffffffff, 0x00000100,
374 0xf096, 0xffffffff, 0x00000100,
375 0xf097, 0xffffffff, 0x00000100,
376 0xf098, 0xffffffff, 0x00000100,
377 0xf09f, 0xffffffff, 0x00000100,
378 0xf09e, 0xffffffff, 0x00000100,
379 0xf084, 0xffffffff, 0x06000100,
380 0xf0a4, 0xffffffff, 0x00000100,
381 0xf09d, 0xffffffff, 0x00000100,
382 0xf0ad, 0xffffffff, 0x00000100,
383 0xf0ac, 0xffffffff, 0x00000100,
384 0xf09c, 0xffffffff, 0x00000100,
385 0xc200, 0xffffffff, 0xe0000000,
386 0xf008, 0xffffffff, 0x00010000,
387 0xf009, 0xffffffff, 0x00030002,
388 0xf00a, 0xffffffff, 0x00040007,
389 0xf00b, 0xffffffff, 0x00060005,
390 0xf00c, 0xffffffff, 0x00090008,
391 0xf00d, 0xffffffff, 0x00010000,
392 0xf00e, 0xffffffff, 0x00030002,
393 0xf00f, 0xffffffff, 0x00040007,
394 0xf010, 0xffffffff, 0x00060005,
395 0xf011, 0xffffffff, 0x00090008,
396 0xf012, 0xffffffff, 0x00010000,
397 0xf013, 0xffffffff, 0x00030002,
398 0xf014, 0xffffffff, 0x00040007,
399 0xf015, 0xffffffff, 0x00060005,
400 0xf016, 0xffffffff, 0x00090008,
401 0xf017, 0xffffffff, 0x00010000,
402 0xf018, 0xffffffff, 0x00030002,
403 0xf019, 0xffffffff, 0x00040007,
404 0xf01a, 0xffffffff, 0x00060005,
405 0xf01b, 0xffffffff, 0x00090008,
406 0xf01c, 0xffffffff, 0x00010000,
407 0xf01d, 0xffffffff, 0x00030002,
408 0xf01e, 0xffffffff, 0x00040007,
409 0xf01f, 0xffffffff, 0x00060005,
410 0xf020, 0xffffffff, 0x00090008,
411 0xf021, 0xffffffff, 0x00010000,
412 0xf022, 0xffffffff, 0x00030002,
413 0xf023, 0xffffffff, 0x00040007,
414 0xf024, 0xffffffff, 0x00060005,
415 0xf025, 0xffffffff, 0x00090008,
416 0xf026, 0xffffffff, 0x00010000,
417 0xf027, 0xffffffff, 0x00030002,
418 0xf028, 0xffffffff, 0x00040007,
419 0xf029, 0xffffffff, 0x00060005,
420 0xf02a, 0xffffffff, 0x00090008,
421 0xf02b, 0xffffffff, 0x00010000,
422 0xf02c, 0xffffffff, 0x00030002,
423 0xf02d, 0xffffffff, 0x00040007,
424 0xf02e, 0xffffffff, 0x00060005,
425 0xf02f, 0xffffffff, 0x00090008,
426 0xf000, 0xffffffff, 0x96e00200,
427 0x21c2, 0xffffffff, 0x00900100,
428 0x3109, 0xffffffff, 0x0020003f,
429 0xe, 0xffffffff, 0x0140001c,
430 0xf, 0x000f0000, 0x000f0000,
431 0x88, 0xffffffff, 0xc060000c,
432 0x89, 0xc0000fff, 0x00000100,
433 0x3e4, 0xffffffff, 0x00000100,
434 0x3e6, 0x00000101, 0x00000000,
435 0x82a, 0xffffffff, 0x00000104,
436 0x1579, 0xff000fff, 0x00000100,
437 0xc33, 0xc0000fff, 0x00000104,
438 0x3079, 0x00000001, 0x00000001,
439 0x3403, 0xff000ff0, 0x00000100,
440 0x3603, 0xff000ff0, 0x00000100
441};
442
443static const u32 kalindi_golden_spm_registers[] =
444{
445 0xc200, 0xe0ffffff, 0xe0000000
446};
447
448static const u32 kalindi_golden_common_registers[] =
449{
450 0x31dc, 0xffffffff, 0x00000800,
451 0x31dd, 0xffffffff, 0x00000800,
452 0x31e6, 0xffffffff, 0x00007fbf,
453 0x31e7, 0xffffffff, 0x00007faf
454};
455
456static const u32 kalindi_golden_registers[] =
457{
458 0xf000, 0xffffdfff, 0x6e944040,
459 0x1579, 0xff607fff, 0xfc000100,
460 0xf088, 0xff000fff, 0x00000100,
461 0xf089, 0xff000fff, 0x00000100,
462 0xf080, 0xfffc0fff, 0x00000100,
463 0x1bb6, 0x00010101, 0x00010000,
464 0x260c, 0xffffffff, 0x00000000,
465 0x260d, 0xf00fffff, 0x00000400,
466 0x16ec, 0x000000f0, 0x00000070,
467 0x16f0, 0xf0311fff, 0x80300000,
468 0x263e, 0x73773777, 0x12010001,
469 0x263f, 0xffffffff, 0x00000010,
470 0x26df, 0x00ff0000, 0x00fc0000,
471 0x200c, 0x00001f0f, 0x0000100a,
472 0xbd2, 0x73773777, 0x12010001,
473 0x902, 0x000fffff, 0x000c007f,
474 0x2285, 0xf000003f, 0x00000007,
475 0x22c9, 0x3fff3fff, 0x00ffcfff,
476 0xc281, 0x0000ff0f, 0x00000000,
477 0xa293, 0x07ffffff, 0x06000000,
478 0x136, 0x00000fff, 0x00000100,
479 0xf9e, 0x00000001, 0x00000002,
480 0x31da, 0x00000008, 0x00000008,
481 0x2300, 0x000000ff, 0x00000003,
482 0x853e, 0x01ff01ff, 0x00000002,
483 0x8526, 0x007ff800, 0x00200000,
484 0x8057, 0xffffffff, 0x00000f40,
485 0x2231, 0x001f3ae3, 0x00000082,
486 0x2235, 0x0000001f, 0x00000010,
487 0xc24d, 0xffffffff, 0x00000000
488};
489
490static const u32 kalindi_mgcg_cgcg_init[] =
491{
492 0x3108, 0xffffffff, 0xfffffffc,
493 0xc200, 0xffffffff, 0xe0000000,
494 0xf0a8, 0xffffffff, 0x00000100,
495 0xf082, 0xffffffff, 0x00000100,
496 0xf0b0, 0xffffffff, 0x00000100,
497 0xf0b2, 0xffffffff, 0x00000100,
498 0xf0b1, 0xffffffff, 0x00000100,
499 0x1579, 0xffffffff, 0x00600100,
500 0xf0a0, 0xffffffff, 0x00000100,
501 0xf085, 0xffffffff, 0x06000100,
502 0xf088, 0xffffffff, 0x00000100,
503 0xf086, 0xffffffff, 0x06000100,
504 0xf081, 0xffffffff, 0x00000100,
505 0xf0b8, 0xffffffff, 0x00000100,
506 0xf089, 0xffffffff, 0x00000100,
507 0xf080, 0xffffffff, 0x00000100,
508 0xf08c, 0xffffffff, 0x00000100,
509 0xf08d, 0xffffffff, 0x00000100,
510 0xf094, 0xffffffff, 0x00000100,
511 0xf095, 0xffffffff, 0x00000100,
512 0xf096, 0xffffffff, 0x00000100,
513 0xf097, 0xffffffff, 0x00000100,
514 0xf098, 0xffffffff, 0x00000100,
515 0xf09f, 0xffffffff, 0x00000100,
516 0xf09e, 0xffffffff, 0x00000100,
517 0xf084, 0xffffffff, 0x06000100,
518 0xf0a4, 0xffffffff, 0x00000100,
519 0xf09d, 0xffffffff, 0x00000100,
520 0xf0ad, 0xffffffff, 0x00000100,
521 0xf0ac, 0xffffffff, 0x00000100,
522 0xf09c, 0xffffffff, 0x00000100,
523 0xc200, 0xffffffff, 0xe0000000,
524 0xf008, 0xffffffff, 0x00010000,
525 0xf009, 0xffffffff, 0x00030002,
526 0xf00a, 0xffffffff, 0x00040007,
527 0xf00b, 0xffffffff, 0x00060005,
528 0xf00c, 0xffffffff, 0x00090008,
529 0xf00d, 0xffffffff, 0x00010000,
530 0xf00e, 0xffffffff, 0x00030002,
531 0xf00f, 0xffffffff, 0x00040007,
532 0xf010, 0xffffffff, 0x00060005,
533 0xf011, 0xffffffff, 0x00090008,
534 0xf000, 0xffffffff, 0x96e00200,
535 0x21c2, 0xffffffff, 0x00900100,
536 0x3109, 0xffffffff, 0x0020003f,
537 0xe, 0xffffffff, 0x0140001c,
538 0xf, 0x000f0000, 0x000f0000,
539 0x88, 0xffffffff, 0xc060000c,
540 0x89, 0xc0000fff, 0x00000100,
541 0x82a, 0xffffffff, 0x00000104,
542 0x1579, 0xff000fff, 0x00000100,
543 0xc33, 0xc0000fff, 0x00000104,
544 0x3079, 0x00000001, 0x00000001,
545 0x3403, 0xff000ff0, 0x00000100,
546 0x3603, 0xff000ff0, 0x00000100
547};
548
549static const u32 hawaii_golden_spm_registers[] =
550{
551 0xc200, 0xe0ffffff, 0xe0000000
552};
553
554static const u32 hawaii_golden_common_registers[] =
555{
556 0xc200, 0xffffffff, 0xe0000000,
557 0xa0d4, 0xffffffff, 0x3a00161a,
558 0xa0d5, 0xffffffff, 0x0000002e,
559 0x2684, 0xffffffff, 0x00018208,
560 0x263e, 0xffffffff, 0x12011003
561};
562
563static const u32 hawaii_golden_registers[] =
564{
565 0xcd5, 0x00000333, 0x00000333,
566 0x2684, 0x00010000, 0x00058208,
567 0x260c, 0xffffffff, 0x00000000,
568 0x260d, 0xf00fffff, 0x00000400,
569 0x260e, 0x0002021c, 0x00020200,
570 0x31e, 0x00000080, 0x00000000,
571 0x16ec, 0x000000f0, 0x00000070,
572 0x16f0, 0xf0311fff, 0x80300000,
573 0xd43, 0x00810000, 0x408af000,
574 0x1c0c, 0x31000111, 0x00000011,
575 0xbd2, 0x73773777, 0x12010001,
576 0x848, 0x0000007f, 0x0000001b,
577 0x877, 0x00007fb6, 0x00002191,
578 0xd8a, 0x0000003f, 0x0000000a,
579 0xd8b, 0x0000003f, 0x0000000a,
580 0xab9, 0x00073ffe, 0x000022a2,
581 0x903, 0x000007ff, 0x00000000,
582 0x22fc, 0x00002001, 0x00000001,
583 0x22c9, 0xffffffff, 0x00ffffff,
584 0xc281, 0x0000ff0f, 0x00000000,
585 0xa293, 0x07ffffff, 0x06000000,
586 0xf9e, 0x00000001, 0x00000002,
587 0x31da, 0x00000008, 0x00000008,
588 0x31dc, 0x00000f00, 0x00000800,
589 0x31dd, 0x00000f00, 0x00000800,
590 0x31e6, 0x00ffffff, 0x00ff7fbf,
591 0x31e7, 0x00ffffff, 0x00ff7faf,
592 0x2300, 0x000000ff, 0x00000800,
593 0x390, 0x00001fff, 0x00001fff,
594 0x2418, 0x0000007f, 0x00000020,
595 0x2542, 0x00010000, 0x00010000,
596 0x2b80, 0x00100000, 0x000ff07c,
597 0x2b05, 0x000003ff, 0x0000000f,
598 0x2b04, 0xffffffff, 0x7564fdec,
599 0x2b03, 0xffffffff, 0x3120b9a8,
600 0x2b02, 0x20000000, 0x0f9c0000
601};
602
603static const u32 hawaii_mgcg_cgcg_init[] =
604{
605 0x3108, 0xffffffff, 0xfffffffd,
606 0xc200, 0xffffffff, 0xe0000000,
607 0xf0a8, 0xffffffff, 0x00000100,
608 0xf082, 0xffffffff, 0x00000100,
609 0xf0b0, 0xffffffff, 0x00000100,
610 0xf0b2, 0xffffffff, 0x00000100,
611 0xf0b1, 0xffffffff, 0x00000100,
612 0x1579, 0xffffffff, 0x00200100,
613 0xf0a0, 0xffffffff, 0x00000100,
614 0xf085, 0xffffffff, 0x06000100,
615 0xf088, 0xffffffff, 0x00000100,
616 0xf086, 0xffffffff, 0x06000100,
617 0xf081, 0xffffffff, 0x00000100,
618 0xf0b8, 0xffffffff, 0x00000100,
619 0xf089, 0xffffffff, 0x00000100,
620 0xf080, 0xffffffff, 0x00000100,
621 0xf08c, 0xffffffff, 0x00000100,
622 0xf08d, 0xffffffff, 0x00000100,
623 0xf094, 0xffffffff, 0x00000100,
624 0xf095, 0xffffffff, 0x00000100,
625 0xf096, 0xffffffff, 0x00000100,
626 0xf097, 0xffffffff, 0x00000100,
627 0xf098, 0xffffffff, 0x00000100,
628 0xf09f, 0xffffffff, 0x00000100,
629 0xf09e, 0xffffffff, 0x00000100,
630 0xf084, 0xffffffff, 0x06000100,
631 0xf0a4, 0xffffffff, 0x00000100,
632 0xf09d, 0xffffffff, 0x00000100,
633 0xf0ad, 0xffffffff, 0x00000100,
634 0xf0ac, 0xffffffff, 0x00000100,
635 0xf09c, 0xffffffff, 0x00000100,
636 0xc200, 0xffffffff, 0xe0000000,
637 0xf008, 0xffffffff, 0x00010000,
638 0xf009, 0xffffffff, 0x00030002,
639 0xf00a, 0xffffffff, 0x00040007,
640 0xf00b, 0xffffffff, 0x00060005,
641 0xf00c, 0xffffffff, 0x00090008,
642 0xf00d, 0xffffffff, 0x00010000,
643 0xf00e, 0xffffffff, 0x00030002,
644 0xf00f, 0xffffffff, 0x00040007,
645 0xf010, 0xffffffff, 0x00060005,
646 0xf011, 0xffffffff, 0x00090008,
647 0xf012, 0xffffffff, 0x00010000,
648 0xf013, 0xffffffff, 0x00030002,
649 0xf014, 0xffffffff, 0x00040007,
650 0xf015, 0xffffffff, 0x00060005,
651 0xf016, 0xffffffff, 0x00090008,
652 0xf017, 0xffffffff, 0x00010000,
653 0xf018, 0xffffffff, 0x00030002,
654 0xf019, 0xffffffff, 0x00040007,
655 0xf01a, 0xffffffff, 0x00060005,
656 0xf01b, 0xffffffff, 0x00090008,
657 0xf01c, 0xffffffff, 0x00010000,
658 0xf01d, 0xffffffff, 0x00030002,
659 0xf01e, 0xffffffff, 0x00040007,
660 0xf01f, 0xffffffff, 0x00060005,
661 0xf020, 0xffffffff, 0x00090008,
662 0xf021, 0xffffffff, 0x00010000,
663 0xf022, 0xffffffff, 0x00030002,
664 0xf023, 0xffffffff, 0x00040007,
665 0xf024, 0xffffffff, 0x00060005,
666 0xf025, 0xffffffff, 0x00090008,
667 0xf026, 0xffffffff, 0x00010000,
668 0xf027, 0xffffffff, 0x00030002,
669 0xf028, 0xffffffff, 0x00040007,
670 0xf029, 0xffffffff, 0x00060005,
671 0xf02a, 0xffffffff, 0x00090008,
672 0xf02b, 0xffffffff, 0x00010000,
673 0xf02c, 0xffffffff, 0x00030002,
674 0xf02d, 0xffffffff, 0x00040007,
675 0xf02e, 0xffffffff, 0x00060005,
676 0xf02f, 0xffffffff, 0x00090008,
677 0xf030, 0xffffffff, 0x00010000,
678 0xf031, 0xffffffff, 0x00030002,
679 0xf032, 0xffffffff, 0x00040007,
680 0xf033, 0xffffffff, 0x00060005,
681 0xf034, 0xffffffff, 0x00090008,
682 0xf035, 0xffffffff, 0x00010000,
683 0xf036, 0xffffffff, 0x00030002,
684 0xf037, 0xffffffff, 0x00040007,
685 0xf038, 0xffffffff, 0x00060005,
686 0xf039, 0xffffffff, 0x00090008,
687 0xf03a, 0xffffffff, 0x00010000,
688 0xf03b, 0xffffffff, 0x00030002,
689 0xf03c, 0xffffffff, 0x00040007,
690 0xf03d, 0xffffffff, 0x00060005,
691 0xf03e, 0xffffffff, 0x00090008,
692 0x30c6, 0xffffffff, 0x00020200,
693 0xcd4, 0xffffffff, 0x00000200,
694 0x570, 0xffffffff, 0x00000400,
695 0x157a, 0xffffffff, 0x00000000,
696 0xbd4, 0xffffffff, 0x00000902,
697 0xf000, 0xffffffff, 0x96940200,
698 0x21c2, 0xffffffff, 0x00900100,
699 0x3109, 0xffffffff, 0x0020003f,
700 0xe, 0xffffffff, 0x0140001c,
701 0xf, 0x000f0000, 0x000f0000,
702 0x88, 0xffffffff, 0xc060000c,
703 0x89, 0xc0000fff, 0x00000100,
704 0x3e4, 0xffffffff, 0x00000100,
705 0x3e6, 0x00000101, 0x00000000,
706 0x82a, 0xffffffff, 0x00000104,
707 0x1579, 0xff000fff, 0x00000100,
708 0xc33, 0xc0000fff, 0x00000104,
709 0x3079, 0x00000001, 0x00000001,
710 0x3403, 0xff000ff0, 0x00000100,
711 0x3603, 0xff000ff0, 0x00000100
712};
713
714static const u32 godavari_golden_registers[] =
715{
716 0x1579, 0xff607fff, 0xfc000100,
717 0x1bb6, 0x00010101, 0x00010000,
718 0x260c, 0xffffffff, 0x00000000,
719 0x260c0, 0xf00fffff, 0x00000400,
720 0x184c, 0xffffffff, 0x00010000,
721 0x16ec, 0x000000f0, 0x00000070,
722 0x16f0, 0xf0311fff, 0x80300000,
723 0x263e, 0x73773777, 0x12010001,
724 0x263f, 0xffffffff, 0x00000010,
725 0x200c, 0x00001f0f, 0x0000100a,
726 0xbd2, 0x73773777, 0x12010001,
727 0x902, 0x000fffff, 0x000c007f,
728 0x2285, 0xf000003f, 0x00000007,
729 0x22c9, 0xffffffff, 0x00ff0fff,
730 0xc281, 0x0000ff0f, 0x00000000,
731 0xa293, 0x07ffffff, 0x06000000,
732 0x136, 0x00000fff, 0x00000100,
733 0x3405, 0x00010000, 0x00810001,
734 0x3605, 0x00010000, 0x00810001,
735 0xf9e, 0x00000001, 0x00000002,
736 0x31da, 0x00000008, 0x00000008,
737 0x31dc, 0x00000f00, 0x00000800,
738 0x31dd, 0x00000f00, 0x00000800,
739 0x31e6, 0x00ffffff, 0x00ff7fbf,
740 0x31e7, 0x00ffffff, 0x00ff7faf,
741 0x2300, 0x000000ff, 0x00000001,
742 0x853e, 0x01ff01ff, 0x00000002,
743 0x8526, 0x007ff800, 0x00200000,
744 0x8057, 0xffffffff, 0x00000f40,
745 0x2231, 0x001f3ae3, 0x00000082,
746 0x2235, 0x0000001f, 0x00000010,
747 0xc24d, 0xffffffff, 0x00000000
748};
749
750static void cik_init_golden_registers(struct amdgpu_device *adev)
751{
752
753 mutex_lock(&adev->grbm_idx_mutex);
754
755 switch (adev->asic_type) {
756 case CHIP_BONAIRE:
757 amdgpu_program_register_sequence(adev,
758 bonaire_mgcg_cgcg_init,
759 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
760 amdgpu_program_register_sequence(adev,
761 bonaire_golden_registers,
762 (const u32)ARRAY_SIZE(bonaire_golden_registers));
763 amdgpu_program_register_sequence(adev,
764 bonaire_golden_common_registers,
765 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
766 amdgpu_program_register_sequence(adev,
767 bonaire_golden_spm_registers,
768 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
769 break;
770 case CHIP_KABINI:
771 amdgpu_program_register_sequence(adev,
772 kalindi_mgcg_cgcg_init,
773 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
774 amdgpu_program_register_sequence(adev,
775 kalindi_golden_registers,
776 (const u32)ARRAY_SIZE(kalindi_golden_registers));
777 amdgpu_program_register_sequence(adev,
778 kalindi_golden_common_registers,
779 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
780 amdgpu_program_register_sequence(adev,
781 kalindi_golden_spm_registers,
782 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
783 break;
784 case CHIP_MULLINS:
785 amdgpu_program_register_sequence(adev,
786 kalindi_mgcg_cgcg_init,
787 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
788 amdgpu_program_register_sequence(adev,
789 godavari_golden_registers,
790 (const u32)ARRAY_SIZE(godavari_golden_registers));
791 amdgpu_program_register_sequence(adev,
792 kalindi_golden_common_registers,
793 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
794 amdgpu_program_register_sequence(adev,
795 kalindi_golden_spm_registers,
796 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
797 break;
798 case CHIP_KAVERI:
799 amdgpu_program_register_sequence(adev,
800 spectre_mgcg_cgcg_init,
801 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
802 amdgpu_program_register_sequence(adev,
803 spectre_golden_registers,
804 (const u32)ARRAY_SIZE(spectre_golden_registers));
805 amdgpu_program_register_sequence(adev,
806 spectre_golden_common_registers,
807 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
808 amdgpu_program_register_sequence(adev,
809 spectre_golden_spm_registers,
810 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
811 break;
812 case CHIP_HAWAII:
813 amdgpu_program_register_sequence(adev,
814 hawaii_mgcg_cgcg_init,
815 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
816 amdgpu_program_register_sequence(adev,
817 hawaii_golden_registers,
818 (const u32)ARRAY_SIZE(hawaii_golden_registers));
819 amdgpu_program_register_sequence(adev,
820 hawaii_golden_common_registers,
821 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
822 amdgpu_program_register_sequence(adev,
823 hawaii_golden_spm_registers,
824 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
825 break;
826 default:
827 break;
828 }
829 mutex_unlock(&adev->grbm_idx_mutex);
830}
831
832
833
834
835
836
837
838
839
840static u32 cik_get_xclk(struct amdgpu_device *adev)
841{
842 u32 reference_clock = adev->clock.spll.reference_freq;
843
844 if (adev->flags & AMD_IS_APU) {
845 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
846 return reference_clock / 2;
847 } else {
848 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
849 return reference_clock / 4;
850 }
851 return reference_clock;
852}
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867void cik_srbm_select(struct amdgpu_device *adev,
868 u32 me, u32 pipe, u32 queue, u32 vmid)
869{
870 u32 srbm_gfx_cntl =
871 (((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)|
872 ((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)|
873 ((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)|
874 ((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK));
875 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
876}
877
878static void cik_vga_set_state(struct amdgpu_device *adev, bool state)
879{
880 uint32_t tmp;
881
882 tmp = RREG32(mmCONFIG_CNTL);
883 if (!state)
884 tmp |= CONFIG_CNTL__VGA_DIS_MASK;
885 else
886 tmp &= ~CONFIG_CNTL__VGA_DIS_MASK;
887 WREG32(mmCONFIG_CNTL, tmp);
888}
889
890static bool cik_read_disabled_bios(struct amdgpu_device *adev)
891{
892 u32 bus_cntl;
893 u32 d1vga_control = 0;
894 u32 d2vga_control = 0;
895 u32 vga_render_control = 0;
896 u32 rom_cntl;
897 bool r;
898
899 bus_cntl = RREG32(mmBUS_CNTL);
900 if (adev->mode_info.num_crtc) {
901 d1vga_control = RREG32(mmD1VGA_CONTROL);
902 d2vga_control = RREG32(mmD2VGA_CONTROL);
903 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
904 }
905 rom_cntl = RREG32_SMC(ixROM_CNTL);
906
907
908 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
909 if (adev->mode_info.num_crtc) {
910
911 WREG32(mmD1VGA_CONTROL,
912 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
913 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
914 WREG32(mmD2VGA_CONTROL,
915 (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
916 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
917 WREG32(mmVGA_RENDER_CONTROL,
918 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
919 }
920 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
921
922 r = amdgpu_read_bios(adev);
923
924
925 WREG32(mmBUS_CNTL, bus_cntl);
926 if (adev->mode_info.num_crtc) {
927 WREG32(mmD1VGA_CONTROL, d1vga_control);
928 WREG32(mmD2VGA_CONTROL, d2vga_control);
929 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
930 }
931 WREG32_SMC(ixROM_CNTL, rom_cntl);
932 return r;
933}
934
935static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
936 u8 *bios, u32 length_bytes)
937{
938 u32 *dw_ptr;
939 unsigned long flags;
940 u32 i, length_dw;
941
942 if (bios == NULL)
943 return false;
944 if (length_bytes == 0)
945 return false;
946
947 if (adev->flags & AMD_IS_APU)
948 return false;
949
950 dw_ptr = (u32 *)bios;
951 length_dw = ALIGN(length_bytes, 4) / 4;
952
953 spin_lock_irqsave(&adev->smc_idx_lock, flags);
954
955 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
956 WREG32(mmSMC_IND_DATA_0, 0);
957
958 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
959 for (i = 0; i < length_dw; i++)
960 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
961 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
962
963 return true;
964}
965
966static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
967 {mmGRBM_STATUS},
968 {mmGB_ADDR_CONFIG},
969 {mmMC_ARB_RAMCFG},
970 {mmGB_TILE_MODE0},
971 {mmGB_TILE_MODE1},
972 {mmGB_TILE_MODE2},
973 {mmGB_TILE_MODE3},
974 {mmGB_TILE_MODE4},
975 {mmGB_TILE_MODE5},
976 {mmGB_TILE_MODE6},
977 {mmGB_TILE_MODE7},
978 {mmGB_TILE_MODE8},
979 {mmGB_TILE_MODE9},
980 {mmGB_TILE_MODE10},
981 {mmGB_TILE_MODE11},
982 {mmGB_TILE_MODE12},
983 {mmGB_TILE_MODE13},
984 {mmGB_TILE_MODE14},
985 {mmGB_TILE_MODE15},
986 {mmGB_TILE_MODE16},
987 {mmGB_TILE_MODE17},
988 {mmGB_TILE_MODE18},
989 {mmGB_TILE_MODE19},
990 {mmGB_TILE_MODE20},
991 {mmGB_TILE_MODE21},
992 {mmGB_TILE_MODE22},
993 {mmGB_TILE_MODE23},
994 {mmGB_TILE_MODE24},
995 {mmGB_TILE_MODE25},
996 {mmGB_TILE_MODE26},
997 {mmGB_TILE_MODE27},
998 {mmGB_TILE_MODE28},
999 {mmGB_TILE_MODE29},
1000 {mmGB_TILE_MODE30},
1001 {mmGB_TILE_MODE31},
1002 {mmGB_MACROTILE_MODE0},
1003 {mmGB_MACROTILE_MODE1},
1004 {mmGB_MACROTILE_MODE2},
1005 {mmGB_MACROTILE_MODE3},
1006 {mmGB_MACROTILE_MODE4},
1007 {mmGB_MACROTILE_MODE5},
1008 {mmGB_MACROTILE_MODE6},
1009 {mmGB_MACROTILE_MODE7},
1010 {mmGB_MACROTILE_MODE8},
1011 {mmGB_MACROTILE_MODE9},
1012 {mmGB_MACROTILE_MODE10},
1013 {mmGB_MACROTILE_MODE11},
1014 {mmGB_MACROTILE_MODE12},
1015 {mmGB_MACROTILE_MODE13},
1016 {mmGB_MACROTILE_MODE14},
1017 {mmGB_MACROTILE_MODE15},
1018 {mmCC_RB_BACKEND_DISABLE, true},
1019 {mmGC_USER_RB_BACKEND_DISABLE, true},
1020 {mmGB_BACKEND_MAP, false},
1021 {mmPA_SC_RASTER_CONFIG, true},
1022 {mmPA_SC_RASTER_CONFIG_1, true},
1023};
1024
1025static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
1026 u32 se_num, u32 sh_num,
1027 u32 reg_offset)
1028{
1029 uint32_t val;
1030
1031 mutex_lock(&adev->grbm_idx_mutex);
1032 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1033 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1034
1035 val = RREG32(reg_offset);
1036
1037 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1038 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1039 mutex_unlock(&adev->grbm_idx_mutex);
1040 return val;
1041}
1042
1043static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
1044 u32 sh_num, u32 reg_offset, u32 *value)
1045{
1046 uint32_t i;
1047
1048 *value = 0;
1049 for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {
1050 if (reg_offset != cik_allowed_read_registers[i].reg_offset)
1051 continue;
1052
1053 *value = cik_allowed_read_registers[i].grbm_indexed ?
1054 cik_read_indexed_register(adev, se_num,
1055 sh_num, reg_offset) :
1056 RREG32(reg_offset);
1057 return 0;
1058 }
1059 return -EINVAL;
1060}
1061
1062struct kv_reset_save_regs {
1063 u32 gmcon_reng_execute;
1064 u32 gmcon_misc;
1065 u32 gmcon_misc3;
1066};
1067
1068static void kv_save_regs_for_reset(struct amdgpu_device *adev,
1069 struct kv_reset_save_regs *save)
1070{
1071 save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);
1072 save->gmcon_misc = RREG32(mmGMCON_MISC);
1073 save->gmcon_misc3 = RREG32(mmGMCON_MISC3);
1074
1075 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute &
1076 ~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK);
1077 WREG32(mmGMCON_MISC, save->gmcon_misc &
1078 ~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK |
1079 GMCON_MISC__STCTRL_STUTTER_EN_MASK));
1080}
1081
1082static void kv_restore_regs_for_reset(struct amdgpu_device *adev,
1083 struct kv_reset_save_regs *save)
1084{
1085 int i;
1086
1087 WREG32(mmGMCON_PGFSM_WRITE, 0);
1088 WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff);
1089
1090 for (i = 0; i < 5; i++)
1091 WREG32(mmGMCON_PGFSM_WRITE, 0);
1092
1093 WREG32(mmGMCON_PGFSM_WRITE, 0);
1094 WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff);
1095
1096 for (i = 0; i < 5; i++)
1097 WREG32(mmGMCON_PGFSM_WRITE, 0);
1098
1099 WREG32(mmGMCON_PGFSM_WRITE, 0x210000);
1100 WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff);
1101
1102 for (i = 0; i < 5; i++)
1103 WREG32(mmGMCON_PGFSM_WRITE, 0);
1104
1105 WREG32(mmGMCON_PGFSM_WRITE, 0x21003);
1106 WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff);
1107
1108 for (i = 0; i < 5; i++)
1109 WREG32(mmGMCON_PGFSM_WRITE, 0);
1110
1111 WREG32(mmGMCON_PGFSM_WRITE, 0x2b00);
1112 WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff);
1113
1114 for (i = 0; i < 5; i++)
1115 WREG32(mmGMCON_PGFSM_WRITE, 0);
1116
1117 WREG32(mmGMCON_PGFSM_WRITE, 0);
1118 WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff);
1119
1120 for (i = 0; i < 5; i++)
1121 WREG32(mmGMCON_PGFSM_WRITE, 0);
1122
1123 WREG32(mmGMCON_PGFSM_WRITE, 0x420000);
1124 WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff);
1125
1126 for (i = 0; i < 5; i++)
1127 WREG32(mmGMCON_PGFSM_WRITE, 0);
1128
1129 WREG32(mmGMCON_PGFSM_WRITE, 0x120202);
1130 WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff);
1131
1132 for (i = 0; i < 5; i++)
1133 WREG32(mmGMCON_PGFSM_WRITE, 0);
1134
1135 WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36);
1136 WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff);
1137
1138 for (i = 0; i < 5; i++)
1139 WREG32(mmGMCON_PGFSM_WRITE, 0);
1140
1141 WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e);
1142 WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff);
1143
1144 for (i = 0; i < 5; i++)
1145 WREG32(mmGMCON_PGFSM_WRITE, 0);
1146
1147 WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332);
1148 WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff);
1149
1150 WREG32(mmGMCON_MISC3, save->gmcon_misc3);
1151 WREG32(mmGMCON_MISC, save->gmcon_misc);
1152 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);
1153}
1154
1155static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
1156{
1157 struct kv_reset_save_regs kv_save = { 0 };
1158 u32 i;
1159 int r = -EINVAL;
1160
1161 dev_info(adev->dev, "GPU pci config reset\n");
1162
1163 if (adev->flags & AMD_IS_APU)
1164 kv_save_regs_for_reset(adev, &kv_save);
1165
1166
1167 pci_clear_master(adev->pdev);
1168
1169 amdgpu_pci_config_reset(adev);
1170
1171 udelay(100);
1172
1173
1174 for (i = 0; i < adev->usec_timeout; i++) {
1175 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
1176
1177 pci_set_master(adev->pdev);
1178 adev->has_hw_reset = true;
1179 r = 0;
1180 break;
1181 }
1182 udelay(1);
1183 }
1184
1185
1186 if (adev->flags & AMD_IS_APU)
1187 kv_restore_regs_for_reset(adev, &kv_save);
1188
1189 return r;
1190}
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201static int cik_asic_reset(struct amdgpu_device *adev)
1202{
1203 int r;
1204
1205 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
1206
1207 r = cik_gpu_pci_config_reset(adev);
1208
1209 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
1210
1211 return r;
1212}
1213
1214static u32 cik_get_config_memsize(struct amdgpu_device *adev)
1215{
1216 return RREG32(mmCONFIG_MEMSIZE);
1217}
1218
1219static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1220 u32 cntl_reg, u32 status_reg)
1221{
1222 int r, i;
1223 struct atom_clock_dividers dividers;
1224 uint32_t tmp;
1225
1226 r = amdgpu_atombios_get_clock_dividers(adev,
1227 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1228 clock, false, ÷rs);
1229 if (r)
1230 return r;
1231
1232 tmp = RREG32_SMC(cntl_reg);
1233 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
1234 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
1235 tmp |= dividers.post_divider;
1236 WREG32_SMC(cntl_reg, tmp);
1237
1238 for (i = 0; i < 100; i++) {
1239 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1240 break;
1241 mdelay(10);
1242 }
1243 if (i == 100)
1244 return -ETIMEDOUT;
1245
1246 return 0;
1247}
1248
1249static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1250{
1251 int r = 0;
1252
1253 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1254 if (r)
1255 return r;
1256
1257 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1258 return r;
1259}
1260
1261static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1262{
1263 int r, i;
1264 struct atom_clock_dividers dividers;
1265 u32 tmp;
1266
1267 r = amdgpu_atombios_get_clock_dividers(adev,
1268 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1269 ecclk, false, ÷rs);
1270 if (r)
1271 return r;
1272
1273 for (i = 0; i < 100; i++) {
1274 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1275 break;
1276 mdelay(10);
1277 }
1278 if (i == 100)
1279 return -ETIMEDOUT;
1280
1281 tmp = RREG32_SMC(ixCG_ECLK_CNTL);
1282 tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
1283 CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
1284 tmp |= dividers.post_divider;
1285 WREG32_SMC(ixCG_ECLK_CNTL, tmp);
1286
1287 for (i = 0; i < 100; i++) {
1288 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1289 break;
1290 mdelay(10);
1291 }
1292 if (i == 100)
1293 return -ETIMEDOUT;
1294
1295 return 0;
1296}
1297
1298static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
1299{
1300 struct pci_dev *root = adev->pdev->bus->self;
1301 int bridge_pos, gpu_pos;
1302 u32 speed_cntl, current_data_rate;
1303 int i;
1304 u16 tmp16;
1305
1306 if (pci_is_root_bus(adev->pdev->bus))
1307 return;
1308
1309 if (amdgpu_pcie_gen2 == 0)
1310 return;
1311
1312 if (adev->flags & AMD_IS_APU)
1313 return;
1314
1315 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1316 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1317 return;
1318
1319 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1320 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >>
1321 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1322 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1323 if (current_data_rate == 2) {
1324 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1325 return;
1326 }
1327 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1328 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1329 if (current_data_rate == 1) {
1330 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1331 return;
1332 }
1333 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1334 }
1335
1336 bridge_pos = pci_pcie_cap(root);
1337 if (!bridge_pos)
1338 return;
1339
1340 gpu_pos = pci_pcie_cap(adev->pdev);
1341 if (!gpu_pos)
1342 return;
1343
1344 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1345
1346 if (current_data_rate != 2) {
1347 u16 bridge_cfg, gpu_cfg;
1348 u16 bridge_cfg2, gpu_cfg2;
1349 u32 max_lw, current_lw, tmp;
1350
1351 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1352 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1353
1354 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1355 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1356
1357 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1358 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1359
1360 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
1361 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
1362 PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT;
1363 current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK)
1364 >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT;
1365
1366 if (current_lw < max_lw) {
1367 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1368 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
1369 tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK |
1370 PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK);
1371 tmp |= (max_lw <<
1372 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT);
1373 tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK |
1374 PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK |
1375 PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK;
1376 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
1377 }
1378 }
1379
1380 for (i = 0; i < 10; i++) {
1381
1382 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1383 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1384 break;
1385
1386 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1387 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1388
1389 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1390 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1391
1392 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1393 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
1394 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1395
1396 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1397 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
1398 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1399
1400 mdelay(100);
1401
1402
1403 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1404 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1405 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1406 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1407
1408 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1409 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1410 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1411 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1412
1413
1414 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1415 tmp16 &= ~((1 << 4) | (7 << 9));
1416 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1417 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1418
1419 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1420 tmp16 &= ~((1 << 4) | (7 << 9));
1421 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1422 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1423
1424 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1425 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
1426 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1427 }
1428 }
1429 }
1430
1431
1432 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK |
1433 PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK;
1434 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
1435 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
1436
1437 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1438 tmp16 &= ~0xf;
1439 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1440 tmp16 |= 3;
1441 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1442 tmp16 |= 2;
1443 else
1444 tmp16 |= 1;
1445 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1446
1447 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1448 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
1449 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
1450
1451 for (i = 0; i < adev->usec_timeout; i++) {
1452 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1453 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0)
1454 break;
1455 udelay(1);
1456 }
1457}
1458
1459static void cik_program_aspm(struct amdgpu_device *adev)
1460{
1461 u32 data, orig;
1462 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1463 bool disable_clkreq = false;
1464
1465 if (amdgpu_aspm == 0)
1466 return;
1467
1468 if (pci_is_root_bus(adev->pdev->bus))
1469 return;
1470
1471
1472 if (adev->flags & AMD_IS_APU)
1473 return;
1474
1475 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1476 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
1477 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) |
1478 PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
1479 if (orig != data)
1480 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
1481
1482 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
1483 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
1484 if (orig != data)
1485 WREG32_PCIE(ixPCIE_LC_CNTL3, data);
1486
1487 orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
1488 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
1489 if (orig != data)
1490 WREG32_PCIE(ixPCIE_P_CNTL, data);
1491
1492 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1493 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK |
1494 PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
1495 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1496 if (!disable_l0s)
1497 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT);
1498
1499 if (!disable_l1) {
1500 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT);
1501 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1502 if (orig != data)
1503 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1504
1505 if (!disable_plloff_in_l1) {
1506 bool clk_req_support;
1507
1508 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0);
1509 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1510 PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
1511 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1512 (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
1513 if (orig != data)
1514 WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data);
1515
1516 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1);
1517 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1518 PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
1519 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1520 (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
1521 if (orig != data)
1522 WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data);
1523
1524 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0);
1525 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1526 PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
1527 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1528 (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
1529 if (orig != data)
1530 WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data);
1531
1532 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1);
1533 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1534 PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
1535 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1536 (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
1537 if (orig != data)
1538 WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data);
1539
1540 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1541 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
1542 data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);
1543 if (orig != data)
1544 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
1545
1546 if (!disable_clkreq) {
1547 struct pci_dev *root = adev->pdev->bus->self;
1548 u32 lnkcap;
1549
1550 clk_req_support = false;
1551 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1552 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1553 clk_req_support = true;
1554 } else {
1555 clk_req_support = false;
1556 }
1557
1558 if (clk_req_support) {
1559 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
1560 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
1561 PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
1562 if (orig != data)
1563 WREG32_PCIE(ixPCIE_LC_CNTL2, data);
1564
1565 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1566 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK |
1567 THM_CLK_CNTL__TMON_CLK_SEL_MASK);
1568 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
1569 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);
1570 if (orig != data)
1571 WREG32_SMC(ixTHM_CLK_CNTL, data);
1572
1573 orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
1574 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
1575 MISC_CLK_CTRL__ZCLK_SEL_MASK);
1576 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
1577 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT);
1578 if (orig != data)
1579 WREG32_SMC(ixMISC_CLK_CTRL, data);
1580
1581 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
1582 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;
1583 if (orig != data)
1584 WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1585
1586 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1587 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK;
1588 if (orig != data)
1589 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data);
1590
1591 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
1592 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
1593 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
1594 if (orig != data)
1595 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
1596 }
1597 }
1598 } else {
1599 if (orig != data)
1600 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1601 }
1602
1603 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
1604 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1605 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1606 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1607 if (orig != data)
1608 WREG32_PCIE(ixPCIE_CNTL2, data);
1609
1610 if (!disable_l0s) {
1611 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1612 if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) ==
1613 PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) {
1614 data = RREG32_PCIE(ixPCIE_LC_STATUS1);
1615 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) &&
1616 (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) {
1617 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1618 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1619 if (orig != data)
1620 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1621 }
1622 }
1623 }
1624}
1625
1626static uint32_t cik_get_rev_id(struct amdgpu_device *adev)
1627{
1628 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1629 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1630}
1631
1632static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
1633{
1634 if (is_virtual_machine())
1635 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
1636}
1637
1638static const struct amdgpu_asic_funcs cik_asic_funcs =
1639{
1640 .read_disabled_bios = &cik_read_disabled_bios,
1641 .read_bios_from_rom = &cik_read_bios_from_rom,
1642 .read_register = &cik_read_register,
1643 .reset = &cik_asic_reset,
1644 .set_vga_state = &cik_vga_set_state,
1645 .get_xclk = &cik_get_xclk,
1646 .set_uvd_clocks = &cik_set_uvd_clocks,
1647 .set_vce_clocks = &cik_set_vce_clocks,
1648 .get_config_memsize = &cik_get_config_memsize,
1649};
1650
1651static int cik_common_early_init(void *handle)
1652{
1653 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1654
1655 adev->smc_rreg = &cik_smc_rreg;
1656 adev->smc_wreg = &cik_smc_wreg;
1657 adev->pcie_rreg = &cik_pcie_rreg;
1658 adev->pcie_wreg = &cik_pcie_wreg;
1659 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;
1660 adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg;
1661 adev->didt_rreg = &cik_didt_rreg;
1662 adev->didt_wreg = &cik_didt_wreg;
1663
1664 adev->asic_funcs = &cik_asic_funcs;
1665
1666 adev->rev_id = cik_get_rev_id(adev);
1667 adev->external_rev_id = 0xFF;
1668 switch (adev->asic_type) {
1669 case CHIP_BONAIRE:
1670 adev->cg_flags =
1671 AMD_CG_SUPPORT_GFX_MGCG |
1672 AMD_CG_SUPPORT_GFX_MGLS |
1673
1674 AMD_CG_SUPPORT_GFX_CGLS |
1675 AMD_CG_SUPPORT_GFX_CGTS |
1676 AMD_CG_SUPPORT_GFX_CGTS_LS |
1677 AMD_CG_SUPPORT_GFX_CP_LS |
1678 AMD_CG_SUPPORT_MC_LS |
1679 AMD_CG_SUPPORT_MC_MGCG |
1680 AMD_CG_SUPPORT_SDMA_MGCG |
1681 AMD_CG_SUPPORT_SDMA_LS |
1682 AMD_CG_SUPPORT_BIF_LS |
1683 AMD_CG_SUPPORT_VCE_MGCG |
1684 AMD_CG_SUPPORT_UVD_MGCG |
1685 AMD_CG_SUPPORT_HDP_LS |
1686 AMD_CG_SUPPORT_HDP_MGCG;
1687 adev->pg_flags = 0;
1688 adev->external_rev_id = adev->rev_id + 0x14;
1689 break;
1690 case CHIP_HAWAII:
1691 adev->cg_flags =
1692 AMD_CG_SUPPORT_GFX_MGCG |
1693 AMD_CG_SUPPORT_GFX_MGLS |
1694
1695 AMD_CG_SUPPORT_GFX_CGLS |
1696 AMD_CG_SUPPORT_GFX_CGTS |
1697 AMD_CG_SUPPORT_GFX_CP_LS |
1698 AMD_CG_SUPPORT_MC_LS |
1699 AMD_CG_SUPPORT_MC_MGCG |
1700 AMD_CG_SUPPORT_SDMA_MGCG |
1701 AMD_CG_SUPPORT_SDMA_LS |
1702 AMD_CG_SUPPORT_BIF_LS |
1703 AMD_CG_SUPPORT_VCE_MGCG |
1704 AMD_CG_SUPPORT_UVD_MGCG |
1705 AMD_CG_SUPPORT_HDP_LS |
1706 AMD_CG_SUPPORT_HDP_MGCG;
1707 adev->pg_flags = 0;
1708 adev->external_rev_id = 0x28;
1709 break;
1710 case CHIP_KAVERI:
1711 adev->cg_flags =
1712 AMD_CG_SUPPORT_GFX_MGCG |
1713 AMD_CG_SUPPORT_GFX_MGLS |
1714
1715 AMD_CG_SUPPORT_GFX_CGLS |
1716 AMD_CG_SUPPORT_GFX_CGTS |
1717 AMD_CG_SUPPORT_GFX_CGTS_LS |
1718 AMD_CG_SUPPORT_GFX_CP_LS |
1719 AMD_CG_SUPPORT_SDMA_MGCG |
1720 AMD_CG_SUPPORT_SDMA_LS |
1721 AMD_CG_SUPPORT_BIF_LS |
1722 AMD_CG_SUPPORT_VCE_MGCG |
1723 AMD_CG_SUPPORT_UVD_MGCG |
1724 AMD_CG_SUPPORT_HDP_LS |
1725 AMD_CG_SUPPORT_HDP_MGCG;
1726 adev->pg_flags =
1727
1728
1729
1730 AMD_PG_SUPPORT_UVD |
1731 AMD_PG_SUPPORT_VCE |
1732
1733
1734
1735
1736
1737 0;
1738 if (adev->pdev->device == 0x1312 ||
1739 adev->pdev->device == 0x1316 ||
1740 adev->pdev->device == 0x1317)
1741 adev->external_rev_id = 0x41;
1742 else
1743 adev->external_rev_id = 0x1;
1744 break;
1745 case CHIP_KABINI:
1746 case CHIP_MULLINS:
1747 adev->cg_flags =
1748 AMD_CG_SUPPORT_GFX_MGCG |
1749 AMD_CG_SUPPORT_GFX_MGLS |
1750
1751 AMD_CG_SUPPORT_GFX_CGLS |
1752 AMD_CG_SUPPORT_GFX_CGTS |
1753 AMD_CG_SUPPORT_GFX_CGTS_LS |
1754 AMD_CG_SUPPORT_GFX_CP_LS |
1755 AMD_CG_SUPPORT_SDMA_MGCG |
1756 AMD_CG_SUPPORT_SDMA_LS |
1757 AMD_CG_SUPPORT_BIF_LS |
1758 AMD_CG_SUPPORT_VCE_MGCG |
1759 AMD_CG_SUPPORT_UVD_MGCG |
1760 AMD_CG_SUPPORT_HDP_LS |
1761 AMD_CG_SUPPORT_HDP_MGCG;
1762 adev->pg_flags =
1763
1764
1765 AMD_PG_SUPPORT_UVD |
1766
1767
1768
1769
1770
1771 0;
1772 if (adev->asic_type == CHIP_KABINI) {
1773 if (adev->rev_id == 0)
1774 adev->external_rev_id = 0x81;
1775 else if (adev->rev_id == 1)
1776 adev->external_rev_id = 0x82;
1777 else if (adev->rev_id == 2)
1778 adev->external_rev_id = 0x85;
1779 } else
1780 adev->external_rev_id = adev->rev_id + 0xa1;
1781 break;
1782 default:
1783
1784 return -EINVAL;
1785 }
1786
1787 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1788
1789 amdgpu_get_pcie_info(adev);
1790
1791 return 0;
1792}
1793
1794static int cik_common_sw_init(void *handle)
1795{
1796 return 0;
1797}
1798
1799static int cik_common_sw_fini(void *handle)
1800{
1801 return 0;
1802}
1803
1804static int cik_common_hw_init(void *handle)
1805{
1806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1807
1808
1809 cik_init_golden_registers(adev);
1810
1811 cik_pcie_gen3_enable(adev);
1812
1813 cik_program_aspm(adev);
1814
1815 return 0;
1816}
1817
1818static int cik_common_hw_fini(void *handle)
1819{
1820 return 0;
1821}
1822
1823static int cik_common_suspend(void *handle)
1824{
1825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1826
1827 amdgpu_amdkfd_suspend(adev);
1828
1829 return cik_common_hw_fini(adev);
1830}
1831
1832static int cik_common_resume(void *handle)
1833{
1834 int r;
1835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1836
1837 r = cik_common_hw_init(adev);
1838 if (r)
1839 return r;
1840
1841 return amdgpu_amdkfd_resume(adev);
1842}
1843
1844static bool cik_common_is_idle(void *handle)
1845{
1846 return true;
1847}
1848
1849static int cik_common_wait_for_idle(void *handle)
1850{
1851 return 0;
1852}
1853
1854static int cik_common_soft_reset(void *handle)
1855{
1856
1857 return 0;
1858}
1859
1860static int cik_common_set_clockgating_state(void *handle,
1861 enum amd_clockgating_state state)
1862{
1863 return 0;
1864}
1865
1866static int cik_common_set_powergating_state(void *handle,
1867 enum amd_powergating_state state)
1868{
1869 return 0;
1870}
1871
1872static const struct amd_ip_funcs cik_common_ip_funcs = {
1873 .name = "cik_common",
1874 .early_init = cik_common_early_init,
1875 .late_init = NULL,
1876 .sw_init = cik_common_sw_init,
1877 .sw_fini = cik_common_sw_fini,
1878 .hw_init = cik_common_hw_init,
1879 .hw_fini = cik_common_hw_fini,
1880 .suspend = cik_common_suspend,
1881 .resume = cik_common_resume,
1882 .is_idle = cik_common_is_idle,
1883 .wait_for_idle = cik_common_wait_for_idle,
1884 .soft_reset = cik_common_soft_reset,
1885 .set_clockgating_state = cik_common_set_clockgating_state,
1886 .set_powergating_state = cik_common_set_powergating_state,
1887};
1888
1889static const struct amdgpu_ip_block_version cik_common_ip_block =
1890{
1891 .type = AMD_IP_BLOCK_TYPE_COMMON,
1892 .major = 1,
1893 .minor = 0,
1894 .rev = 0,
1895 .funcs = &cik_common_ip_funcs,
1896};
1897
1898int cik_set_ip_blocks(struct amdgpu_device *adev)
1899{
1900 cik_detect_hw_virtualization(adev);
1901
1902 switch (adev->asic_type) {
1903 case CHIP_BONAIRE:
1904 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1905 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1906 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1907 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1908 if (adev->enable_virtual_display)
1909 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1910 else
1911 amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
1912 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
1913 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1914 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1915 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1916 break;
1917 case CHIP_HAWAII:
1918 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1919 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1920 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1921 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1922 if (adev->enable_virtual_display)
1923 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1924 else
1925 amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
1926 amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
1927 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1928 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1929 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1930 break;
1931 case CHIP_KAVERI:
1932 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1933 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1934 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1935 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1936 if (adev->enable_virtual_display)
1937 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1938 else
1939 amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
1940 amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
1941 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1942 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1943 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1944 break;
1945 case CHIP_KABINI:
1946 case CHIP_MULLINS:
1947 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1948 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1949 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1950 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1951 if (adev->enable_virtual_display)
1952 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1953 else
1954 amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
1955 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
1956 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1957 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1958 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1959 break;
1960 default:
1961
1962 return -EINVAL;
1963 }
1964 return 0;
1965}
1966
