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23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
28#include "clearstate_si.h"
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gca/gfx_6_0_d.h"
34#include "gca/gfx_6_0_sh_mask.h"
35#include "gmc/gmc_6_0_d.h"
36#include "gmc/gmc_6_0_sh_mask.h"
37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
41
42static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
43static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
44static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
45
46MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
47MODULE_FIRMWARE("radeon/tahiti_me.bin");
48MODULE_FIRMWARE("radeon/tahiti_ce.bin");
49MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
50
51MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
52MODULE_FIRMWARE("radeon/pitcairn_me.bin");
53MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
54MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
55
56MODULE_FIRMWARE("radeon/verde_pfp.bin");
57MODULE_FIRMWARE("radeon/verde_me.bin");
58MODULE_FIRMWARE("radeon/verde_ce.bin");
59MODULE_FIRMWARE("radeon/verde_rlc.bin");
60
61MODULE_FIRMWARE("radeon/oland_pfp.bin");
62MODULE_FIRMWARE("radeon/oland_me.bin");
63MODULE_FIRMWARE("radeon/oland_ce.bin");
64MODULE_FIRMWARE("radeon/oland_rlc.bin");
65
66MODULE_FIRMWARE("radeon/hainan_pfp.bin");
67MODULE_FIRMWARE("radeon/hainan_me.bin");
68MODULE_FIRMWARE("radeon/hainan_ce.bin");
69MODULE_FIRMWARE("radeon/hainan_rlc.bin");
70
71static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
72static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
73
74static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
75
76#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
77#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
78#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
79#define MICRO_TILE_MODE(x) ((x) << 0)
80#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
81#define BANK_WIDTH(x) ((x) << 14)
82#define BANK_HEIGHT(x) ((x) << 16)
83#define MACRO_TILE_ASPECT(x) ((x) << 18)
84#define NUM_BANKS(x) ((x) << 20)
85
86static const u32 verde_rlc_save_restore_register_list[] =
87{
88 (0x8000 << 16) | (0x98f4 >> 2),
89 0x00000000,
90 (0x8040 << 16) | (0x98f4 >> 2),
91 0x00000000,
92 (0x8000 << 16) | (0xe80 >> 2),
93 0x00000000,
94 (0x8040 << 16) | (0xe80 >> 2),
95 0x00000000,
96 (0x8000 << 16) | (0x89bc >> 2),
97 0x00000000,
98 (0x8040 << 16) | (0x89bc >> 2),
99 0x00000000,
100 (0x8000 << 16) | (0x8c1c >> 2),
101 0x00000000,
102 (0x8040 << 16) | (0x8c1c >> 2),
103 0x00000000,
104 (0x9c00 << 16) | (0x98f0 >> 2),
105 0x00000000,
106 (0x9c00 << 16) | (0xe7c >> 2),
107 0x00000000,
108 (0x8000 << 16) | (0x9148 >> 2),
109 0x00000000,
110 (0x8040 << 16) | (0x9148 >> 2),
111 0x00000000,
112 (0x9c00 << 16) | (0x9150 >> 2),
113 0x00000000,
114 (0x9c00 << 16) | (0x897c >> 2),
115 0x00000000,
116 (0x9c00 << 16) | (0x8d8c >> 2),
117 0x00000000,
118 (0x9c00 << 16) | (0xac54 >> 2),
119 0X00000000,
120 0x3,
121 (0x9c00 << 16) | (0x98f8 >> 2),
122 0x00000000,
123 (0x9c00 << 16) | (0x9910 >> 2),
124 0x00000000,
125 (0x9c00 << 16) | (0x9914 >> 2),
126 0x00000000,
127 (0x9c00 << 16) | (0x9918 >> 2),
128 0x00000000,
129 (0x9c00 << 16) | (0x991c >> 2),
130 0x00000000,
131 (0x9c00 << 16) | (0x9920 >> 2),
132 0x00000000,
133 (0x9c00 << 16) | (0x9924 >> 2),
134 0x00000000,
135 (0x9c00 << 16) | (0x9928 >> 2),
136 0x00000000,
137 (0x9c00 << 16) | (0x992c >> 2),
138 0x00000000,
139 (0x9c00 << 16) | (0x9930 >> 2),
140 0x00000000,
141 (0x9c00 << 16) | (0x9934 >> 2),
142 0x00000000,
143 (0x9c00 << 16) | (0x9938 >> 2),
144 0x00000000,
145 (0x9c00 << 16) | (0x993c >> 2),
146 0x00000000,
147 (0x9c00 << 16) | (0x9940 >> 2),
148 0x00000000,
149 (0x9c00 << 16) | (0x9944 >> 2),
150 0x00000000,
151 (0x9c00 << 16) | (0x9948 >> 2),
152 0x00000000,
153 (0x9c00 << 16) | (0x994c >> 2),
154 0x00000000,
155 (0x9c00 << 16) | (0x9950 >> 2),
156 0x00000000,
157 (0x9c00 << 16) | (0x9954 >> 2),
158 0x00000000,
159 (0x9c00 << 16) | (0x9958 >> 2),
160 0x00000000,
161 (0x9c00 << 16) | (0x995c >> 2),
162 0x00000000,
163 (0x9c00 << 16) | (0x9960 >> 2),
164 0x00000000,
165 (0x9c00 << 16) | (0x9964 >> 2),
166 0x00000000,
167 (0x9c00 << 16) | (0x9968 >> 2),
168 0x00000000,
169 (0x9c00 << 16) | (0x996c >> 2),
170 0x00000000,
171 (0x9c00 << 16) | (0x9970 >> 2),
172 0x00000000,
173 (0x9c00 << 16) | (0x9974 >> 2),
174 0x00000000,
175 (0x9c00 << 16) | (0x9978 >> 2),
176 0x00000000,
177 (0x9c00 << 16) | (0x997c >> 2),
178 0x00000000,
179 (0x9c00 << 16) | (0x9980 >> 2),
180 0x00000000,
181 (0x9c00 << 16) | (0x9984 >> 2),
182 0x00000000,
183 (0x9c00 << 16) | (0x9988 >> 2),
184 0x00000000,
185 (0x9c00 << 16) | (0x998c >> 2),
186 0x00000000,
187 (0x9c00 << 16) | (0x8c00 >> 2),
188 0x00000000,
189 (0x9c00 << 16) | (0x8c14 >> 2),
190 0x00000000,
191 (0x9c00 << 16) | (0x8c04 >> 2),
192 0x00000000,
193 (0x9c00 << 16) | (0x8c08 >> 2),
194 0x00000000,
195 (0x8000 << 16) | (0x9b7c >> 2),
196 0x00000000,
197 (0x8040 << 16) | (0x9b7c >> 2),
198 0x00000000,
199 (0x8000 << 16) | (0xe84 >> 2),
200 0x00000000,
201 (0x8040 << 16) | (0xe84 >> 2),
202 0x00000000,
203 (0x8000 << 16) | (0x89c0 >> 2),
204 0x00000000,
205 (0x8040 << 16) | (0x89c0 >> 2),
206 0x00000000,
207 (0x8000 << 16) | (0x914c >> 2),
208 0x00000000,
209 (0x8040 << 16) | (0x914c >> 2),
210 0x00000000,
211 (0x8000 << 16) | (0x8c20 >> 2),
212 0x00000000,
213 (0x8040 << 16) | (0x8c20 >> 2),
214 0x00000000,
215 (0x8000 << 16) | (0x9354 >> 2),
216 0x00000000,
217 (0x8040 << 16) | (0x9354 >> 2),
218 0x00000000,
219 (0x9c00 << 16) | (0x9060 >> 2),
220 0x00000000,
221 (0x9c00 << 16) | (0x9364 >> 2),
222 0x00000000,
223 (0x9c00 << 16) | (0x9100 >> 2),
224 0x00000000,
225 (0x9c00 << 16) | (0x913c >> 2),
226 0x00000000,
227 (0x8000 << 16) | (0x90e0 >> 2),
228 0x00000000,
229 (0x8000 << 16) | (0x90e4 >> 2),
230 0x00000000,
231 (0x8000 << 16) | (0x90e8 >> 2),
232 0x00000000,
233 (0x8040 << 16) | (0x90e0 >> 2),
234 0x00000000,
235 (0x8040 << 16) | (0x90e4 >> 2),
236 0x00000000,
237 (0x8040 << 16) | (0x90e8 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x8bcc >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x8b24 >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x88c4 >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x8e50 >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0x8c0c >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0x8e58 >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0x8e5c >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0x9508 >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0x950c >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x9494 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0xac0c >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0xac10 >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0xac14 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0xae00 >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0xac08 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x88d4 >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x88c8 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0x88cc >> 2),
274 0x00000000,
275 (0x9c00 << 16) | (0x89b0 >> 2),
276 0x00000000,
277 (0x9c00 << 16) | (0x8b10 >> 2),
278 0x00000000,
279 (0x9c00 << 16) | (0x8a14 >> 2),
280 0x00000000,
281 (0x9c00 << 16) | (0x9830 >> 2),
282 0x00000000,
283 (0x9c00 << 16) | (0x9834 >> 2),
284 0x00000000,
285 (0x9c00 << 16) | (0x9838 >> 2),
286 0x00000000,
287 (0x9c00 << 16) | (0x9a10 >> 2),
288 0x00000000,
289 (0x8000 << 16) | (0x9870 >> 2),
290 0x00000000,
291 (0x8000 << 16) | (0x9874 >> 2),
292 0x00000000,
293 (0x8001 << 16) | (0x9870 >> 2),
294 0x00000000,
295 (0x8001 << 16) | (0x9874 >> 2),
296 0x00000000,
297 (0x8040 << 16) | (0x9870 >> 2),
298 0x00000000,
299 (0x8040 << 16) | (0x9874 >> 2),
300 0x00000000,
301 (0x8041 << 16) | (0x9870 >> 2),
302 0x00000000,
303 (0x8041 << 16) | (0x9874 >> 2),
304 0x00000000,
305 0x00000000
306};
307
308static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
309{
310 const char *chip_name;
311 char fw_name[30];
312 int err;
313 const struct gfx_firmware_header_v1_0 *cp_hdr;
314 const struct rlc_firmware_header_v1_0 *rlc_hdr;
315
316 DRM_DEBUG("\n");
317
318 switch (adev->asic_type) {
319 case CHIP_TAHITI:
320 chip_name = "tahiti";
321 break;
322 case CHIP_PITCAIRN:
323 chip_name = "pitcairn";
324 break;
325 case CHIP_VERDE:
326 chip_name = "verde";
327 break;
328 case CHIP_OLAND:
329 chip_name = "oland";
330 break;
331 case CHIP_HAINAN:
332 chip_name = "hainan";
333 break;
334 default: BUG();
335 }
336
337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
339 if (err)
340 goto out;
341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
342 if (err)
343 goto out;
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
347
348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
350 if (err)
351 goto out;
352 err = amdgpu_ucode_validate(adev->gfx.me_fw);
353 if (err)
354 goto out;
355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
358
359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
361 if (err)
362 goto out;
363 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
364 if (err)
365 goto out;
366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
369
370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
372 if (err)
373 goto out;
374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
378
379out:
380 if (err) {
381 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
382 release_firmware(adev->gfx.pfp_fw);
383 adev->gfx.pfp_fw = NULL;
384 release_firmware(adev->gfx.me_fw);
385 adev->gfx.me_fw = NULL;
386 release_firmware(adev->gfx.ce_fw);
387 adev->gfx.ce_fw = NULL;
388 release_firmware(adev->gfx.rlc_fw);
389 adev->gfx.rlc_fw = NULL;
390 }
391 return err;
392}
393
394static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
395{
396 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
397 u32 reg_offset, split_equal_to_row_size, *tilemode;
398
399 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
400 tilemode = adev->gfx.config.tile_mode_array;
401
402 switch (adev->gfx.config.mem_row_size_in_kb) {
403 case 1:
404 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
405 break;
406 case 2:
407 default:
408 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
409 break;
410 case 4:
411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
412 break;
413 }
414
415 if (adev->asic_type == CHIP_VERDE) {
416 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
418 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
420 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
423 NUM_BANKS(ADDR_SURF_16_BANK);
424 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
426 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
427 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
431 NUM_BANKS(ADDR_SURF_16_BANK);
432 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
434 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
435 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
439 NUM_BANKS(ADDR_SURF_16_BANK);
440 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
442 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
446 NUM_BANKS(ADDR_SURF_8_BANK) |
447 TILE_SPLIT(split_equal_to_row_size);
448 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16);
451 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
452 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
453 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
454 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
455 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
458 NUM_BANKS(ADDR_SURF_4_BANK);
459 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
461 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
462 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
466 NUM_BANKS(ADDR_SURF_4_BANK);
467 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
474 NUM_BANKS(ADDR_SURF_2_BANK);
475 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
476 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
477 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
478 PIPE_CONFIG(ADDR_SURF_P4_8x16);
479 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
480 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
481 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
482 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
486 NUM_BANKS(ADDR_SURF_16_BANK);
487 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
489 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
490 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
494 NUM_BANKS(ADDR_SURF_16_BANK);
495 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
497 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
500 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
501 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
502 NUM_BANKS(ADDR_SURF_16_BANK);
503 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
504 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
505 PIPE_CONFIG(ADDR_SURF_P4_8x16);
506 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
507 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
508 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
510 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
513 NUM_BANKS(ADDR_SURF_16_BANK);
514 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
515 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
516 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
521 NUM_BANKS(ADDR_SURF_16_BANK);
522 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
523 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
524 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
526 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
529 NUM_BANKS(ADDR_SURF_16_BANK);
530 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
531 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
536 NUM_BANKS(ADDR_SURF_16_BANK) |
537 TILE_SPLIT(split_equal_to_row_size);
538 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
539 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16);
541 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
542 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
543 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
544 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
547 NUM_BANKS(ADDR_SURF_16_BANK) |
548 TILE_SPLIT(split_equal_to_row_size);
549 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
551 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
552 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
555 NUM_BANKS(ADDR_SURF_16_BANK) |
556 TILE_SPLIT(split_equal_to_row_size);
557 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
558 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
560 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
561 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
564 NUM_BANKS(ADDR_SURF_8_BANK);
565 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
566 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
567 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
568 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
572 NUM_BANKS(ADDR_SURF_8_BANK);
573 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
574 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
575 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
580 NUM_BANKS(ADDR_SURF_4_BANK);
581 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
582 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
583 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
584 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
588 NUM_BANKS(ADDR_SURF_4_BANK);
589 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
591 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
592 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
596 NUM_BANKS(ADDR_SURF_2_BANK);
597 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
598 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
604 NUM_BANKS(ADDR_SURF_2_BANK);
605 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
606 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
607 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
609 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
610 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
611 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
612 NUM_BANKS(ADDR_SURF_2_BANK);
613 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
614 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
615 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
617 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
620 NUM_BANKS(ADDR_SURF_2_BANK);
621 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
623 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
628 NUM_BANKS(ADDR_SURF_2_BANK);
629 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
631 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
636 NUM_BANKS(ADDR_SURF_2_BANK);
637 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
638 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
639 } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) {
640 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
641 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
642 PIPE_CONFIG(ADDR_SURF_P2) |
643 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
644 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
645 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
646 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
647 NUM_BANKS(ADDR_SURF_16_BANK);
648 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
649 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
650 PIPE_CONFIG(ADDR_SURF_P2) |
651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
652 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
653 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
654 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
655 NUM_BANKS(ADDR_SURF_16_BANK);
656 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
657 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
658 PIPE_CONFIG(ADDR_SURF_P2) |
659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
660 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
661 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
662 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
663 NUM_BANKS(ADDR_SURF_16_BANK);
664 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
665 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
666 PIPE_CONFIG(ADDR_SURF_P2) |
667 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
668 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
669 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
670 NUM_BANKS(ADDR_SURF_8_BANK) |
671 TILE_SPLIT(split_equal_to_row_size);
672 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
673 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
674 PIPE_CONFIG(ADDR_SURF_P2);
675 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
676 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
677 PIPE_CONFIG(ADDR_SURF_P2) |
678 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
679 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
680 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
681 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
682 NUM_BANKS(ADDR_SURF_8_BANK);
683 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
684 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
685 PIPE_CONFIG(ADDR_SURF_P2) |
686 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
687 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
688 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
689 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
690 NUM_BANKS(ADDR_SURF_8_BANK);
691 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
693 PIPE_CONFIG(ADDR_SURF_P2) |
694 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
698 NUM_BANKS(ADDR_SURF_4_BANK);
699 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
700 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
701 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
702 PIPE_CONFIG(ADDR_SURF_P2);
703 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
704 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
705 PIPE_CONFIG(ADDR_SURF_P2) |
706 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
707 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
708 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
709 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
710 NUM_BANKS(ADDR_SURF_16_BANK);
711 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
712 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
713 PIPE_CONFIG(ADDR_SURF_P2) |
714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
717 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
718 NUM_BANKS(ADDR_SURF_16_BANK);
719 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
720 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
721 PIPE_CONFIG(ADDR_SURF_P2) |
722 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
723 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
725 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
726 NUM_BANKS(ADDR_SURF_16_BANK);
727 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
728 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
729 PIPE_CONFIG(ADDR_SURF_P2);
730 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
731 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
732 PIPE_CONFIG(ADDR_SURF_P2) |
733 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
737 NUM_BANKS(ADDR_SURF_16_BANK);
738 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
739 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
740 PIPE_CONFIG(ADDR_SURF_P2) |
741 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
745 NUM_BANKS(ADDR_SURF_16_BANK);
746 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
747 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
748 PIPE_CONFIG(ADDR_SURF_P2) |
749 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
753 NUM_BANKS(ADDR_SURF_16_BANK);
754 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
755 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
756 PIPE_CONFIG(ADDR_SURF_P2) |
757 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
758 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
759 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
760 NUM_BANKS(ADDR_SURF_16_BANK) |
761 TILE_SPLIT(split_equal_to_row_size);
762 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
763 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
764 PIPE_CONFIG(ADDR_SURF_P2);
765 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
766 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
767 PIPE_CONFIG(ADDR_SURF_P2) |
768 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
771 NUM_BANKS(ADDR_SURF_16_BANK) |
772 TILE_SPLIT(split_equal_to_row_size);
773 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
774 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
775 PIPE_CONFIG(ADDR_SURF_P2) |
776 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
778 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
779 NUM_BANKS(ADDR_SURF_16_BANK) |
780 TILE_SPLIT(split_equal_to_row_size);
781 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
782 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
783 PIPE_CONFIG(ADDR_SURF_P2) |
784 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
785 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
786 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
787 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
788 NUM_BANKS(ADDR_SURF_8_BANK);
789 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
790 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
791 PIPE_CONFIG(ADDR_SURF_P2) |
792 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
796 NUM_BANKS(ADDR_SURF_8_BANK);
797 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
798 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
799 PIPE_CONFIG(ADDR_SURF_P2) |
800 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
801 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
802 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
803 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
804 NUM_BANKS(ADDR_SURF_8_BANK);
805 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
806 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
807 PIPE_CONFIG(ADDR_SURF_P2) |
808 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
809 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
812 NUM_BANKS(ADDR_SURF_8_BANK);
813 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
814 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
815 PIPE_CONFIG(ADDR_SURF_P2) |
816 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
817 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
820 NUM_BANKS(ADDR_SURF_4_BANK);
821 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
822 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
823 PIPE_CONFIG(ADDR_SURF_P2) |
824 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
825 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
828 NUM_BANKS(ADDR_SURF_4_BANK);
829 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
830 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
831 PIPE_CONFIG(ADDR_SURF_P2) |
832 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
836 NUM_BANKS(ADDR_SURF_4_BANK);
837 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
838 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
839 PIPE_CONFIG(ADDR_SURF_P2) |
840 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
841 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
842 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
843 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
844 NUM_BANKS(ADDR_SURF_4_BANK);
845 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
846 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
847 PIPE_CONFIG(ADDR_SURF_P2) |
848 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
849 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
850 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
851 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
852 NUM_BANKS(ADDR_SURF_4_BANK);
853 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
854 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
855 PIPE_CONFIG(ADDR_SURF_P2) |
856 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
857 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
860 NUM_BANKS(ADDR_SURF_4_BANK);
861 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
862 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
863 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
864 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
865 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
866 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
867 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
868 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
870 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
871 NUM_BANKS(ADDR_SURF_16_BANK);
872 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
873 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
874 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
875 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
876 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
877 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
878 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
879 NUM_BANKS(ADDR_SURF_16_BANK);
880 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
881 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
882 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
883 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
884 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
885 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
886 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
887 NUM_BANKS(ADDR_SURF_16_BANK);
888 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
889 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
890 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
891 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
892 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
893 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
894 NUM_BANKS(ADDR_SURF_4_BANK) |
895 TILE_SPLIT(split_equal_to_row_size);
896 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
897 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
898 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
899 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
901 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
906 NUM_BANKS(ADDR_SURF_2_BANK);
907 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
909 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
914 NUM_BANKS(ADDR_SURF_2_BANK);
915 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
916 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
917 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
918 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
919 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
920 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
921 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
922 NUM_BANKS(ADDR_SURF_2_BANK);
923 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
924 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
925 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
926 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
927 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
928 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
929 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
930 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
931 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
932 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
933 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
934 NUM_BANKS(ADDR_SURF_16_BANK);
935 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
936 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
937 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
938 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
939 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
940 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
941 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
942 NUM_BANKS(ADDR_SURF_16_BANK);
943 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
944 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
945 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
946 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
947 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
948 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
949 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
950 NUM_BANKS(ADDR_SURF_16_BANK);
951 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
952 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
953 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
954 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
955 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
961 NUM_BANKS(ADDR_SURF_16_BANK);
962 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
963 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
964 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
965 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
966 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
967 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
968 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
969 NUM_BANKS(ADDR_SURF_16_BANK);
970 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
971 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
972 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
973 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
974 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
975 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
976 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
977 NUM_BANKS(ADDR_SURF_16_BANK);
978 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
979 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
980 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
984 NUM_BANKS(ADDR_SURF_16_BANK) |
985 TILE_SPLIT(split_equal_to_row_size);
986 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
987 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
988 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
989 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
990 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
991 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
992 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
993 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
994 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
995 NUM_BANKS(ADDR_SURF_16_BANK) |
996 TILE_SPLIT(split_equal_to_row_size);
997 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
998 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
999 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1003 NUM_BANKS(ADDR_SURF_16_BANK) |
1004 TILE_SPLIT(split_equal_to_row_size);
1005 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1006 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1007 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1008 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1009 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1010 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1011 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1012 NUM_BANKS(ADDR_SURF_4_BANK);
1013 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1014 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1017 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1018 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1019 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1020 NUM_BANKS(ADDR_SURF_4_BANK);
1021 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1022 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1023 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1024 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1025 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1026 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1027 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1028 NUM_BANKS(ADDR_SURF_2_BANK);
1029 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1030 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1031 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1032 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1033 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1034 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1035 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1036 NUM_BANKS(ADDR_SURF_2_BANK);
1037 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1038 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1039 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1040 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1041 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1042 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1043 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1044 NUM_BANKS(ADDR_SURF_2_BANK);
1045 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1046 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1047 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1049 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1050 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1051 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1052 NUM_BANKS(ADDR_SURF_2_BANK);
1053 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1054 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1055 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1057 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1058 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1059 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1060 NUM_BANKS(ADDR_SURF_2_BANK);
1061 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1062 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1063 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1065 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1066 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1067 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1068 NUM_BANKS(ADDR_SURF_2_BANK);
1069 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1070 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1072 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1073 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1074 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1075 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1076 NUM_BANKS(ADDR_SURF_2_BANK);
1077 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1078 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1079 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1080 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1081 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1082 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1083 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1084 NUM_BANKS(ADDR_SURF_2_BANK);
1085 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1086 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1087 } else {
1088 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1089 }
1090}
1091
1092static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1093 u32 sh_num, u32 instance)
1094{
1095 u32 data;
1096
1097 if (instance == 0xffffffff)
1098 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1099 else
1100 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1101
1102 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1103 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1104 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1105 else if (se_num == 0xffffffff)
1106 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1107 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1108 else if (sh_num == 0xffffffff)
1109 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1110 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1111 else
1112 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1113 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1114 WREG32(mmGRBM_GFX_INDEX, data);
1115}
1116
1117static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1118{
1119 u32 data, mask;
1120
1121 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1122 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1123
1124 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1125
1126 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1127 adev->gfx.config.max_sh_per_se);
1128
1129 return ~data & mask;
1130}
1131
1132static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1133{
1134 switch (adev->asic_type) {
1135 case CHIP_TAHITI:
1136 case CHIP_PITCAIRN:
1137 *rconf |=
1138 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1139 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1140 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1141 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1142 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1143 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1144 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1145 break;
1146 case CHIP_VERDE:
1147 *rconf |=
1148 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1149 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1150 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1151 break;
1152 case CHIP_OLAND:
1153 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1154 break;
1155 case CHIP_HAINAN:
1156 *rconf |= 0x0;
1157 break;
1158 default:
1159 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1160 break;
1161 }
1162}
1163
1164static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1165 u32 raster_config, unsigned rb_mask,
1166 unsigned num_rb)
1167{
1168 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1169 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1170 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1171 unsigned rb_per_se = num_rb / num_se;
1172 unsigned se_mask[4];
1173 unsigned se;
1174
1175 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1176 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1177 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1178 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1179
1180 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1181 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1182 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1183
1184 for (se = 0; se < num_se; se++) {
1185 unsigned raster_config_se = raster_config;
1186 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1187 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1188 int idx = (se / 2) * 2;
1189
1190 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1191 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1192
1193 if (!se_mask[idx])
1194 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1195 else
1196 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1197 }
1198
1199 pkr0_mask &= rb_mask;
1200 pkr1_mask &= rb_mask;
1201 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1202 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1203
1204 if (!pkr0_mask)
1205 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1206 else
1207 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1208 }
1209
1210 if (rb_per_se >= 2) {
1211 unsigned rb0_mask = 1 << (se * rb_per_se);
1212 unsigned rb1_mask = rb0_mask << 1;
1213
1214 rb0_mask &= rb_mask;
1215 rb1_mask &= rb_mask;
1216 if (!rb0_mask || !rb1_mask) {
1217 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1218
1219 if (!rb0_mask)
1220 raster_config_se |=
1221 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1222 else
1223 raster_config_se |=
1224 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1225 }
1226
1227 if (rb_per_se > 2) {
1228 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1229 rb1_mask = rb0_mask << 1;
1230 rb0_mask &= rb_mask;
1231 rb1_mask &= rb_mask;
1232 if (!rb0_mask || !rb1_mask) {
1233 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1234
1235 if (!rb0_mask)
1236 raster_config_se |=
1237 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1238 else
1239 raster_config_se |=
1240 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1241 }
1242 }
1243 }
1244
1245
1246 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1247 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1248 }
1249
1250
1251 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1252}
1253
1254static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1255{
1256 int i, j;
1257 u32 data;
1258 u32 raster_config = 0;
1259 u32 active_rbs = 0;
1260 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1261 adev->gfx.config.max_sh_per_se;
1262 unsigned num_rb_pipes;
1263
1264 mutex_lock(&adev->grbm_idx_mutex);
1265 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1266 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1267 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1268 data = gfx_v6_0_get_rb_active_bitmap(adev);
1269 active_rbs |= data <<
1270 ((i * adev->gfx.config.max_sh_per_se + j) *
1271 rb_bitmap_width_per_sh);
1272 }
1273 }
1274 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1275
1276 adev->gfx.config.backend_enable_mask = active_rbs;
1277 adev->gfx.config.num_rbs = hweight32(active_rbs);
1278
1279 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1280 adev->gfx.config.max_shader_engines, 16);
1281
1282 gfx_v6_0_raster_config(adev, &raster_config);
1283
1284 if (!adev->gfx.config.backend_enable_mask ||
1285 adev->gfx.config.num_rbs >= num_rb_pipes)
1286 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1287 else
1288 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1289 adev->gfx.config.backend_enable_mask,
1290 num_rb_pipes);
1291
1292
1293 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1294 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1295 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1296 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1297 RREG32(mmCC_RB_BACKEND_DISABLE);
1298 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1299 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1300 adev->gfx.config.rb_config[i][j].raster_config =
1301 RREG32(mmPA_SC_RASTER_CONFIG);
1302 }
1303 }
1304 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1305 mutex_unlock(&adev->grbm_idx_mutex);
1306}
1307
1308static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1309 u32 bitmap)
1310{
1311 u32 data;
1312
1313 if (!bitmap)
1314 return;
1315
1316 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1317 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1318
1319 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1320}
1321
1322static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1323{
1324 u32 data, mask;
1325
1326 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1327 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1328
1329 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1330 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1331}
1332
1333
1334static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1335{
1336 int i, j, k;
1337 u32 data, mask;
1338 u32 active_cu = 0;
1339
1340 mutex_lock(&adev->grbm_idx_mutex);
1341 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1342 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1343 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1344 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1345 active_cu = gfx_v6_0_get_cu_enabled(adev);
1346
1347 mask = 1;
1348 for (k = 0; k < 16; k++) {
1349 mask <<= k;
1350 if (active_cu & mask) {
1351 data &= ~mask;
1352 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1353 break;
1354 }
1355 }
1356 }
1357 }
1358 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1359 mutex_unlock(&adev->grbm_idx_mutex);
1360}
1361
1362static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1363{
1364 adev->gfx.config.double_offchip_lds_buf = 0;
1365}
1366
1367static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1368{
1369 u32 gb_addr_config = 0;
1370 u32 mc_shared_chmap, mc_arb_ramcfg;
1371 u32 sx_debug_1;
1372 u32 hdp_host_path_cntl;
1373 u32 tmp;
1374
1375 switch (adev->asic_type) {
1376 case CHIP_TAHITI:
1377 adev->gfx.config.max_shader_engines = 2;
1378 adev->gfx.config.max_tile_pipes = 12;
1379 adev->gfx.config.max_cu_per_sh = 8;
1380 adev->gfx.config.max_sh_per_se = 2;
1381 adev->gfx.config.max_backends_per_se = 4;
1382 adev->gfx.config.max_texture_channel_caches = 12;
1383 adev->gfx.config.max_gprs = 256;
1384 adev->gfx.config.max_gs_threads = 32;
1385 adev->gfx.config.max_hw_contexts = 8;
1386
1387 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1388 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1389 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1390 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1391 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1392 break;
1393 case CHIP_PITCAIRN:
1394 adev->gfx.config.max_shader_engines = 2;
1395 adev->gfx.config.max_tile_pipes = 8;
1396 adev->gfx.config.max_cu_per_sh = 5;
1397 adev->gfx.config.max_sh_per_se = 2;
1398 adev->gfx.config.max_backends_per_se = 4;
1399 adev->gfx.config.max_texture_channel_caches = 8;
1400 adev->gfx.config.max_gprs = 256;
1401 adev->gfx.config.max_gs_threads = 32;
1402 adev->gfx.config.max_hw_contexts = 8;
1403
1404 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1405 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1406 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1407 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1408 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1409 break;
1410 case CHIP_VERDE:
1411 adev->gfx.config.max_shader_engines = 1;
1412 adev->gfx.config.max_tile_pipes = 4;
1413 adev->gfx.config.max_cu_per_sh = 5;
1414 adev->gfx.config.max_sh_per_se = 2;
1415 adev->gfx.config.max_backends_per_se = 4;
1416 adev->gfx.config.max_texture_channel_caches = 4;
1417 adev->gfx.config.max_gprs = 256;
1418 adev->gfx.config.max_gs_threads = 32;
1419 adev->gfx.config.max_hw_contexts = 8;
1420
1421 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1422 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1423 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1424 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1425 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1426 break;
1427 case CHIP_OLAND:
1428 adev->gfx.config.max_shader_engines = 1;
1429 adev->gfx.config.max_tile_pipes = 4;
1430 adev->gfx.config.max_cu_per_sh = 6;
1431 adev->gfx.config.max_sh_per_se = 1;
1432 adev->gfx.config.max_backends_per_se = 2;
1433 adev->gfx.config.max_texture_channel_caches = 4;
1434 adev->gfx.config.max_gprs = 256;
1435 adev->gfx.config.max_gs_threads = 16;
1436 adev->gfx.config.max_hw_contexts = 8;
1437
1438 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1439 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1440 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1441 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1442 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1443 break;
1444 case CHIP_HAINAN:
1445 adev->gfx.config.max_shader_engines = 1;
1446 adev->gfx.config.max_tile_pipes = 4;
1447 adev->gfx.config.max_cu_per_sh = 5;
1448 adev->gfx.config.max_sh_per_se = 1;
1449 adev->gfx.config.max_backends_per_se = 1;
1450 adev->gfx.config.max_texture_channel_caches = 2;
1451 adev->gfx.config.max_gprs = 256;
1452 adev->gfx.config.max_gs_threads = 16;
1453 adev->gfx.config.max_hw_contexts = 8;
1454
1455 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1456 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1457 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1458 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1459 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1460 break;
1461 default:
1462 BUG();
1463 break;
1464 }
1465
1466 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1467 WREG32(mmSRBM_INT_CNTL, 1);
1468 WREG32(mmSRBM_INT_ACK, 1);
1469
1470 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1471
1472 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1473 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1474 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1475
1476 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1477 adev->gfx.config.mem_max_burst_length_bytes = 256;
1478 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1479 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1480 if (adev->gfx.config.mem_row_size_in_kb > 4)
1481 adev->gfx.config.mem_row_size_in_kb = 4;
1482 adev->gfx.config.shader_engine_tile_size = 32;
1483 adev->gfx.config.num_gpus = 1;
1484 adev->gfx.config.multi_gpu_tile_size = 64;
1485
1486 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1487 switch (adev->gfx.config.mem_row_size_in_kb) {
1488 case 1:
1489 default:
1490 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1491 break;
1492 case 2:
1493 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1494 break;
1495 case 4:
1496 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1497 break;
1498 }
1499 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1500 if (adev->gfx.config.max_shader_engines == 2)
1501 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1502 adev->gfx.config.gb_addr_config = gb_addr_config;
1503
1504 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1505 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1506 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1507 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1508 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1509 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1510
1511#if 0
1512 if (adev->has_uvd) {
1513 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1514 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1515 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1516 }
1517#endif
1518 gfx_v6_0_tiling_mode_table_init(adev);
1519
1520 gfx_v6_0_setup_rb(adev);
1521
1522 gfx_v6_0_setup_spi(adev);
1523
1524 gfx_v6_0_get_cu_info(adev);
1525 gfx_v6_0_config_init(adev);
1526
1527 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1528 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1529 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1530 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1531
1532 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1533 WREG32(mmSX_DEBUG_1, sx_debug_1);
1534
1535 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1536
1537 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1538 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1539 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1540 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1541
1542 WREG32(mmVGT_NUM_INSTANCES, 1);
1543 WREG32(mmCP_PERFMON_CNTL, 0);
1544 WREG32(mmSQ_CONFIG, 0);
1545 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1546 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1547
1548 WREG32(mmVGT_CACHE_INVALIDATION,
1549 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1550 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1551
1552 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1553 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1554
1555 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1556 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1557 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1558 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1559 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1560 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1561 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1562 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1563
1564 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1565 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1566
1567 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1568 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1569
1570 udelay(50);
1571}
1572
1573
1574static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1575{
1576 adev->gfx.scratch.num_reg = 7;
1577 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1578 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1579}
1580
1581static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1582{
1583 struct amdgpu_device *adev = ring->adev;
1584 uint32_t scratch;
1585 uint32_t tmp = 0;
1586 unsigned i;
1587 int r;
1588
1589 r = amdgpu_gfx_scratch_get(adev, &scratch);
1590 if (r) {
1591 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1592 return r;
1593 }
1594 WREG32(scratch, 0xCAFEDEAD);
1595
1596 r = amdgpu_ring_alloc(ring, 3);
1597 if (r) {
1598 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1599 amdgpu_gfx_scratch_free(adev, scratch);
1600 return r;
1601 }
1602 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1603 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1604 amdgpu_ring_write(ring, 0xDEADBEEF);
1605 amdgpu_ring_commit(ring);
1606
1607 for (i = 0; i < adev->usec_timeout; i++) {
1608 tmp = RREG32(scratch);
1609 if (tmp == 0xDEADBEEF)
1610 break;
1611 DRM_UDELAY(1);
1612 }
1613 if (i < adev->usec_timeout) {
1614 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1615 } else {
1616 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1617 ring->idx, scratch, tmp);
1618 r = -EINVAL;
1619 }
1620 amdgpu_gfx_scratch_free(adev, scratch);
1621 return r;
1622}
1623
1624static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1625{
1626
1627 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1628 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1629 WRITE_DATA_DST_SEL(0)));
1630 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1631 amdgpu_ring_write(ring, 0);
1632 amdgpu_ring_write(ring, 0x1);
1633}
1634
1635static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1636{
1637 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1638 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1639 EVENT_INDEX(0));
1640}
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1651{
1652 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1653 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1654 WRITE_DATA_DST_SEL(0)));
1655 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1656 amdgpu_ring_write(ring, 0);
1657 amdgpu_ring_write(ring, 0x1);
1658}
1659
1660static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1661 u64 seq, unsigned flags)
1662{
1663 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1664 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1665
1666 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1667 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1668 amdgpu_ring_write(ring, 0);
1669 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1670 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1671 PACKET3_TC_ACTION_ENA |
1672 PACKET3_SH_KCACHE_ACTION_ENA |
1673 PACKET3_SH_ICACHE_ACTION_ENA);
1674 amdgpu_ring_write(ring, 0xFFFFFFFF);
1675 amdgpu_ring_write(ring, 0);
1676 amdgpu_ring_write(ring, 10);
1677
1678 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1679 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1680 amdgpu_ring_write(ring, addr & 0xfffffffc);
1681 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1682 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1683 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1684 amdgpu_ring_write(ring, lower_32_bits(seq));
1685 amdgpu_ring_write(ring, upper_32_bits(seq));
1686}
1687
1688static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1689 struct amdgpu_ib *ib,
1690 unsigned vm_id, bool ctx_switch)
1691{
1692 u32 header, control = 0;
1693
1694
1695 if (ctx_switch) {
1696 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1697 amdgpu_ring_write(ring, 0);
1698 }
1699
1700 if (ib->flags & AMDGPU_IB_FLAG_CE)
1701 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1702 else
1703 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1704
1705 control |= ib->length_dw | (vm_id << 24);
1706
1707 amdgpu_ring_write(ring, header);
1708 amdgpu_ring_write(ring,
1709#ifdef __BIG_ENDIAN
1710 (2 << 0) |
1711#endif
1712 (ib->gpu_addr & 0xFFFFFFFC));
1713 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1714 amdgpu_ring_write(ring, control);
1715}
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1727{
1728 struct amdgpu_device *adev = ring->adev;
1729 struct amdgpu_ib ib;
1730 struct dma_fence *f = NULL;
1731 uint32_t scratch;
1732 uint32_t tmp = 0;
1733 long r;
1734
1735 r = amdgpu_gfx_scratch_get(adev, &scratch);
1736 if (r) {
1737 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1738 return r;
1739 }
1740 WREG32(scratch, 0xCAFEDEAD);
1741 memset(&ib, 0, sizeof(ib));
1742 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1743 if (r) {
1744 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1745 goto err1;
1746 }
1747 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1748 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1749 ib.ptr[2] = 0xDEADBEEF;
1750 ib.length_dw = 3;
1751
1752 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1753 if (r)
1754 goto err2;
1755
1756 r = dma_fence_wait_timeout(f, false, timeout);
1757 if (r == 0) {
1758 DRM_ERROR("amdgpu: IB test timed out\n");
1759 r = -ETIMEDOUT;
1760 goto err2;
1761 } else if (r < 0) {
1762 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1763 goto err2;
1764 }
1765 tmp = RREG32(scratch);
1766 if (tmp == 0xDEADBEEF) {
1767 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1768 r = 0;
1769 } else {
1770 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1771 scratch, tmp);
1772 r = -EINVAL;
1773 }
1774
1775err2:
1776 amdgpu_ib_free(adev, &ib, NULL);
1777 dma_fence_put(f);
1778err1:
1779 amdgpu_gfx_scratch_free(adev, scratch);
1780 return r;
1781}
1782
1783static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1784{
1785 int i;
1786 if (enable) {
1787 WREG32(mmCP_ME_CNTL, 0);
1788 } else {
1789 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1790 CP_ME_CNTL__PFP_HALT_MASK |
1791 CP_ME_CNTL__CE_HALT_MASK));
1792 WREG32(mmSCRATCH_UMSK, 0);
1793 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1794 adev->gfx.gfx_ring[i].ready = false;
1795 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1796 adev->gfx.compute_ring[i].ready = false;
1797 }
1798 udelay(50);
1799}
1800
1801static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1802{
1803 unsigned i;
1804 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1805 const struct gfx_firmware_header_v1_0 *ce_hdr;
1806 const struct gfx_firmware_header_v1_0 *me_hdr;
1807 const __le32 *fw_data;
1808 u32 fw_size;
1809
1810 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1811 return -EINVAL;
1812
1813 gfx_v6_0_cp_gfx_enable(adev, false);
1814 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1815 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1816 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1817
1818 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1819 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1820 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1821
1822
1823 fw_data = (const __le32 *)
1824 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1825 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1826 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1827 for (i = 0; i < fw_size; i++)
1828 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1829 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1830
1831
1832 fw_data = (const __le32 *)
1833 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1834 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1835 WREG32(mmCP_CE_UCODE_ADDR, 0);
1836 for (i = 0; i < fw_size; i++)
1837 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1838 WREG32(mmCP_CE_UCODE_ADDR, 0);
1839
1840
1841 fw_data = (const __be32 *)
1842 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1843 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1844 WREG32(mmCP_ME_RAM_WADDR, 0);
1845 for (i = 0; i < fw_size; i++)
1846 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1847 WREG32(mmCP_ME_RAM_WADDR, 0);
1848
1849 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1850 WREG32(mmCP_CE_UCODE_ADDR, 0);
1851 WREG32(mmCP_ME_RAM_WADDR, 0);
1852 WREG32(mmCP_ME_RAM_RADDR, 0);
1853 return 0;
1854}
1855
1856static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1857{
1858 const struct cs_section_def *sect = NULL;
1859 const struct cs_extent_def *ext = NULL;
1860 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1861 int r, i;
1862
1863 r = amdgpu_ring_alloc(ring, 7 + 4);
1864 if (r) {
1865 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1866 return r;
1867 }
1868 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1869 amdgpu_ring_write(ring, 0x1);
1870 amdgpu_ring_write(ring, 0x0);
1871 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1872 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1873 amdgpu_ring_write(ring, 0);
1874 amdgpu_ring_write(ring, 0);
1875
1876 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1877 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1878 amdgpu_ring_write(ring, 0xc000);
1879 amdgpu_ring_write(ring, 0xe000);
1880 amdgpu_ring_commit(ring);
1881
1882 gfx_v6_0_cp_gfx_enable(adev, true);
1883
1884 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
1885 if (r) {
1886 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1887 return r;
1888 }
1889
1890 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1891 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1892
1893 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1894 for (ext = sect->section; ext->extent != NULL; ++ext) {
1895 if (sect->id == SECT_CONTEXT) {
1896 amdgpu_ring_write(ring,
1897 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1898 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1899 for (i = 0; i < ext->reg_count; i++)
1900 amdgpu_ring_write(ring, ext->extent[i]);
1901 }
1902 }
1903 }
1904
1905 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1906 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1907
1908 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1909 amdgpu_ring_write(ring, 0);
1910
1911 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1912 amdgpu_ring_write(ring, 0x00000316);
1913 amdgpu_ring_write(ring, 0x0000000e);
1914 amdgpu_ring_write(ring, 0x00000010);
1915
1916 amdgpu_ring_commit(ring);
1917
1918 return 0;
1919}
1920
1921static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1922{
1923 struct amdgpu_ring *ring;
1924 u32 tmp;
1925 u32 rb_bufsz;
1926 int r;
1927 u64 rptr_addr;
1928
1929 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
1930 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1931
1932
1933 WREG32(mmCP_RB_WPTR_DELAY, 0);
1934
1935 WREG32(mmCP_DEBUG, 0);
1936 WREG32(mmSCRATCH_ADDR, 0);
1937
1938
1939
1940 ring = &adev->gfx.gfx_ring[0];
1941 rb_bufsz = order_base_2(ring->ring_size / 8);
1942 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1943
1944#ifdef __BIG_ENDIAN
1945 tmp |= BUF_SWAP_32BIT;
1946#endif
1947 WREG32(mmCP_RB0_CNTL, tmp);
1948
1949
1950 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
1951 ring->wptr = 0;
1952 WREG32(mmCP_RB0_WPTR, ring->wptr);
1953
1954
1955 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1956 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1957 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1958
1959 WREG32(mmSCRATCH_UMSK, 0);
1960
1961 mdelay(1);
1962 WREG32(mmCP_RB0_CNTL, tmp);
1963
1964 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
1965
1966
1967 gfx_v6_0_cp_gfx_start(adev);
1968 ring->ready = true;
1969 r = amdgpu_ring_test_ring(ring);
1970 if (r) {
1971 ring->ready = false;
1972 return r;
1973 }
1974
1975 return 0;
1976}
1977
1978static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
1979{
1980 return ring->adev->wb.wb[ring->rptr_offs];
1981}
1982
1983static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
1984{
1985 struct amdgpu_device *adev = ring->adev;
1986
1987 if (ring == &adev->gfx.gfx_ring[0])
1988 return RREG32(mmCP_RB0_WPTR);
1989 else if (ring == &adev->gfx.compute_ring[0])
1990 return RREG32(mmCP_RB1_WPTR);
1991 else if (ring == &adev->gfx.compute_ring[1])
1992 return RREG32(mmCP_RB2_WPTR);
1993 else
1994 BUG();
1995}
1996
1997static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1998{
1999 struct amdgpu_device *adev = ring->adev;
2000
2001 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2002 (void)RREG32(mmCP_RB0_WPTR);
2003}
2004
2005static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2006{
2007 struct amdgpu_device *adev = ring->adev;
2008
2009 if (ring == &adev->gfx.compute_ring[0]) {
2010 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2011 (void)RREG32(mmCP_RB1_WPTR);
2012 } else if (ring == &adev->gfx.compute_ring[1]) {
2013 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2014 (void)RREG32(mmCP_RB2_WPTR);
2015 } else {
2016 BUG();
2017 }
2018
2019}
2020
2021static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2022{
2023 struct amdgpu_ring *ring;
2024 u32 tmp;
2025 u32 rb_bufsz;
2026 int i, r;
2027 u64 rptr_addr;
2028
2029
2030
2031
2032 ring = &adev->gfx.compute_ring[0];
2033 rb_bufsz = order_base_2(ring->ring_size / 8);
2034 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2035#ifdef __BIG_ENDIAN
2036 tmp |= BUF_SWAP_32BIT;
2037#endif
2038 WREG32(mmCP_RB1_CNTL, tmp);
2039
2040 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2041 ring->wptr = 0;
2042 WREG32(mmCP_RB1_WPTR, ring->wptr);
2043
2044 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2045 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2046 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2047
2048 mdelay(1);
2049 WREG32(mmCP_RB1_CNTL, tmp);
2050 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2051
2052 ring = &adev->gfx.compute_ring[1];
2053 rb_bufsz = order_base_2(ring->ring_size / 8);
2054 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2055#ifdef __BIG_ENDIAN
2056 tmp |= BUF_SWAP_32BIT;
2057#endif
2058 WREG32(mmCP_RB2_CNTL, tmp);
2059
2060 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2061 ring->wptr = 0;
2062 WREG32(mmCP_RB2_WPTR, ring->wptr);
2063 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2064 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2065 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2066
2067 mdelay(1);
2068 WREG32(mmCP_RB2_CNTL, tmp);
2069 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2070
2071 adev->gfx.compute_ring[0].ready = false;
2072 adev->gfx.compute_ring[1].ready = false;
2073
2074 for (i = 0; i < 2; i++) {
2075 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2076 if (r)
2077 return r;
2078 adev->gfx.compute_ring[i].ready = true;
2079 }
2080
2081 return 0;
2082}
2083
2084static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2085{
2086 gfx_v6_0_cp_gfx_enable(adev, enable);
2087}
2088
2089static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2090{
2091 return gfx_v6_0_cp_gfx_load_microcode(adev);
2092}
2093
2094static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2095 bool enable)
2096{
2097 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2098 u32 mask;
2099 int i;
2100
2101 if (enable)
2102 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2103 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2104 else
2105 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2106 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2107 WREG32(mmCP_INT_CNTL_RING0, tmp);
2108
2109 if (!enable) {
2110
2111 tmp = RREG32(mmDB_DEPTH_INFO);
2112
2113 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2114 for (i = 0; i < adev->usec_timeout; i++) {
2115 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2116 break;
2117 udelay(1);
2118 }
2119 }
2120}
2121
2122static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2123{
2124 int r;
2125
2126 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2127
2128 r = gfx_v6_0_cp_load_microcode(adev);
2129 if (r)
2130 return r;
2131
2132 r = gfx_v6_0_cp_gfx_resume(adev);
2133 if (r)
2134 return r;
2135 r = gfx_v6_0_cp_compute_resume(adev);
2136 if (r)
2137 return r;
2138
2139 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2140
2141 return 0;
2142}
2143
2144static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2145{
2146 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2147 uint32_t seq = ring->fence_drv.sync_seq;
2148 uint64_t addr = ring->fence_drv.gpu_addr;
2149
2150 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2151 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) |
2152 WAIT_REG_MEM_FUNCTION(3) |
2153 WAIT_REG_MEM_ENGINE(usepfp)));
2154 amdgpu_ring_write(ring, addr & 0xfffffffc);
2155 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2156 amdgpu_ring_write(ring, seq);
2157 amdgpu_ring_write(ring, 0xffffffff);
2158 amdgpu_ring_write(ring, 4);
2159
2160 if (usepfp) {
2161
2162 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2163 amdgpu_ring_write(ring, 0);
2164 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2165 amdgpu_ring_write(ring, 0);
2166 }
2167}
2168
2169static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2170 unsigned vm_id, uint64_t pd_addr)
2171{
2172 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2173
2174
2175 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2176 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2177 WRITE_DATA_DST_SEL(0)));
2178 if (vm_id < 8) {
2179 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
2180 } else {
2181 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
2182 }
2183 amdgpu_ring_write(ring, 0);
2184 amdgpu_ring_write(ring, pd_addr >> 12);
2185
2186
2187 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2188 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2189 WRITE_DATA_DST_SEL(0)));
2190 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2191 amdgpu_ring_write(ring, 0);
2192 amdgpu_ring_write(ring, 1 << vm_id);
2193
2194
2195 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2196 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |
2197 WAIT_REG_MEM_ENGINE(0)));
2198 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2199 amdgpu_ring_write(ring, 0);
2200 amdgpu_ring_write(ring, 0);
2201 amdgpu_ring_write(ring, 0);
2202 amdgpu_ring_write(ring, 0x20);
2203
2204 if (usepfp) {
2205
2206 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2207 amdgpu_ring_write(ring, 0x0);
2208
2209
2210 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2211 amdgpu_ring_write(ring, 0);
2212 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2213 amdgpu_ring_write(ring, 0);
2214 }
2215}
2216
2217
2218static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2219{
2220 int r;
2221
2222 if (adev->gfx.rlc.save_restore_obj) {
2223 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, true);
2224 if (unlikely(r != 0))
2225 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
2226 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
2227 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2228
2229 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
2230 adev->gfx.rlc.save_restore_obj = NULL;
2231 }
2232
2233 if (adev->gfx.rlc.clear_state_obj) {
2234 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
2235 if (unlikely(r != 0))
2236 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
2237 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
2238 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2239
2240 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2241 adev->gfx.rlc.clear_state_obj = NULL;
2242 }
2243
2244 if (adev->gfx.rlc.cp_table_obj) {
2245 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true);
2246 if (unlikely(r != 0))
2247 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
2248 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
2249 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
2250
2251 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
2252 adev->gfx.rlc.cp_table_obj = NULL;
2253 }
2254}
2255
2256static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2257{
2258 const u32 *src_ptr;
2259 volatile u32 *dst_ptr;
2260 u32 dws, i;
2261 u64 reg_list_mc_addr;
2262 const struct cs_section_def *cs_data;
2263 int r;
2264
2265 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2266 adev->gfx.rlc.reg_list_size =
2267 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2268
2269 adev->gfx.rlc.cs_data = si_cs_data;
2270 src_ptr = adev->gfx.rlc.reg_list;
2271 dws = adev->gfx.rlc.reg_list_size;
2272 cs_data = adev->gfx.rlc.cs_data;
2273
2274 if (src_ptr) {
2275
2276 if (adev->gfx.rlc.save_restore_obj == NULL) {
2277 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2278 AMDGPU_GEM_DOMAIN_VRAM,
2279 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2280 NULL, NULL,
2281 &adev->gfx.rlc.save_restore_obj);
2282
2283 if (r) {
2284 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2285 return r;
2286 }
2287 }
2288
2289 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2290 if (unlikely(r != 0)) {
2291 gfx_v6_0_rlc_fini(adev);
2292 return r;
2293 }
2294 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2295 &adev->gfx.rlc.save_restore_gpu_addr);
2296 if (r) {
2297 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2298 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2299 gfx_v6_0_rlc_fini(adev);
2300 return r;
2301 }
2302
2303 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2304 if (r) {
2305 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2306 gfx_v6_0_rlc_fini(adev);
2307 return r;
2308 }
2309
2310 dst_ptr = adev->gfx.rlc.sr_ptr;
2311 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2312 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2313 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2314 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2315 }
2316
2317 if (cs_data) {
2318
2319 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2320 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2321
2322 if (adev->gfx.rlc.clear_state_obj == NULL) {
2323 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2324 AMDGPU_GEM_DOMAIN_VRAM,
2325 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2326 NULL, NULL,
2327 &adev->gfx.rlc.clear_state_obj);
2328
2329 if (r) {
2330 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2331 gfx_v6_0_rlc_fini(adev);
2332 return r;
2333 }
2334 }
2335 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2336 if (unlikely(r != 0)) {
2337 gfx_v6_0_rlc_fini(adev);
2338 return r;
2339 }
2340 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2341 &adev->gfx.rlc.clear_state_gpu_addr);
2342 if (r) {
2343 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2344 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2345 gfx_v6_0_rlc_fini(adev);
2346 return r;
2347 }
2348
2349 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2350 if (r) {
2351 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2352 gfx_v6_0_rlc_fini(adev);
2353 return r;
2354 }
2355
2356 dst_ptr = adev->gfx.rlc.cs_ptr;
2357 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2358 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2359 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2360 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2361 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2362 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2363 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2364 }
2365
2366 return 0;
2367}
2368
2369static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2370{
2371 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2372
2373 if (!enable) {
2374 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2375 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2376 }
2377}
2378
2379static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2380{
2381 int i;
2382
2383 for (i = 0; i < adev->usec_timeout; i++) {
2384 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2385 break;
2386 udelay(1);
2387 }
2388
2389 for (i = 0; i < adev->usec_timeout; i++) {
2390 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2391 break;
2392 udelay(1);
2393 }
2394}
2395
2396static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2397{
2398 u32 tmp;
2399
2400 tmp = RREG32(mmRLC_CNTL);
2401 if (tmp != rlc)
2402 WREG32(mmRLC_CNTL, rlc);
2403}
2404
2405static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2406{
2407 u32 data, orig;
2408
2409 orig = data = RREG32(mmRLC_CNTL);
2410
2411 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2412 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2413 WREG32(mmRLC_CNTL, data);
2414
2415 gfx_v6_0_wait_for_rlc_serdes(adev);
2416 }
2417
2418 return orig;
2419}
2420
2421static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2422{
2423 WREG32(mmRLC_CNTL, 0);
2424
2425 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2426 gfx_v6_0_wait_for_rlc_serdes(adev);
2427}
2428
2429static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2430{
2431 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2432
2433 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2434
2435 udelay(50);
2436}
2437
2438static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2439{
2440 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2441 udelay(50);
2442 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2443 udelay(50);
2444}
2445
2446static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2447{
2448 u32 tmp;
2449
2450
2451 tmp = RREG32(mmMC_SEQ_MISC0);
2452 if ((tmp & 0xF0000000) == 0xB0000000)
2453 return true;
2454 return false;
2455}
2456
2457static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2458{
2459}
2460
2461static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2462{
2463 u32 i;
2464 const struct rlc_firmware_header_v1_0 *hdr;
2465 const __le32 *fw_data;
2466 u32 fw_size;
2467
2468
2469 if (!adev->gfx.rlc_fw)
2470 return -EINVAL;
2471
2472 gfx_v6_0_rlc_stop(adev);
2473 gfx_v6_0_rlc_reset(adev);
2474 gfx_v6_0_init_pg(adev);
2475 gfx_v6_0_init_cg(adev);
2476
2477 WREG32(mmRLC_RL_BASE, 0);
2478 WREG32(mmRLC_RL_SIZE, 0);
2479 WREG32(mmRLC_LB_CNTL, 0);
2480 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2481 WREG32(mmRLC_LB_CNTR_INIT, 0);
2482 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2483
2484 WREG32(mmRLC_MC_CNTL, 0);
2485 WREG32(mmRLC_UCODE_CNTL, 0);
2486
2487 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2488 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2489 fw_data = (const __le32 *)
2490 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2491
2492 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2493
2494 for (i = 0; i < fw_size; i++) {
2495 WREG32(mmRLC_UCODE_ADDR, i);
2496 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2497 }
2498 WREG32(mmRLC_UCODE_ADDR, 0);
2499
2500 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2501 gfx_v6_0_rlc_start(adev);
2502
2503 return 0;
2504}
2505
2506static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2507{
2508 u32 data, orig, tmp;
2509
2510 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2511
2512 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2513 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2514
2515 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2516
2517 tmp = gfx_v6_0_halt_rlc(adev);
2518
2519 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2520 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2521 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2522
2523 gfx_v6_0_wait_for_rlc_serdes(adev);
2524 gfx_v6_0_update_rlc(adev, tmp);
2525
2526 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2527
2528 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2529 } else {
2530 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2531
2532 RREG32(mmCB_CGTT_SCLK_CTRL);
2533 RREG32(mmCB_CGTT_SCLK_CTRL);
2534 RREG32(mmCB_CGTT_SCLK_CTRL);
2535 RREG32(mmCB_CGTT_SCLK_CTRL);
2536
2537 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2538 }
2539
2540 if (orig != data)
2541 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2542
2543}
2544
2545static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2546{
2547
2548 u32 data, orig, tmp = 0;
2549
2550 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2551 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2552 data = 0x96940200;
2553 if (orig != data)
2554 WREG32(mmCGTS_SM_CTRL_REG, data);
2555
2556 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2557 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2558 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2559 if (orig != data)
2560 WREG32(mmCP_MEM_SLP_CNTL, data);
2561 }
2562
2563 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2564 data &= 0xffffffc0;
2565 if (orig != data)
2566 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2567
2568 tmp = gfx_v6_0_halt_rlc(adev);
2569
2570 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2571 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2572 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2573
2574 gfx_v6_0_update_rlc(adev, tmp);
2575 } else {
2576 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2577 data |= 0x00000003;
2578 if (orig != data)
2579 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2580
2581 data = RREG32(mmCP_MEM_SLP_CNTL);
2582 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2583 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2584 WREG32(mmCP_MEM_SLP_CNTL, data);
2585 }
2586 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2587 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2588 if (orig != data)
2589 WREG32(mmCGTS_SM_CTRL_REG, data);
2590
2591 tmp = gfx_v6_0_halt_rlc(adev);
2592
2593 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2594 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2595 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2596
2597 gfx_v6_0_update_rlc(adev, tmp);
2598 }
2599}
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2617 bool enable)
2618{
2619}
2620
2621static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2622 bool enable)
2623{
2624}
2625
2626static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2627{
2628 u32 data, orig;
2629
2630 orig = data = RREG32(mmRLC_PG_CNTL);
2631 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2632 data &= ~0x8000;
2633 else
2634 data |= 0x8000;
2635 if (orig != data)
2636 WREG32(mmRLC_PG_CNTL, data);
2637}
2638
2639static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2640{
2641}
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
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2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2711 bool enable)
2712{
2713 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2714 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2715 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2716 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2717 } else {
2718 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2719 (void)RREG32(mmDB_RENDER_CONTROL);
2720 }
2721}
2722
2723static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2724{
2725 u32 tmp;
2726
2727 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2728
2729 tmp = RREG32(mmRLC_MAX_PG_CU);
2730 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2731 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2732 WREG32(mmRLC_MAX_PG_CU, tmp);
2733}
2734
2735static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2736 bool enable)
2737{
2738 u32 data, orig;
2739
2740 orig = data = RREG32(mmRLC_PG_CNTL);
2741 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2742 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2743 else
2744 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2745 if (orig != data)
2746 WREG32(mmRLC_PG_CNTL, data);
2747}
2748
2749static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2750 bool enable)
2751{
2752 u32 data, orig;
2753
2754 orig = data = RREG32(mmRLC_PG_CNTL);
2755 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2756 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2757 else
2758 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2759 if (orig != data)
2760 WREG32(mmRLC_PG_CNTL, data);
2761}
2762
2763static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2764{
2765 u32 tmp;
2766
2767 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2768 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2769 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2770
2771 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2772 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2773 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2774 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2775 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2776}
2777
2778static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2779{
2780 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2781 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2782 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2783}
2784
2785static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2786{
2787 u32 count = 0;
2788 const struct cs_section_def *sect = NULL;
2789 const struct cs_extent_def *ext = NULL;
2790
2791 if (adev->gfx.rlc.cs_data == NULL)
2792 return 0;
2793
2794
2795 count += 2;
2796
2797 count += 3;
2798
2799 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2800 for (ext = sect->section; ext->extent != NULL; ++ext) {
2801 if (sect->id == SECT_CONTEXT)
2802 count += 2 + ext->reg_count;
2803 else
2804 return 0;
2805 }
2806 }
2807
2808 count += 3;
2809
2810 count += 2;
2811
2812 count += 2;
2813
2814 return count;
2815}
2816
2817static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2818 volatile u32 *buffer)
2819{
2820 u32 count = 0, i;
2821 const struct cs_section_def *sect = NULL;
2822 const struct cs_extent_def *ext = NULL;
2823
2824 if (adev->gfx.rlc.cs_data == NULL)
2825 return;
2826 if (buffer == NULL)
2827 return;
2828
2829 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2830 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2831 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2832 buffer[count++] = cpu_to_le32(0x80000000);
2833 buffer[count++] = cpu_to_le32(0x80000000);
2834
2835 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2836 for (ext = sect->section; ext->extent != NULL; ++ext) {
2837 if (sect->id == SECT_CONTEXT) {
2838 buffer[count++] =
2839 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2840 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2841 for (i = 0; i < ext->reg_count; i++)
2842 buffer[count++] = cpu_to_le32(ext->extent[i]);
2843 } else {
2844 return;
2845 }
2846 }
2847 }
2848
2849 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2850 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2851
2852 switch (adev->asic_type) {
2853 case CHIP_TAHITI:
2854 case CHIP_PITCAIRN:
2855 buffer[count++] = cpu_to_le32(0x2a00126a);
2856 break;
2857 case CHIP_VERDE:
2858 buffer[count++] = cpu_to_le32(0x0000124a);
2859 break;
2860 case CHIP_OLAND:
2861 buffer[count++] = cpu_to_le32(0x00000082);
2862 break;
2863 case CHIP_HAINAN:
2864 buffer[count++] = cpu_to_le32(0x00000000);
2865 break;
2866 default:
2867 buffer[count++] = cpu_to_le32(0x00000000);
2868 break;
2869 }
2870
2871 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2872 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2873
2874 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2875 buffer[count++] = cpu_to_le32(0);
2876}
2877
2878static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2879{
2880 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2881 AMD_PG_SUPPORT_GFX_SMG |
2882 AMD_PG_SUPPORT_GFX_DMG |
2883 AMD_PG_SUPPORT_CP |
2884 AMD_PG_SUPPORT_GDS |
2885 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2886 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2887 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2888 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2889 gfx_v6_0_init_gfx_cgpg(adev);
2890 gfx_v6_0_enable_cp_pg(adev, true);
2891 gfx_v6_0_enable_gds_pg(adev, true);
2892 } else {
2893 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2894 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2895
2896 }
2897 gfx_v6_0_init_ao_cu_mask(adev);
2898 gfx_v6_0_update_gfx_pg(adev, true);
2899 } else {
2900
2901 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2902 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2903 }
2904}
2905
2906static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2907{
2908 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2909 AMD_PG_SUPPORT_GFX_SMG |
2910 AMD_PG_SUPPORT_GFX_DMG |
2911 AMD_PG_SUPPORT_CP |
2912 AMD_PG_SUPPORT_GDS |
2913 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2914 gfx_v6_0_update_gfx_pg(adev, false);
2915 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2916 gfx_v6_0_enable_cp_pg(adev, false);
2917 gfx_v6_0_enable_gds_pg(adev, false);
2918 }
2919 }
2920}
2921
2922static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2923{
2924 uint64_t clock;
2925
2926 mutex_lock(&adev->gfx.gpu_clock_mutex);
2927 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2928 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2929 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2930 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2931 return clock;
2932}
2933
2934static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2935{
2936 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2937 gfx_v6_0_ring_emit_vgt_flush(ring);
2938 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2939 amdgpu_ring_write(ring, 0x80000000);
2940 amdgpu_ring_write(ring, 0);
2941}
2942
2943
2944static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2945{
2946 WREG32(mmSQ_IND_INDEX,
2947 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2948 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2949 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2950 (SQ_IND_INDEX__FORCE_READ_MASK));
2951 return RREG32(mmSQ_IND_DATA);
2952}
2953
2954static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2955 uint32_t wave, uint32_t thread,
2956 uint32_t regno, uint32_t num, uint32_t *out)
2957{
2958 WREG32(mmSQ_IND_INDEX,
2959 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2960 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2961 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2962 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2963 (SQ_IND_INDEX__FORCE_READ_MASK) |
2964 (SQ_IND_INDEX__AUTO_INCR_MASK));
2965 while (num--)
2966 *(out++) = RREG32(mmSQ_IND_DATA);
2967}
2968
2969static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2970{
2971
2972 dst[(*no_fields)++] = 0;
2973 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
2985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
2986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
2987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
2988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2991}
2992
2993static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
2994 uint32_t wave, uint32_t start,
2995 uint32_t size, uint32_t *dst)
2996{
2997 wave_read_regs(
2998 adev, simd, wave, 0,
2999 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3000}
3001
3002static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3003 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3004 .select_se_sh = &gfx_v6_0_select_se_sh,
3005 .read_wave_data = &gfx_v6_0_read_wave_data,
3006 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3007};
3008
3009static int gfx_v6_0_early_init(void *handle)
3010{
3011 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3012
3013 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3014 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3015 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3016 gfx_v6_0_set_ring_funcs(adev);
3017 gfx_v6_0_set_irq_funcs(adev);
3018
3019 return 0;
3020}
3021
3022static int gfx_v6_0_sw_init(void *handle)
3023{
3024 struct amdgpu_ring *ring;
3025 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3026 int i, r;
3027
3028 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3029 if (r)
3030 return r;
3031
3032 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3033 if (r)
3034 return r;
3035
3036 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3037 if (r)
3038 return r;
3039
3040 gfx_v6_0_scratch_init(adev);
3041
3042 r = gfx_v6_0_init_microcode(adev);
3043 if (r) {
3044 DRM_ERROR("Failed to load gfx firmware!\n");
3045 return r;
3046 }
3047
3048 r = gfx_v6_0_rlc_init(adev);
3049 if (r) {
3050 DRM_ERROR("Failed to init rlc BOs!\n");
3051 return r;
3052 }
3053
3054 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3055 ring = &adev->gfx.gfx_ring[i];
3056 ring->ring_obj = NULL;
3057 sprintf(ring->name, "gfx");
3058 r = amdgpu_ring_init(adev, ring, 1024,
3059 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3060 if (r)
3061 return r;
3062 }
3063
3064 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3065 unsigned irq_type;
3066
3067 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3068 DRM_ERROR("Too many (%d) compute rings!\n", i);
3069 break;
3070 }
3071 ring = &adev->gfx.compute_ring[i];
3072 ring->ring_obj = NULL;
3073 ring->use_doorbell = false;
3074 ring->doorbell_index = 0;
3075 ring->me = 1;
3076 ring->pipe = i;
3077 ring->queue = i;
3078 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3079 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3080 r = amdgpu_ring_init(adev, ring, 1024,
3081 &adev->gfx.eop_irq, irq_type);
3082 if (r)
3083 return r;
3084 }
3085
3086 return r;
3087}
3088
3089static int gfx_v6_0_sw_fini(void *handle)
3090{
3091 int i;
3092 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3093
3094 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3095 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3096 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3097 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3098
3099 gfx_v6_0_rlc_fini(adev);
3100
3101 return 0;
3102}
3103
3104static int gfx_v6_0_hw_init(void *handle)
3105{
3106 int r;
3107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3108
3109 gfx_v6_0_gpu_init(adev);
3110
3111 r = gfx_v6_0_rlc_resume(adev);
3112 if (r)
3113 return r;
3114
3115 r = gfx_v6_0_cp_resume(adev);
3116 if (r)
3117 return r;
3118
3119 adev->gfx.ce_ram_size = 0x8000;
3120
3121 return r;
3122}
3123
3124static int gfx_v6_0_hw_fini(void *handle)
3125{
3126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3127
3128 gfx_v6_0_cp_enable(adev, false);
3129 gfx_v6_0_rlc_stop(adev);
3130 gfx_v6_0_fini_pg(adev);
3131
3132 return 0;
3133}
3134
3135static int gfx_v6_0_suspend(void *handle)
3136{
3137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3138
3139 return gfx_v6_0_hw_fini(adev);
3140}
3141
3142static int gfx_v6_0_resume(void *handle)
3143{
3144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3145
3146 return gfx_v6_0_hw_init(adev);
3147}
3148
3149static bool gfx_v6_0_is_idle(void *handle)
3150{
3151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3152
3153 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3154 return false;
3155 else
3156 return true;
3157}
3158
3159static int gfx_v6_0_wait_for_idle(void *handle)
3160{
3161 unsigned i;
3162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3163
3164 for (i = 0; i < adev->usec_timeout; i++) {
3165 if (gfx_v6_0_is_idle(handle))
3166 return 0;
3167 udelay(1);
3168 }
3169 return -ETIMEDOUT;
3170}
3171
3172static int gfx_v6_0_soft_reset(void *handle)
3173{
3174 return 0;
3175}
3176
3177static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3178 enum amdgpu_interrupt_state state)
3179{
3180 u32 cp_int_cntl;
3181
3182 switch (state) {
3183 case AMDGPU_IRQ_STATE_DISABLE:
3184 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3185 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3186 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3187 break;
3188 case AMDGPU_IRQ_STATE_ENABLE:
3189 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3190 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3191 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3192 break;
3193 default:
3194 break;
3195 }
3196}
3197
3198static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3199 int ring,
3200 enum amdgpu_interrupt_state state)
3201{
3202 u32 cp_int_cntl;
3203 switch (state){
3204 case AMDGPU_IRQ_STATE_DISABLE:
3205 if (ring == 0) {
3206 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3207 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3208 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3209 break;
3210 } else {
3211 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3212 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3213 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3214 break;
3215
3216 }
3217 case AMDGPU_IRQ_STATE_ENABLE:
3218 if (ring == 0) {
3219 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3220 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3221 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3222 break;
3223 } else {
3224 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3225 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3226 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3227 break;
3228
3229 }
3230
3231 default:
3232 BUG();
3233 break;
3234
3235 }
3236}
3237
3238static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3239 struct amdgpu_irq_src *src,
3240 unsigned type,
3241 enum amdgpu_interrupt_state state)
3242{
3243 u32 cp_int_cntl;
3244
3245 switch (state) {
3246 case AMDGPU_IRQ_STATE_DISABLE:
3247 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3248 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3249 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3250 break;
3251 case AMDGPU_IRQ_STATE_ENABLE:
3252 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3253 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3254 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3255 break;
3256 default:
3257 break;
3258 }
3259
3260 return 0;
3261}
3262
3263static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3264 struct amdgpu_irq_src *src,
3265 unsigned type,
3266 enum amdgpu_interrupt_state state)
3267{
3268 u32 cp_int_cntl;
3269
3270 switch (state) {
3271 case AMDGPU_IRQ_STATE_DISABLE:
3272 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3273 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3274 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3275 break;
3276 case AMDGPU_IRQ_STATE_ENABLE:
3277 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3278 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3279 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3280 break;
3281 default:
3282 break;
3283 }
3284
3285 return 0;
3286}
3287
3288static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3289 struct amdgpu_irq_src *src,
3290 unsigned type,
3291 enum amdgpu_interrupt_state state)
3292{
3293 switch (type) {
3294 case AMDGPU_CP_IRQ_GFX_EOP:
3295 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3296 break;
3297 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3298 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3299 break;
3300 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3301 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3302 break;
3303 default:
3304 break;
3305 }
3306 return 0;
3307}
3308
3309static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3310 struct amdgpu_irq_src *source,
3311 struct amdgpu_iv_entry *entry)
3312{
3313 switch (entry->ring_id) {
3314 case 0:
3315 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3316 break;
3317 case 1:
3318 case 2:
3319 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3320 break;
3321 default:
3322 break;
3323 }
3324 return 0;
3325}
3326
3327static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3328 struct amdgpu_irq_src *source,
3329 struct amdgpu_iv_entry *entry)
3330{
3331 DRM_ERROR("Illegal register access in command stream\n");
3332 schedule_work(&adev->reset_work);
3333 return 0;
3334}
3335
3336static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3337 struct amdgpu_irq_src *source,
3338 struct amdgpu_iv_entry *entry)
3339{
3340 DRM_ERROR("Illegal instruction in command stream\n");
3341 schedule_work(&adev->reset_work);
3342 return 0;
3343}
3344
3345static int gfx_v6_0_set_clockgating_state(void *handle,
3346 enum amd_clockgating_state state)
3347{
3348 bool gate = false;
3349 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3350
3351 if (state == AMD_CG_STATE_GATE)
3352 gate = true;
3353
3354 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3355 if (gate) {
3356 gfx_v6_0_enable_mgcg(adev, true);
3357 gfx_v6_0_enable_cgcg(adev, true);
3358 } else {
3359 gfx_v6_0_enable_cgcg(adev, false);
3360 gfx_v6_0_enable_mgcg(adev, false);
3361 }
3362 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3363
3364 return 0;
3365}
3366
3367static int gfx_v6_0_set_powergating_state(void *handle,
3368 enum amd_powergating_state state)
3369{
3370 bool gate = false;
3371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3372
3373 if (state == AMD_PG_STATE_GATE)
3374 gate = true;
3375
3376 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3377 AMD_PG_SUPPORT_GFX_SMG |
3378 AMD_PG_SUPPORT_GFX_DMG |
3379 AMD_PG_SUPPORT_CP |
3380 AMD_PG_SUPPORT_GDS |
3381 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3382 gfx_v6_0_update_gfx_pg(adev, gate);
3383 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3384 gfx_v6_0_enable_cp_pg(adev, gate);
3385 gfx_v6_0_enable_gds_pg(adev, gate);
3386 }
3387 }
3388
3389 return 0;
3390}
3391
3392static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3393 .name = "gfx_v6_0",
3394 .early_init = gfx_v6_0_early_init,
3395 .late_init = NULL,
3396 .sw_init = gfx_v6_0_sw_init,
3397 .sw_fini = gfx_v6_0_sw_fini,
3398 .hw_init = gfx_v6_0_hw_init,
3399 .hw_fini = gfx_v6_0_hw_fini,
3400 .suspend = gfx_v6_0_suspend,
3401 .resume = gfx_v6_0_resume,
3402 .is_idle = gfx_v6_0_is_idle,
3403 .wait_for_idle = gfx_v6_0_wait_for_idle,
3404 .soft_reset = gfx_v6_0_soft_reset,
3405 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3406 .set_powergating_state = gfx_v6_0_set_powergating_state,
3407};
3408
3409static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3410 .type = AMDGPU_RING_TYPE_GFX,
3411 .align_mask = 0xff,
3412 .nop = 0x80000000,
3413 .support_64bit_ptrs = false,
3414 .get_rptr = gfx_v6_0_ring_get_rptr,
3415 .get_wptr = gfx_v6_0_ring_get_wptr,
3416 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3417 .emit_frame_size =
3418 5 +
3419 5 +
3420 14 + 14 + 14 +
3421 7 + 4 +
3422 17 + 6 +
3423 3 + 2,
3424 .emit_ib_size = 6,
3425 .emit_ib = gfx_v6_0_ring_emit_ib,
3426 .emit_fence = gfx_v6_0_ring_emit_fence,
3427 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3428 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3429 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3430 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3431 .test_ring = gfx_v6_0_ring_test_ring,
3432 .test_ib = gfx_v6_0_ring_test_ib,
3433 .insert_nop = amdgpu_ring_insert_nop,
3434 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3435};
3436
3437static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3438 .type = AMDGPU_RING_TYPE_COMPUTE,
3439 .align_mask = 0xff,
3440 .nop = 0x80000000,
3441 .get_rptr = gfx_v6_0_ring_get_rptr,
3442 .get_wptr = gfx_v6_0_ring_get_wptr,
3443 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3444 .emit_frame_size =
3445 5 +
3446 5 +
3447 7 +
3448 17 +
3449 14 + 14 + 14,
3450 .emit_ib_size = 6,
3451 .emit_ib = gfx_v6_0_ring_emit_ib,
3452 .emit_fence = gfx_v6_0_ring_emit_fence,
3453 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3454 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3455 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3456 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3457 .test_ring = gfx_v6_0_ring_test_ring,
3458 .test_ib = gfx_v6_0_ring_test_ib,
3459 .insert_nop = amdgpu_ring_insert_nop,
3460};
3461
3462static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3463{
3464 int i;
3465
3466 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3467 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3468 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3469 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3470}
3471
3472static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3473 .set = gfx_v6_0_set_eop_interrupt_state,
3474 .process = gfx_v6_0_eop_irq,
3475};
3476
3477static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3478 .set = gfx_v6_0_set_priv_reg_fault_state,
3479 .process = gfx_v6_0_priv_reg_irq,
3480};
3481
3482static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3483 .set = gfx_v6_0_set_priv_inst_fault_state,
3484 .process = gfx_v6_0_priv_inst_irq,
3485};
3486
3487static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3488{
3489 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3490 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3491
3492 adev->gfx.priv_reg_irq.num_types = 1;
3493 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3494
3495 adev->gfx.priv_inst_irq.num_types = 1;
3496 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3497}
3498
3499static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3500{
3501 int i, j, k, counter, active_cu_number = 0;
3502 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3503 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3504 unsigned disable_masks[4 * 2];
3505 u32 ao_cu_num;
3506
3507 if (adev->flags & AMD_IS_APU)
3508 ao_cu_num = 2;
3509 else
3510 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3511
3512 memset(cu_info, 0, sizeof(*cu_info));
3513
3514 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3515
3516 mutex_lock(&adev->grbm_idx_mutex);
3517 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3518 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3519 mask = 1;
3520 ao_bitmap = 0;
3521 counter = 0;
3522 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3523 if (i < 4 && j < 2)
3524 gfx_v6_0_set_user_cu_inactive_bitmap(
3525 adev, disable_masks[i * 2 + j]);
3526 bitmap = gfx_v6_0_get_cu_enabled(adev);
3527 cu_info->bitmap[i][j] = bitmap;
3528
3529 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3530 if (bitmap & mask) {
3531 if (counter < ao_cu_num)
3532 ao_bitmap |= mask;
3533 counter ++;
3534 }
3535 mask <<= 1;
3536 }
3537 active_cu_number += counter;
3538 if (i < 2 && j < 2)
3539 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3540 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3541 }
3542 }
3543
3544 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3545 mutex_unlock(&adev->grbm_idx_mutex);
3546
3547 cu_info->number = active_cu_number;
3548 cu_info->ao_cu_mask = ao_cu_mask;
3549}
3550
3551const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3552{
3553 .type = AMD_IP_BLOCK_TYPE_GFX,
3554 .major = 6,
3555 .minor = 0,
3556 .rev = 0,
3557 .funcs = &gfx_v6_0_ip_funcs,
3558};
3559
