1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef _PSP_TEE_GFX_IF_H_ 25#define _PSP_TEE_GFX_IF_H_ 26 27#define PSP_GFX_CMD_BUF_VERSION 0x00000001 28 29#define GFX_CMD_STATUS_MASK 0x0000FFFF 30#define GFX_CMD_ID_MASK 0x000F0000 31#define GFX_CMD_RESERVED_MASK 0x7FF00000 32#define GFX_CMD_RESPONSE_MASK 0x80000000 33 34/* TEE Gfx Command IDs for the register interface. 35* Command ID must be between 0x00010000 and 0x000F0000. 36*/ 37enum psp_gfx_crtl_cmd_id 38{ 39 GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ 40 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ 41 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ 42 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ 43 44 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ 45}; 46 47 48/* Control registers of the TEE Gfx interface. These are located in 49* SRBM-to-PSP mailbox registers (total 8 registers). 50*/ 51struct psp_gfx_ctrl 52{ 53 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */ 54 volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */ 55 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */ 56 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ 57 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ 58 volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of physical address of ring buffer */ 59 volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of physical address of ring buffer */ 60 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */ 61 62}; 63 64 65/* Response flag is set in the command when command is completed by PSP. 66* Used in the GFX_CTRL.CmdResp. 67* When PSP GFX I/F is initialized, the flag is set. 68*/ 69#define GFX_FLAG_RESPONSE 0x80000000 70 71 72/* TEE Gfx Command IDs for the ring buffer interface. */ 73enum psp_gfx_cmd_id 74{ 75 GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ 76 GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ 77 GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ 78 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ 79 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ 80 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ 81 82}; 83 84 85/* Command to load Trusted Application binary into PSP OS. */ 86struct psp_gfx_cmd_load_ta 87{ 88 uint32_t app_phy_addr_lo; /* bits [31:0] of the physical address of the TA binary (must be 4 KB aligned) */ 89 uint32_t app_phy_addr_hi; /* bits [63:32] of the physical address of the TA binary */ 90 uint32_t app_len; /* length of the TA binary in bytes */ 91 uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the physical address of CMD buffer (must be 4 KB aligned) */ 92 uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the physical address of CMD buffer */ 93 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ 94 95 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided 96 * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead 97 * of using global persistent buffer. 98 */ 99}; 100 101 102/* Command to Unload Trusted Application binary from PSP OS. */ 103struct psp_gfx_cmd_unload_ta 104{ 105 uint32_t session_id; /* Session ID of the loaded TA to be unloaded */ 106 107}; 108 109 110/* Shared buffers for InvokeCommand. 111*/ 112struct psp_gfx_buf_desc 113{ 114 uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of the buffer (must be 4 KB aligned) */ 115 uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of the buffer */ 116 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ 117 118}; 119 120/* Max number of descriptors for one shared buffer (in how many different 121* physical locations one shared buffer can be stored). If buffer is too much 122* fragmented, error will be returned. 123*/ 124#define GFX_BUF_MAX_DESC 64 125 126struct psp_gfx_buf_list 127{ 128 uint32_t num_desc; /* number of buffer descriptors in the list */ 129 uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ 130 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ 131 132 /* total 776 bytes */ 133}; 134 135/* Command to execute InvokeCommand entry point of the TA. */ 136struct psp_gfx_cmd_invoke_cmd 137{ 138 uint32_t session_id; /* Session ID of the TA to be executed */ 139 uint32_t ta_cmd_id; /* Command ID to be sent to TA */ 140 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ 141 142}; 143 144 145/* Command to setup TMR region. */ 146struct psp_gfx_cmd_setup_tmr 147{ 148 uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of TMR buffer (must be 4 KB aligned) */ 149 uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of TMR buffer */ 150 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ 151 152}; 153 154 155/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ 156enum psp_gfx_fw_type 157{ 158 GFX_FW_TYPE_NONE = 0, 159 GFX_FW_TYPE_CP_ME = 1, 160 GFX_FW_TYPE_CP_PFP = 2, 161 GFX_FW_TYPE_CP_CE = 3, 162 GFX_FW_TYPE_CP_MEC = 4, 163 GFX_FW_TYPE_CP_MEC_ME1 = 5, 164 GFX_FW_TYPE_CP_MEC_ME2 = 6, 165 GFX_FW_TYPE_RLC_V = 7, 166 GFX_FW_TYPE_RLC_G = 8, 167 GFX_FW_TYPE_SDMA0 = 9, 168 GFX_FW_TYPE_SDMA1 = 10, 169 GFX_FW_TYPE_DMCU_ERAM = 11, 170 GFX_FW_TYPE_DMCU_ISR = 12, 171 GFX_FW_TYPE_VCN = 13, 172 GFX_FW_TYPE_UVD = 14, 173 GFX_FW_TYPE_VCE = 15, 174 GFX_FW_TYPE_ISP = 16, 175 GFX_FW_TYPE_ACP = 17, 176 GFX_FW_TYPE_SMU = 18, 177}; 178 179/* Command to load HW IP FW. */ 180struct psp_gfx_cmd_load_ip_fw 181{ 182 uint32_t fw_phy_addr_lo; /* bits [31:0] of physical address of FW location (must be 4 KB aligned) */ 183 uint32_t fw_phy_addr_hi; /* bits [63:32] of physical address of FW location */ 184 uint32_t fw_size; /* FW buffer size in bytes */ 185 enum psp_gfx_fw_type fw_type; /* FW type */ 186 187}; 188 189 190/* All GFX ring buffer commands. */ 191union psp_gfx_commands 192{ 193 struct psp_gfx_cmd_load_ta cmd_load_ta; 194 struct psp_gfx_cmd_unload_ta cmd_unload_ta; 195 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; 196 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; 197 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; 198 199}; 200 201 202/* Structure of GFX Response buffer. 203* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI 204* it is separate buffer. 205*/ 206struct psp_gfx_resp 207{ 208 uint32_t status; /* +0 status of command execution */ 209 uint32_t session_id; /* +4 session ID in response to LoadTa command */ 210 uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ 211 uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ 212 213 uint32_t reserved[4]; 214 215 /* total 32 bytes */ 216}; 217 218/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi 219* and psp_gfx_rb_frame.cmd_buf_addr_lo. 220*/ 221struct psp_gfx_cmd_resp 222{ 223 uint32_t buf_size; /* +0 total size of the buffer in bytes */ 224 uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ 225 uint32_t cmd_id; /* +8 command ID */ 226 227 /* These fields are used for RBI only. They are all 0 in GPCOM commands 228 */ 229 uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of physical address of response buffer (must be 4 KB aligned) */ 230 uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of physical address of response buffer */ 231 uint32_t resp_offset; /* +20 offset within response buffer */ 232 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */ 233 234 union psp_gfx_commands cmd; /* +28 command specific structures */ 235 236 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; 237 238 /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response 239 * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. 240 */ 241 struct psp_gfx_resp resp; /* +864 response */ 242 243 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; 244 245 /* total size 1024 bytes */ 246}; 247 248 249#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ 250 251/* Structure of the Ring Buffer Frame */ 252struct psp_gfx_rb_frame 253{ 254 uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of physical address of command buffer (must be 4 KB aligned) */ 255 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of physical address of command buffer */ 256 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */ 257 uint32_t fence_addr_lo; /* +12 bits [31:0] of physical address of Fence for this frame */ 258 uint32_t fence_addr_hi; /* +16 bits [63:32] of physical address of Fence for this frame */ 259 uint32_t fence_value; /* +20 Fence value */ 260 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ 261 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ 262 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */ 263 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ 264 uint8_t reserved1[2]; /* +34 reserved, must be 0 */ 265 uint32_t reserved2[7]; /* +40 reserved, must be 0 */ 266 /* total 64 bytes */ 267}; 268 269#endif /* _PSP_TEE_GFX_IF_H_ */ 270