LXR linux/drivers/gpu/drm/amd/amdgpu/psp_v10

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Author: Huang Rui
  23 *
  24 */
  25
  26#include <linux/firmware.h>
  27#include "amdgpu.h"
  28#include "amdgpu_psp.h"
  29#include "amdgpu_ucode.h"
  30#include "soc15_common.h"
  31#include "psp_v10_0.h"
  32
  33#include "vega10/soc15ip.h"
  34#include "raven1/MP/mp_10_0_offset.h"
  35#include "raven1/GC/gc_9_1_offset.h"
  36#include "raven1/SDMA0/sdma0_4_1_offset.h"
  37
  38static int
  39psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
  40{
  41        switch(ucode->ucode_id) {
  42        case AMDGPU_UCODE_ID_SDMA0:
  43                *type = GFX_FW_TYPE_SDMA0;
  44                break;
  45        case AMDGPU_UCODE_ID_SDMA1:
  46                *type = GFX_FW_TYPE_SDMA1;
  47                break;
  48        case AMDGPU_UCODE_ID_CP_CE:
  49                *type = GFX_FW_TYPE_CP_CE;
  50                break;
  51        case AMDGPU_UCODE_ID_CP_PFP:
  52                *type = GFX_FW_TYPE_CP_PFP;
  53                break;
  54        case AMDGPU_UCODE_ID_CP_ME:
  55                *type = GFX_FW_TYPE_CP_ME;
  56                break;
  57        case AMDGPU_UCODE_ID_CP_MEC1:
  58                *type = GFX_FW_TYPE_CP_MEC;
  59                break;
  60        case AMDGPU_UCODE_ID_CP_MEC1_JT:
  61                *type = GFX_FW_TYPE_CP_MEC_ME1;
  62                break;
  63        case AMDGPU_UCODE_ID_CP_MEC2:
  64                *type = GFX_FW_TYPE_CP_MEC;
  65                break;
  66        case AMDGPU_UCODE_ID_CP_MEC2_JT:
  67                *type = GFX_FW_TYPE_CP_MEC_ME2;
  68                break;
  69        case AMDGPU_UCODE_ID_RLC_G:
  70                *type = GFX_FW_TYPE_RLC_G;
  71                break;
  72        case AMDGPU_UCODE_ID_SMC:
  73                *type = GFX_FW_TYPE_SMU;
  74                break;
  75        case AMDGPU_UCODE_ID_UVD:
  76                *type = GFX_FW_TYPE_UVD;
  77                break;
  78        case AMDGPU_UCODE_ID_VCE:
  79                *type = GFX_FW_TYPE_VCE;
  80                break;
  81        case AMDGPU_UCODE_ID_MAXIMUM:
  82        default:
  83                return -EINVAL;
  84        }
  85
  86        return 0;
  87}
  88
  89int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
  90{
  91        int ret;
  92        uint64_t fw_mem_mc_addr = ucode->mc_addr;
  93        struct  common_firmware_header *header;
  94
  95        memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
  96        header = (struct common_firmware_header *)ucode->fw;
  97
  98        cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
  99        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 100        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 101        cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
 102
 103        ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 104        if (ret)
 105                DRM_ERROR("Unknown firmware type\n");
 106
 107        return ret;
 108}
 109
 110int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
 111{
 112        int ret = 0;
 113        unsigned int psp_ring_reg = 0;
 114        struct psp_ring *ring;
 115        struct amdgpu_device *adev = psp->adev;
 116
 117        ring = &psp->km_ring;
 118
 119        ring->ring_type = ring_type;
 120
 121        /* allocate 4k Page of Local Frame Buffer memory for ring */
 122        ring->ring_size = 0x1000;
 123        ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 124                                      AMDGPU_GEM_DOMAIN_VRAM,
 125                                      &adev->firmware.rbuf,
 126                                      &ring->ring_mem_mc_addr,
 127                                      (void **)&ring->ring_mem);
 128        if (ret) {
 129                ring->ring_size = 0;
 130                return ret;
 131        }
 132
 133        /* Write low address of the ring to C2PMSG_69 */
 134        psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 135        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 136        /* Write high address of the ring to C2PMSG_70 */
 137        psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 138        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 139        /* Write size of ring to C2PMSG_71 */
 140        psp_ring_reg = ring->ring_size;
 141        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 142        /* Write the ring initialization command to C2PMSG_64 */
 143        psp_ring_reg = ring_type;
 144        psp_ring_reg = psp_ring_reg << 16;
 145        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 146        /* Wait for response flag (bit 31) in C2PMSG_64 */
 147        psp_ring_reg = 0;
 148        while ((psp_ring_reg & 0x80000000) == 0) {
 149                psp_ring_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64);
 150        }
 151
 152        return 0;
 153}
 154
 155int psp_v10_0_cmd_submit(struct psp_context *psp,
 156                        struct amdgpu_firmware_info *ucode,
 157                        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 158                        int index)
 159{
 160        unsigned int psp_write_ptr_reg = 0;
 161        struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 162        struct psp_ring *ring = &psp->km_ring;
 163        struct amdgpu_device *adev = psp->adev;
 164
 165        /* KM (GPCOM) prepare write pointer */
 166        psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 167
 168        /* Update KM RB frame pointer to new frame */
 169        if ((psp_write_ptr_reg % ring->ring_size) == 0)
 170                write_frame = ring->ring_mem;
 171        else
 172                write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
 173
 174        /* Update KM RB frame */
 175        write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 176        write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 177        write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 178        write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 179        write_frame->fence_value = index;
 180
 181        /* Update the write Pointer in DWORDs */
 182        psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
 183        psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
 184        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 185
 186        return 0;
 187}
 188
 189static int
 190psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 191                  unsigned int *sram_data_reg_offset,
 192                  enum AMDGPU_UCODE_ID ucode_id)
 193{
 194        int ret = 0;
 195
 196        switch(ucode_id) {
 197/* TODO: needs to confirm */
 198#if 0
 199        case AMDGPU_UCODE_ID_SMC:
 200                *sram_offset = 0;
 201                *sram_addr_reg_offset = 0;
 202                *sram_data_reg_offset = 0;
 203                break;
 204#endif
 205
 206        case AMDGPU_UCODE_ID_CP_CE:
 207                *sram_offset = 0x0;
 208                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 209                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 210                break;
 211
 212        case AMDGPU_UCODE_ID_CP_PFP:
 213                *sram_offset = 0x0;
 214                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 215                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 216                break;
 217
 218        case AMDGPU_UCODE_ID_CP_ME:
 219                *sram_offset = 0x0;
 220                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 221                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 222                break;
 223
 224        case AMDGPU_UCODE_ID_CP_MEC1:
 225                *sram_offset = 0x10000;
 226                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 227                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 228                break;
 229
 230        case AMDGPU_UCODE_ID_CP_MEC2:
 231                *sram_offset = 0x10000;
 232                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 233                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 234                break;
 235
 236        case AMDGPU_UCODE_ID_RLC_G:
 237                *sram_offset = 0x2000;
 238                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 239                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 240                break;
 241
 242        case AMDGPU_UCODE_ID_SDMA0:
 243                *sram_offset = 0x0;
 244                *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 245                *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 246                break;
 247
 248/* TODO: needs to confirm */
 249#if 0
 250        case AMDGPU_UCODE_ID_SDMA1:
 251                *sram_offset = ;
 252                *sram_addr_reg_offset = ;
 253                break;
 254
 255        case AMDGPU_UCODE_ID_UVD:
 256                *sram_offset = ;
 257                *sram_addr_reg_offset = ;
 258                break;
 259
 260        case AMDGPU_UCODE_ID_VCE:
 261                *sram_offset = ;
 262                *sram_addr_reg_offset = ;
 263                break;
 264#endif
 265
 266        case AMDGPU_UCODE_ID_MAXIMUM:
 267        default:
 268                ret = -EINVAL;
 269                break;
 270        }
 271
 272        return ret;
 273}
 274
 275bool psp_v10_0_compare_sram_data(struct psp_context *psp,
 276                                struct amdgpu_firmware_info *ucode,
 277                                enum AMDGPU_UCODE_ID ucode_type)
 278{
 279        int err = 0;
 280        unsigned int fw_sram_reg_val = 0;
 281        unsigned int fw_sram_addr_reg_offset = 0;
 282        unsigned int fw_sram_data_reg_offset = 0;
 283        unsigned int ucode_size;
 284        uint32_t *ucode_mem = NULL;
 285        struct amdgpu_device *adev = psp->adev;
 286
 287        err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
 288                                &fw_sram_data_reg_offset, ucode_type);
 289        if (err)
 290                return false;
 291
 292        WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 293
 294        ucode_size = ucode->ucode_size;
 295        ucode_mem = (uint32_t *)ucode->kaddr;
 296        while (!ucode_size) {
 297                fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 298
 299                if (*ucode_mem != fw_sram_reg_val)
 300                        return false;
 301
 302                ucode_mem++;
 303                /* 4 bytes */
 304                ucode_size -= 4;
 305        }
 306
 307        return true;
 308}
 309