1/* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef UVD_4_0_D_H 24#define UVD_4_0_D_H 25 26#define ixUVD_CGC_CTRL2 0x00C1 27#define ixUVD_CGC_MEM_CTRL 0x00C0 28#define ixUVD_LMI_ADDR_EXT2 0x00AB 29#define ixUVD_LMI_CACHE_CTRL 0x009B 30#define ixUVD_LMI_SWAP_CNTL2 0x00AA 31#define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048 32#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114 33#define ixUVD_MIF_REF_ADDR_CONFIG 0x004C 34#define mmUVD_CGC_CTRL 0x3D2C 35#define mmUVD_CGC_GATE 0x3D2A 36#define mmUVD_CGC_STATUS 0x3D2B 37#define mmUVD_CGC_UDEC_STATUS 0x3D2D 38#define mmUVD_CONTEXT_ID 0x3DBD 39#define mmUVD_CTX_DATA 0x3D29 40#define mmUVD_CTX_INDEX 0x3D28 41#define mmUVD_ENGINE_CNTL 0x3BC6 42#define mmUVD_GPCOM_VCPU_CMD 0x3BC3 43#define mmUVD_GPCOM_VCPU_DATA0 0x3BC4 44#define mmUVD_GPCOM_VCPU_DATA1 0x3BC5 45#define mmUVD_GP_SCRATCH4 0x3D38 46#define mmUVD_LMI_ADDR_EXT 0x3D65 47#define mmUVD_LMI_CTRL 0x3D66 48#define mmUVD_LMI_CTRL2 0x3D3D 49#define mmUVD_LMI_EXT40_ADDR 0x3D26 50#define mmUVD_LMI_STATUS 0x3D67 51#define mmUVD_LMI_SWAP_CNTL 0x3D6D 52#define mmUVD_MASTINT_EN 0x3D40 53#define mmUVD_MPC_CNTL 0x3D77 54#define mmUVD_MPC_SET_ALU 0x3D7E 55#define mmUVD_MPC_SET_MUX 0x3D7D 56#define mmUVD_MPC_SET_MUXA0 0x3D79 57#define mmUVD_MPC_SET_MUXA1 0x3D7A 58#define mmUVD_MPC_SET_MUXB0 0x3D7B 59#define mmUVD_MPC_SET_MUXB1 0x3D7C 60#define mmUVD_MP_SWAP_CNTL 0x3D6F 61#define mmUVD_NO_OP 0x3BFF 62#define mmUVD_PGFSM_CONFIG 0x38F8 63#define mmUVD_PGFSM_READ_TILE1 0x38FA 64#define mmUVD_PGFSM_READ_TILE2 0x38FB 65#define mmUVD_POWER_STATUS 0x38FC 66#define mmUVD_RBC_IB_BASE 0x3DA1 67#define mmUVD_RBC_IB_SIZE 0x3DA2 68#define mmUVD_RBC_IB_SIZE_UPDATE 0x3DF1 69#define mmUVD_RBC_RB_BASE 0x3DA3 70#define mmUVD_RBC_RB_CNTL 0x3DA9 71#define mmUVD_RBC_RB_RPTR 0x3DA4 72#define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA 73#define mmUVD_RBC_RB_WPTR 0x3DA5 74#define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6 75#define mmUVD_SEMA_ADDR_HIGH 0x3BC1 76#define mmUVD_SEMA_ADDR_LOW 0x3BC0 77#define mmUVD_SEMA_CMD 0x3BC2 78#define mmUVD_SEMA_CNTL 0x3D00 79#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3DB3 80#define mmUVD_SEMA_TIMEOUT_STATUS 0x3DB0 81#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3DB2 82#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3DB1 83#define mmUVD_SOFT_RESET 0x3DA0 84#define mmUVD_STATUS 0x3DAF 85#define mmUVD_UDEC_ADDR_CONFIG 0x3BD3 86#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3BD4 87#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5 88#define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 89#define mmUVD_VCPU_CACHE_OFFSET1 0x3D38 90#define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A 91#define mmUVD_VCPU_CACHE_SIZE0 0x3D37 92#define mmUVD_VCPU_CACHE_SIZE1 0x3D39 93#define mmUVD_VCPU_CACHE_SIZE2 0x3D3B 94#define mmUVD_VCPU_CNTL 0x3D98 95 96#endif 97