1/* 2 * Register definition file for Analogix DP core driver 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#ifndef _ANALOGIX_DP_REG_H 13#define _ANALOGIX_DP_REG_H 14 15#define ANALOGIX_DP_TX_SW_RESET 0x14 16#define ANALOGIX_DP_FUNC_EN_1 0x18 17#define ANALOGIX_DP_FUNC_EN_2 0x1C 18#define ANALOGIX_DP_VIDEO_CTL_1 0x20 19#define ANALOGIX_DP_VIDEO_CTL_2 0x24 20#define ANALOGIX_DP_VIDEO_CTL_3 0x28 21 22#define ANALOGIX_DP_VIDEO_CTL_8 0x3C 23#define ANALOGIX_DP_VIDEO_CTL_10 0x44 24 25#define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8 26 27#define ANALOGIX_DP_PLL_REG_1 0xfc 28#define ANALOGIX_DP_PLL_REG_2 0x9e4 29#define ANALOGIX_DP_PLL_REG_3 0x9e8 30#define ANALOGIX_DP_PLL_REG_4 0x9ec 31#define ANALOGIX_DP_PLL_REG_5 0xa00 32 33#define ANALOGIX_DP_PD 0x12c 34 35#define ANALOGIX_DP_IF_TYPE 0x244 36#define ANALOGIX_DP_IF_PKT_DB1 0x254 37#define ANALOGIX_DP_IF_PKT_DB2 0x258 38#define ANALOGIX_DP_SPD_HB0 0x2F8 39#define ANALOGIX_DP_SPD_HB1 0x2FC 40#define ANALOGIX_DP_SPD_HB2 0x300 41#define ANALOGIX_DP_SPD_HB3 0x304 42#define ANALOGIX_DP_SPD_PB0 0x308 43#define ANALOGIX_DP_SPD_PB1 0x30C 44#define ANALOGIX_DP_SPD_PB2 0x310 45#define ANALOGIX_DP_SPD_PB3 0x314 46#define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL 0x318 47#define ANALOGIX_DP_VSC_SHADOW_DB0 0x31C 48#define ANALOGIX_DP_VSC_SHADOW_DB1 0x320 49 50#define ANALOGIX_DP_LANE_MAP 0x35C 51 52#define ANALOGIX_DP_ANALOG_CTL_1 0x370 53#define ANALOGIX_DP_ANALOG_CTL_2 0x374 54#define ANALOGIX_DP_ANALOG_CTL_3 0x378 55#define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 56#define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 57 58#define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 59 60#define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 61#define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 62#define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 63#define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 64#define ANALOGIX_DP_INT_STA 0x3DC 65#define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 66#define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 67#define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 68#define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 69#define ANALOGIX_DP_INT_STA_MASK 0x3F8 70#define ANALOGIX_DP_INT_CTL 0x3FC 71 72#define ANALOGIX_DP_SYS_CTL_1 0x600 73#define ANALOGIX_DP_SYS_CTL_2 0x604 74#define ANALOGIX_DP_SYS_CTL_3 0x608 75#define ANALOGIX_DP_SYS_CTL_4 0x60C 76 77#define ANALOGIX_DP_PKT_SEND_CTL 0x640 78#define ANALOGIX_DP_HDCP_CTL 0x648 79 80#define ANALOGIX_DP_LINK_BW_SET 0x680 81#define ANALOGIX_DP_LANE_COUNT_SET 0x684 82#define ANALOGIX_DP_TRAINING_PTN_SET 0x688 83#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 84#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 85#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 86#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 87 88#define ANALOGIX_DP_DEBUG_CTL 0x6C0 89#define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 90#define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 91#define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 92 93#define ANALOGIX_DP_M_VID_0 0x700 94#define ANALOGIX_DP_M_VID_1 0x704 95#define ANALOGIX_DP_M_VID_2 0x708 96#define ANALOGIX_DP_N_VID_0 0x70C 97#define ANALOGIX_DP_N_VID_1 0x710 98#define ANALOGIX_DP_N_VID_2 0x714 99 100#define ANALOGIX_DP_PLL_CTL 0x71C 101#define ANALOGIX_DP_PHY_PD 0x720 102#define ANALOGIX_DP_PHY_TEST 0x724 103 104#define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 105#define ANALOGIX_DP_AUDIO_MARGIN 0x73C 106 107#define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 108#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 109#define ANALOGIX_DP_AUX_CH_STA 0x780 110#define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 111#define ANALOGIX_DP_AUX_RX_COMM 0x78C 112#define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 113#define ANALOGIX_DP_AUX_CH_CTL_1 0x794 114#define ANALOGIX_DP_AUX_ADDR_7_0 0x798 115#define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 116#define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 117#define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 118 119#define ANALOGIX_DP_BUF_DATA_0 0x7C0 120 121#define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 122 123#define ANALOGIX_DP_CRC_CON 0x890 124 125/* ANALOGIX_DP_TX_SW_RESET */ 126#define RESET_DP_TX (0x1 << 0) 127 128/* ANALOGIX_DP_FUNC_EN_1 */ 129#define MASTER_VID_FUNC_EN_N (0x1 << 7) 130#define SLAVE_VID_FUNC_EN_N (0x1 << 5) 131#define AUD_FIFO_FUNC_EN_N (0x1 << 4) 132#define AUD_FUNC_EN_N (0x1 << 3) 133#define HDCP_FUNC_EN_N (0x1 << 2) 134#define CRC_FUNC_EN_N (0x1 << 1) 135#define SW_FUNC_EN_N (0x1 << 0) 136 137/* ANALOGIX_DP_FUNC_EN_2 */ 138#define SSC_FUNC_EN_N (0x1 << 7) 139#define AUX_FUNC_EN_N (0x1 << 2) 140#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 141#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 142 143/* ANALOGIX_DP_VIDEO_CTL_1 */ 144#define VIDEO_EN (0x1 << 7) 145#define HDCP_VIDEO_MUTE (0x1 << 6) 146 147/* ANALOGIX_DP_VIDEO_CTL_1 */ 148#define IN_D_RANGE_MASK (0x1 << 7) 149#define IN_D_RANGE_SHIFT (7) 150#define IN_D_RANGE_CEA (0x1 << 7) 151#define IN_D_RANGE_VESA (0x0 << 7) 152#define IN_BPC_MASK (0x7 << 4) 153#define IN_BPC_SHIFT (4) 154#define IN_BPC_12_BITS (0x3 << 4) 155#define IN_BPC_10_BITS (0x2 << 4) 156#define IN_BPC_8_BITS (0x1 << 4) 157#define IN_BPC_6_BITS (0x0 << 4) 158#define IN_COLOR_F_MASK (0x3 << 0) 159#define IN_COLOR_F_SHIFT (0) 160#define IN_COLOR_F_YCBCR444 (0x2 << 0) 161#define IN_COLOR_F_YCBCR422 (0x1 << 0) 162#define IN_COLOR_F_RGB (0x0 << 0) 163 164/* ANALOGIX_DP_VIDEO_CTL_3 */ 165#define IN_YC_COEFFI_MASK (0x1 << 7) 166#define IN_YC_COEFFI_SHIFT (7) 167#define IN_YC_COEFFI_ITU709 (0x1 << 7) 168#define IN_YC_COEFFI_ITU601 (0x0 << 7) 169#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 170#define VID_CHK_UPDATE_TYPE_SHIFT (4) 171#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 172#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 173#define REUSE_SPD_EN (0x1 << 3) 174 175/* ANALOGIX_DP_VIDEO_CTL_8 */ 176#define VID_HRES_TH(x) (((x) & 0xf) << 4) 177#define VID_VRES_TH(x) (((x) & 0xf) << 0) 178 179/* ANALOGIX_DP_VIDEO_CTL_10 */ 180#define FORMAT_SEL (0x1 << 4) 181#define INTERACE_SCAN_CFG (0x1 << 2) 182#define VSYNC_POLARITY_CFG (0x1 << 1) 183#define HSYNC_POLARITY_CFG (0x1 << 0) 184 185/* ANALOGIX_DP_PLL_REG_1 */ 186#define REF_CLK_24M (0x1 << 0) 187#define REF_CLK_27M (0x0 << 0) 188#define REF_CLK_MASK (0x1 << 0) 189 190/* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */ 191#define PSR_FRAME_UP_TYPE_BURST (0x1 << 0) 192#define PSR_FRAME_UP_TYPE_SINGLE (0x0 << 0) 193#define PSR_CRC_SEL_HARDWARE (0x1 << 1) 194#define PSR_CRC_SEL_MANUALLY (0x0 << 1) 195 196/* ANALOGIX_DP_LANE_MAP */ 197#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 198#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 199#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 200#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 201#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 202#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 203#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 204#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 205#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 206#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 207#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 208#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 209#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 210#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 211#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 212#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 213 214/* ANALOGIX_DP_ANALOG_CTL_1 */ 215#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 216 217/* ANALOGIX_DP_ANALOG_CTL_2 */ 218#define SEL_24M (0x1 << 3) 219#define TX_DVDD_BIT_1_0625V (0x4 << 0) 220 221/* ANALOGIX_DP_ANALOG_CTL_3 */ 222#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 223#define VCO_BIT_600_MICRO (0x5 << 0) 224 225/* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 226#define PD_RING_OSC (0x1 << 6) 227#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 228#define TX_CUR1_2X (0x1 << 2) 229#define TX_CUR_16_MA (0x3 << 0) 230 231/* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 232#define CH3_AMP_400_MV (0x0 << 24) 233#define CH2_AMP_400_MV (0x0 << 16) 234#define CH1_AMP_400_MV (0x0 << 8) 235#define CH0_AMP_400_MV (0x0 << 0) 236 237/* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 238#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 239#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 240#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 241#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 242#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 243#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 244#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 245 246/* ANALOGIX_DP_COMMON_INT_STA_1 */ 247#define VSYNC_DET (0x1 << 7) 248#define PLL_LOCK_CHG (0x1 << 6) 249#define SPDIF_ERR (0x1 << 5) 250#define SPDIF_UNSTBL (0x1 << 4) 251#define VID_FORMAT_CHG (0x1 << 3) 252#define AUD_CLK_CHG (0x1 << 2) 253#define VID_CLK_CHG (0x1 << 1) 254#define SW_INT (0x1 << 0) 255 256/* ANALOGIX_DP_COMMON_INT_STA_2 */ 257#define ENC_EN_CHG (0x1 << 6) 258#define HW_BKSV_RDY (0x1 << 3) 259#define HW_SHA_DONE (0x1 << 2) 260#define HW_AUTH_STATE_CHG (0x1 << 1) 261#define HW_AUTH_DONE (0x1 << 0) 262 263/* ANALOGIX_DP_COMMON_INT_STA_3 */ 264#define AFIFO_UNDER (0x1 << 7) 265#define AFIFO_OVER (0x1 << 6) 266#define R0_CHK_FLAG (0x1 << 5) 267 268/* ANALOGIX_DP_COMMON_INT_STA_4 */ 269#define PSR_ACTIVE (0x1 << 7) 270#define PSR_INACTIVE (0x1 << 6) 271#define SPDIF_BI_PHASE_ERR (0x1 << 5) 272#define HOTPLUG_CHG (0x1 << 2) 273#define HPD_LOST (0x1 << 1) 274#define PLUG (0x1 << 0) 275 276/* ANALOGIX_DP_INT_STA */ 277#define INT_HPD (0x1 << 6) 278#define HW_TRAINING_FINISH (0x1 << 5) 279#define RPLY_RECEIV (0x1 << 1) 280#define AUX_ERR (0x1 << 0) 281 282/* ANALOGIX_DP_INT_CTL */ 283#define SOFT_INT_CTRL (0x1 << 2) 284#define INT_POL1 (0x1 << 1) 285#define INT_POL0 (0x1 << 0) 286 287/* ANALOGIX_DP_SYS_CTL_1 */ 288#define DET_STA (0x1 << 2) 289#define FORCE_DET (0x1 << 1) 290#define DET_CTRL (0x1 << 0) 291 292/* ANALOGIX_DP_SYS_CTL_2 */ 293#define CHA_CRI(x) (((x) & 0xf) << 4) 294#define CHA_STA (0x1 << 2) 295#define FORCE_CHA (0x1 << 1) 296#define CHA_CTRL (0x1 << 0) 297 298/* ANALOGIX_DP_SYS_CTL_3 */ 299#define HPD_STATUS (0x1 << 6) 300#define F_HPD (0x1 << 5) 301#define HPD_CTRL (0x1 << 4) 302#define HDCP_RDY (0x1 << 3) 303#define STRM_VALID (0x1 << 2) 304#define F_VALID (0x1 << 1) 305#define VALID_CTRL (0x1 << 0) 306 307/* ANALOGIX_DP_SYS_CTL_4 */ 308#define FIX_M_AUD (0x1 << 4) 309#define ENHANCED (0x1 << 3) 310#define FIX_M_VID (0x1 << 2) 311#define M_VID_UPDATE_CTRL (0x3 << 0) 312 313/* ANALOGIX_DP_TRAINING_PTN_SET */ 314#define SCRAMBLER_TYPE (0x1 << 9) 315#define HW_LINK_TRAINING_PATTERN (0x1 << 8) 316#define SCRAMBLING_DISABLE (0x1 << 5) 317#define SCRAMBLING_ENABLE (0x0 << 5) 318#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 319#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 320#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 321#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 322#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 323#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 324#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 325#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 326 327/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 328#define PRE_EMPHASIS_SET_MASK (0x3 << 3) 329#define PRE_EMPHASIS_SET_SHIFT (3) 330 331/* ANALOGIX_DP_DEBUG_CTL */ 332#define PLL_LOCK (0x1 << 4) 333#define F_PLL_LOCK (0x1 << 3) 334#define PLL_LOCK_CTRL (0x1 << 2) 335#define PN_INV (0x1 << 0) 336 337/* ANALOGIX_DP_PLL_CTL */ 338#define DP_PLL_PD (0x1 << 7) 339#define DP_PLL_RESET (0x1 << 6) 340#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 341#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 342#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 343 344/* ANALOGIX_DP_PHY_PD */ 345#define DP_PHY_PD (0x1 << 5) 346#define AUX_PD (0x1 << 4) 347#define CH3_PD (0x1 << 3) 348#define CH2_PD (0x1 << 2) 349#define CH1_PD (0x1 << 1) 350#define CH0_PD (0x1 << 0) 351 352/* ANALOGIX_DP_PHY_TEST */ 353#define MACRO_RST (0x1 << 5) 354#define CH1_TEST (0x1 << 1) 355#define CH0_TEST (0x1 << 0) 356 357/* ANALOGIX_DP_AUX_CH_STA */ 358#define AUX_BUSY (0x1 << 4) 359#define AUX_STATUS_MASK (0xf << 0) 360 361/* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 362#define DEFER_CTRL_EN (0x1 << 7) 363#define DEFER_COUNT(x) (((x) & 0x7f) << 0) 364 365/* ANALOGIX_DP_AUX_RX_COMM */ 366#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 367#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 368 369/* ANALOGIX_DP_BUFFER_DATA_CTL */ 370#define BUF_CLR (0x1 << 7) 371#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 372 373/* ANALOGIX_DP_AUX_CH_CTL_1 */ 374#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 375#define AUX_TX_COMM_MASK (0xf << 0) 376#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 377#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 378#define AUX_TX_COMM_MOT (0x1 << 2) 379#define AUX_TX_COMM_WRITE (0x0 << 0) 380#define AUX_TX_COMM_READ (0x1 << 0) 381 382/* ANALOGIX_DP_AUX_ADDR_7_0 */ 383#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 384 385/* ANALOGIX_DP_AUX_ADDR_15_8 */ 386#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 387 388/* ANALOGIX_DP_AUX_ADDR_19_16 */ 389#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 390 391/* ANALOGIX_DP_AUX_CH_CTL_2 */ 392#define ADDR_ONLY (0x1 << 1) 393#define AUX_EN (0x1 << 0) 394 395/* ANALOGIX_DP_SOC_GENERAL_CTL */ 396#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 397#define AUDIO_MODE_MASTER_MODE (0x0 << 8) 398#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 399#define VIDEO_MASTER_CLK_SEL (0x1 << 2) 400#define VIDEO_MASTER_MODE_EN (0x1 << 1) 401#define VIDEO_MODE_MASK (0x1 << 0) 402#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 403#define VIDEO_MODE_MASTER_MODE (0x0 << 0) 404 405/* ANALOGIX_DP_PKT_SEND_CTL */ 406#define IF_UP (0x1 << 4) 407#define IF_EN (0x1 << 0) 408 409/* ANALOGIX_DP_CRC_CON */ 410#define PSR_VID_CRC_FLUSH (0x1 << 2) 411#define PSR_VID_CRC_ENABLE (0x1 << 0) 412 413#endif /* _ANALOGIX_DP_REG_H */ 414