1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <linux/bitops.h>
19#include <linux/clk.h>
20#include <video/display_timing.h>
21#include <linux/mfd/syscon.h>
22#include <linux/regmap.h>
23#include <linux/reset.h>
24
25#include <drm/drmP.h>
26#include <drm/drm_crtc.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_plane_helper.h>
31#include <drm/drm_gem_cma_helper.h>
32#include <drm/drm_fb_cma_helper.h>
33
34#include "kirin_drm_drv.h"
35#include "kirin_ade_reg.h"
36
37#define PRIMARY_CH ADE_CH1
38#define OUT_OVLY ADE_OVLY2
39#define ADE_DEBUG 1
40
41#define to_ade_crtc(crtc) \
42 container_of(crtc, struct ade_crtc, base)
43
44#define to_ade_plane(plane) \
45 container_of(plane, struct ade_plane, base)
46
47struct ade_hw_ctx {
48 void __iomem *base;
49 struct regmap *noc_regmap;
50 struct clk *ade_core_clk;
51 struct clk *media_noc_clk;
52 struct clk *ade_pix_clk;
53 struct reset_control *reset;
54 bool power_on;
55 int irq;
56};
57
58struct ade_crtc {
59 struct drm_crtc base;
60 struct ade_hw_ctx *ctx;
61 bool enable;
62 u32 out_format;
63};
64
65struct ade_plane {
66 struct drm_plane base;
67 void *ctx;
68 u8 ch;
69};
70
71struct ade_data {
72 struct ade_crtc acrtc;
73 struct ade_plane aplane[ADE_CH_NUM];
74 struct ade_hw_ctx ctx;
75};
76
77
78struct ade_format {
79 u32 pixel_format;
80 enum ade_fb_format ade_format;
81};
82
83static const struct ade_format ade_formats[] = {
84
85 { DRM_FORMAT_RGB565, ADE_RGB_565 },
86 { DRM_FORMAT_BGR565, ADE_BGR_565 },
87
88 { DRM_FORMAT_RGB888, ADE_RGB_888 },
89 { DRM_FORMAT_BGR888, ADE_BGR_888 },
90
91 { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 },
92 { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 },
93 { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 },
94 { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 },
95 { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 },
96 { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 },
97};
98
99static const u32 channel_formats1[] = {
100
101 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
102 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
103 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
104 DRM_FORMAT_ABGR8888
105};
106
107u32 ade_get_channel_formats(u8 ch, const u32 **formats)
108{
109 switch (ch) {
110 case ADE_CH1:
111 *formats = channel_formats1;
112 return ARRAY_SIZE(channel_formats1);
113 default:
114 DRM_ERROR("no this channel %d\n", ch);
115 *formats = NULL;
116 return 0;
117 }
118}
119
120
121static u32 ade_get_format(u32 pixel_format)
122{
123 int i;
124
125 for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
126 if (ade_formats[i].pixel_format == pixel_format)
127 return ade_formats[i].ade_format;
128
129
130 DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
131 pixel_format);
132 return ADE_FORMAT_UNSUPPORT;
133}
134
135static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
136{
137 u32 bit_ofst, reg_num;
138
139 bit_ofst = bit_num % 32;
140 reg_num = bit_num / 32;
141
142 ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst,
143 MASK(1), !!val);
144}
145
146static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num)
147{
148 u32 tmp, bit_ofst, reg_num;
149
150 bit_ofst = bit_num % 32;
151 reg_num = bit_num / 32;
152
153 tmp = readl(base + ADE_RELOAD_DIS(reg_num));
154 return !!(BIT(bit_ofst) & tmp);
155}
156
157static void ade_init(struct ade_hw_ctx *ctx)
158{
159 void __iomem *base = ctx->base;
160
161
162 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST,
163 AUTO_CLK_GATE_EN, ADE_ENABLE);
164
165 writel(0, base + ADE_OVLY1_TRANS_CFG);
166 writel(0, base + ADE_OVLY_CTL);
167 writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
168
169 writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
170 writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
171 writel(MASK(32), base + ADE_RELOAD_DIS(0));
172 writel(MASK(32), base + ADE_RELOAD_DIS(1));
173
174
175
176
177 ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
178 FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
179}
180
181static void ade_set_pix_clk(struct ade_hw_ctx *ctx,
182 struct drm_display_mode *mode,
183 struct drm_display_mode *adj_mode)
184{
185 u32 clk_Hz = mode->clock * 1000;
186 int ret;
187
188
189
190
191
192 ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz);
193 if (ret)
194 DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret);
195 adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
196}
197
198static void ade_ldi_set_mode(struct ade_crtc *acrtc,
199 struct drm_display_mode *mode,
200 struct drm_display_mode *adj_mode)
201{
202 struct ade_hw_ctx *ctx = acrtc->ctx;
203 void __iomem *base = ctx->base;
204 u32 width = mode->hdisplay;
205 u32 height = mode->vdisplay;
206 u32 hfp, hbp, hsw, vfp, vbp, vsw;
207 u32 plr_flags;
208
209 plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0;
210 plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0;
211 hfp = mode->hsync_start - mode->hdisplay;
212 hbp = mode->htotal - mode->hsync_end;
213 hsw = mode->hsync_end - mode->hsync_start;
214 vfp = mode->vsync_start - mode->vdisplay;
215 vbp = mode->vtotal - mode->vsync_end;
216 vsw = mode->vsync_end - mode->vsync_start;
217 if (vsw > 15) {
218 DRM_DEBUG_DRIVER("vsw exceeded 15\n");
219 vsw = 15;
220 }
221
222 writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0);
223
224 writel(hsw - 1, base + LDI_HRZ_CTRL1);
225 writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0);
226
227 writel(vsw - 1, base + LDI_VRT_CTRL1);
228
229 writel(((height - 1) << VSIZE_OFST) | (width - 1),
230 base + LDI_DSP_SIZE);
231 writel(plr_flags, base + LDI_PLR_CTRL);
232
233
234 writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
235 base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
236
237
238 writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
239
240 writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6));
241 ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0);
242
243 ade_set_pix_clk(ctx, mode, adj_mode);
244
245 DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height);
246}
247
248static int ade_power_up(struct ade_hw_ctx *ctx)
249{
250 int ret;
251
252 ret = clk_prepare_enable(ctx->media_noc_clk);
253 if (ret) {
254 DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret);
255 return ret;
256 }
257
258 ret = reset_control_deassert(ctx->reset);
259 if (ret) {
260 DRM_ERROR("failed to deassert reset\n");
261 return ret;
262 }
263
264 ret = clk_prepare_enable(ctx->ade_core_clk);
265 if (ret) {
266 DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret);
267 return ret;
268 }
269
270 ade_init(ctx);
271 ctx->power_on = true;
272 return 0;
273}
274
275static void ade_power_down(struct ade_hw_ctx *ctx)
276{
277 void __iomem *base = ctx->base;
278
279 writel(ADE_DISABLE, base + LDI_CTRL);
280
281 writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT);
282
283 clk_disable_unprepare(ctx->ade_core_clk);
284 reset_control_assert(ctx->reset);
285 clk_disable_unprepare(ctx->media_noc_clk);
286 ctx->power_on = false;
287}
288
289static void ade_set_medianoc_qos(struct ade_crtc *acrtc)
290{
291 struct ade_hw_ctx *ctx = acrtc->ctx;
292 struct regmap *map = ctx->noc_regmap;
293
294 regmap_update_bits(map, ADE0_QOSGENERATOR_MODE,
295 QOSGENERATOR_MODE_MASK, BYPASS_MODE);
296 regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL,
297 SOCKET_QOS_EN, SOCKET_QOS_EN);
298
299 regmap_update_bits(map, ADE1_QOSGENERATOR_MODE,
300 QOSGENERATOR_MODE_MASK, BYPASS_MODE);
301 regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL,
302 SOCKET_QOS_EN, SOCKET_QOS_EN);
303}
304
305static int ade_crtc_enable_vblank(struct drm_crtc *crtc)
306{
307 struct ade_crtc *acrtc = to_ade_crtc(crtc);
308 struct ade_hw_ctx *ctx = acrtc->ctx;
309 void __iomem *base = ctx->base;
310
311 if (!ctx->power_on)
312 (void)ade_power_up(ctx);
313
314 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
315 MASK(1), 1);
316
317 return 0;
318}
319
320static void ade_crtc_disable_vblank(struct drm_crtc *crtc)
321{
322 struct ade_crtc *acrtc = to_ade_crtc(crtc);
323 struct ade_hw_ctx *ctx = acrtc->ctx;
324 void __iomem *base = ctx->base;
325
326 if (!ctx->power_on) {
327 DRM_ERROR("power is down! vblank disable fail\n");
328 return;
329 }
330
331 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
332 MASK(1), 0);
333}
334
335static irqreturn_t ade_irq_handler(int irq, void *data)
336{
337 struct ade_crtc *acrtc = data;
338 struct ade_hw_ctx *ctx = acrtc->ctx;
339 struct drm_crtc *crtc = &acrtc->base;
340 void __iomem *base = ctx->base;
341 u32 status;
342
343 status = readl(base + LDI_MSK_INT);
344 DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
345
346
347 if (status & BIT(FRAME_END_INT_EN_OFST)) {
348 ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
349 MASK(1), 1);
350 drm_crtc_handle_vblank(crtc);
351 }
352
353 return IRQ_HANDLED;
354}
355
356static void ade_display_enable(struct ade_crtc *acrtc)
357{
358 struct ade_hw_ctx *ctx = acrtc->ctx;
359 void __iomem *base = ctx->base;
360 u32 out_fmt = acrtc->out_format;
361
362
363 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
364 ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
365
366
367 writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
368
369
370 writel(ADE_ENABLE, base + ADE_EN);
371
372 writel(NORMAL_MODE, base + LDI_WORK_MODE);
373 writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN,
374 base + LDI_CTRL);
375
376 writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
377}
378
379#if ADE_DEBUG
380static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
381{
382 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
383 u32 val;
384
385 reg_ctrl = RD_CH_CTRL(ch);
386 reg_addr = RD_CH_ADDR(ch);
387 reg_size = RD_CH_SIZE(ch);
388 reg_stride = RD_CH_STRIDE(ch);
389 reg_space = RD_CH_SPACE(ch);
390 reg_en = RD_CH_EN(ch);
391
392 val = ade_read_reload_bit(base, RDMA_OFST + ch);
393 DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val);
394 val = readl(base + reg_ctrl);
395 DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val);
396 val = readl(base + reg_addr);
397 DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val);
398 val = readl(base + reg_size);
399 DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val);
400 val = readl(base + reg_stride);
401 DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val);
402 val = readl(base + reg_space);
403 DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val);
404 val = readl(base + reg_en);
405 DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val);
406}
407
408static void ade_clip_dump_regs(void __iomem *base, u32 ch)
409{
410 u32 val;
411
412 val = ade_read_reload_bit(base, CLIP_OFST + ch);
413 DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val);
414 val = readl(base + ADE_CLIP_DISABLE(ch));
415 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val);
416 val = readl(base + ADE_CLIP_SIZE0(ch));
417 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val);
418 val = readl(base + ADE_CLIP_SIZE1(ch));
419 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val);
420}
421
422static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch)
423{
424 u8 ovly_ch = 0;
425 u32 val;
426
427 val = readl(base + ADE_OVLY_CH_XY0(ovly_ch));
428 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val);
429 val = readl(base + ADE_OVLY_CH_XY1(ovly_ch));
430 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val);
431 val = readl(base + ADE_OVLY_CH_CTL(ovly_ch));
432 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val);
433}
434
435static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp)
436{
437 u32 val;
438
439 val = ade_read_reload_bit(base, OVLY_OFST + comp);
440 DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val);
441 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
442 DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val);
443 val = readl(base + ADE_OVLY_CTL);
444 DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val);
445}
446
447static void ade_dump_regs(void __iomem *base)
448{
449 u32 i;
450
451
452 for (i = 0; i < ADE_CH_NUM; i++) {
453
454 ade_rdma_dump_regs(base, i);
455
456
457 ade_clip_dump_regs(base, i);
458
459
460 ade_compositor_routing_dump_regs(base, i);
461 }
462
463
464 ade_dump_overlay_compositor_regs(base, OUT_OVLY);
465}
466#else
467static void ade_dump_regs(void __iomem *base) { }
468#endif
469
470static void ade_crtc_enable(struct drm_crtc *crtc)
471{
472 struct ade_crtc *acrtc = to_ade_crtc(crtc);
473 struct ade_hw_ctx *ctx = acrtc->ctx;
474 int ret;
475
476 if (acrtc->enable)
477 return;
478
479 if (!ctx->power_on) {
480 ret = ade_power_up(ctx);
481 if (ret)
482 return;
483 }
484
485 ade_set_medianoc_qos(acrtc);
486 ade_display_enable(acrtc);
487 ade_dump_regs(ctx->base);
488 drm_crtc_vblank_on(crtc);
489 acrtc->enable = true;
490}
491
492static void ade_crtc_disable(struct drm_crtc *crtc)
493{
494 struct ade_crtc *acrtc = to_ade_crtc(crtc);
495 struct ade_hw_ctx *ctx = acrtc->ctx;
496
497 if (!acrtc->enable)
498 return;
499
500 drm_crtc_vblank_off(crtc);
501 ade_power_down(ctx);
502 acrtc->enable = false;
503}
504
505static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc)
506{
507 struct ade_crtc *acrtc = to_ade_crtc(crtc);
508 struct ade_hw_ctx *ctx = acrtc->ctx;
509 struct drm_display_mode *mode = &crtc->state->mode;
510 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
511
512 if (!ctx->power_on)
513 (void)ade_power_up(ctx);
514 ade_ldi_set_mode(acrtc, mode, adj_mode);
515}
516
517static void ade_crtc_atomic_begin(struct drm_crtc *crtc,
518 struct drm_crtc_state *old_state)
519{
520 struct ade_crtc *acrtc = to_ade_crtc(crtc);
521 struct ade_hw_ctx *ctx = acrtc->ctx;
522
523 if (!ctx->power_on)
524 (void)ade_power_up(ctx);
525}
526
527static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
528 struct drm_crtc_state *old_state)
529
530{
531 struct ade_crtc *acrtc = to_ade_crtc(crtc);
532 struct ade_hw_ctx *ctx = acrtc->ctx;
533 struct drm_pending_vblank_event *event = crtc->state->event;
534 void __iomem *base = ctx->base;
535
536
537 if (acrtc->enable) {
538 ade_dump_regs(base);
539
540 writel(ADE_ENABLE, base + ADE_EN);
541 }
542
543 if (event) {
544 crtc->state->event = NULL;
545
546 spin_lock_irq(&crtc->dev->event_lock);
547 if (drm_crtc_vblank_get(crtc) == 0)
548 drm_crtc_arm_vblank_event(crtc, event);
549 else
550 drm_crtc_send_vblank_event(crtc, event);
551 spin_unlock_irq(&crtc->dev->event_lock);
552 }
553}
554
555static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = {
556 .enable = ade_crtc_enable,
557 .disable = ade_crtc_disable,
558 .mode_set_nofb = ade_crtc_mode_set_nofb,
559 .atomic_begin = ade_crtc_atomic_begin,
560 .atomic_flush = ade_crtc_atomic_flush,
561};
562
563static const struct drm_crtc_funcs ade_crtc_funcs = {
564 .destroy = drm_crtc_cleanup,
565 .set_config = drm_atomic_helper_set_config,
566 .page_flip = drm_atomic_helper_page_flip,
567 .reset = drm_atomic_helper_crtc_reset,
568 .set_property = drm_atomic_helper_crtc_set_property,
569 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
570 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
571 .enable_vblank = ade_crtc_enable_vblank,
572 .disable_vblank = ade_crtc_disable_vblank,
573};
574
575static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
576 struct drm_plane *plane)
577{
578 struct device_node *port;
579 int ret;
580
581
582
583
584 port = of_get_child_by_name(dev->dev->of_node, "port");
585 if (!port) {
586 DRM_ERROR("no port node found in %s\n",
587 dev->dev->of_node->full_name);
588 return -EINVAL;
589 }
590 of_node_put(port);
591 crtc->port = port;
592
593 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
594 &ade_crtc_funcs, NULL);
595 if (ret) {
596 DRM_ERROR("failed to init crtc.\n");
597 return ret;
598 }
599
600 drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs);
601
602 return 0;
603}
604
605static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,
606 u32 ch, u32 y, u32 in_h, u32 fmt)
607{
608 struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
609 struct drm_format_name_buf format_name;
610 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
611 u32 stride = fb->pitches[0];
612 u32 addr = (u32)obj->paddr + y * stride;
613
614 DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
615 ch + 1, y, in_h, stride, (u32)obj->paddr);
616 DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n",
617 addr, fb->width, fb->height, fmt,
618 drm_get_format_name(fb->format->format, &format_name));
619
620
621 reg_ctrl = RD_CH_CTRL(ch);
622 reg_addr = RD_CH_ADDR(ch);
623 reg_size = RD_CH_SIZE(ch);
624 reg_stride = RD_CH_STRIDE(ch);
625 reg_space = RD_CH_SPACE(ch);
626 reg_en = RD_CH_EN(ch);
627
628
629
630
631 writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
632 writel(addr, base + reg_addr);
633 writel((in_h << 16) | stride, base + reg_size);
634 writel(stride, base + reg_stride);
635 writel(in_h * stride, base + reg_space);
636 writel(ADE_ENABLE, base + reg_en);
637 ade_update_reload_bit(base, RDMA_OFST + ch, 0);
638}
639
640static void ade_rdma_disable(void __iomem *base, u32 ch)
641{
642 u32 reg_en;
643
644
645 reg_en = RD_CH_EN(ch);
646 writel(0, base + reg_en);
647 ade_update_reload_bit(base, RDMA_OFST + ch, 1);
648}
649
650static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,
651 u32 in_w, u32 in_h)
652{
653 u32 disable_val;
654 u32 clip_left;
655 u32 clip_right;
656
657
658
659
660 if (fb_w == in_w) {
661 disable_val = 1;
662 clip_left = 0;
663 clip_right = 0;
664 } else {
665 disable_val = 0;
666 clip_left = x;
667 clip_right = fb_w - (x + in_w) - 1;
668 }
669
670 DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",
671 ch + 1, clip_left, clip_right);
672
673 writel(disable_val, base + ADE_CLIP_DISABLE(ch));
674 writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
675 writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
676 ade_update_reload_bit(base, CLIP_OFST + ch, 0);
677}
678
679static void ade_clip_disable(void __iomem *base, u32 ch)
680{
681 writel(1, base + ADE_CLIP_DISABLE(ch));
682 ade_update_reload_bit(base, CLIP_OFST + ch, 1);
683}
684
685static bool has_Alpha_channel(int format)
686{
687 switch (format) {
688 case ADE_ARGB_8888:
689 case ADE_ABGR_8888:
690 case ADE_RGBA_8888:
691 case ADE_BGRA_8888:
692 return true;
693 default:
694 return false;
695 }
696}
697
698static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,
699 u8 *alp_sel, u8 *under_alp_sel)
700{
701 bool has_alpha = has_Alpha_channel(fmt);
702
703
704
705
706 if (has_alpha && glb_alpha < 255)
707 *alp_mode = ADE_ALP_PIXEL_AND_GLB;
708 else if (has_alpha)
709 *alp_mode = ADE_ALP_PIXEL;
710 else
711 *alp_mode = ADE_ALP_GLOBAL;
712
713
714
715
716 *alp_sel = ADE_ALP_MUL_COEFF_3;
717 *under_alp_sel = ADE_ALP_MUL_COEFF_2;
718}
719
720static void ade_compositor_routing_set(void __iomem *base, u8 ch,
721 u32 x0, u32 y0,
722 u32 in_w, u32 in_h, u32 fmt)
723{
724 u8 ovly_ch = 0;
725 u8 glb_alpha = 255;
726 u32 x1 = x0 + in_w - 1;
727 u32 y1 = y0 + in_h - 1;
728 u32 val;
729 u8 alp_sel;
730 u8 under_alp_sel;
731 u8 alp_mode;
732
733 ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel,
734 &under_alp_sel);
735
736
737
738 writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch));
739 writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch));
740 val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) |
741 alp_sel << CH_ALP_SEL_OFST |
742 under_alp_sel << CH_UNDER_ALP_SEL_OFST |
743 glb_alpha << CH_ALP_GBL_OFST |
744 alp_mode << CH_ALP_MODE_OFST;
745 writel(val, base + ADE_OVLY_CH_CTL(ovly_ch));
746
747 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
748 CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY));
749}
750
751static void ade_compositor_routing_disable(void __iomem *base, u32 ch)
752{
753 u8 ovly_ch = 0;
754
755
756 ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST,
757 MASK(1), 0);
758
759 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
760 CH_OVLY_SEL_MASK, 0);
761}
762
763
764
765
766static void ade_update_channel(struct ade_plane *aplane,
767 struct drm_framebuffer *fb, int crtc_x,
768 int crtc_y, unsigned int crtc_w,
769 unsigned int crtc_h, u32 src_x,
770 u32 src_y, u32 src_w, u32 src_h)
771{
772 struct ade_hw_ctx *ctx = aplane->ctx;
773 void __iomem *base = ctx->base;
774 u32 fmt = ade_get_format(fb->format->format);
775 u32 ch = aplane->ch;
776 u32 in_w;
777 u32 in_h;
778
779 DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d",
780 ch + 1, src_x, src_y, src_w, src_h,
781 crtc_x, crtc_y, crtc_w, crtc_h);
782
783
784 in_w = src_w;
785 in_h = src_h;
786 ade_rdma_set(base, fb, ch, src_y, in_h, fmt);
787
788
789 ade_clip_set(base, ch, fb->width, src_x, in_w, in_h);
790
791
792
793
794
795
796 ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt);
797}
798
799static void ade_disable_channel(struct ade_plane *aplane)
800{
801 struct ade_hw_ctx *ctx = aplane->ctx;
802 void __iomem *base = ctx->base;
803 u32 ch = aplane->ch;
804
805 DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1);
806
807
808 ade_rdma_disable(base, ch);
809
810
811 ade_clip_disable(base, ch);
812
813
814 ade_compositor_routing_disable(base, ch);
815}
816
817static int ade_plane_atomic_check(struct drm_plane *plane,
818 struct drm_plane_state *state)
819{
820 struct drm_framebuffer *fb = state->fb;
821 struct drm_crtc *crtc = state->crtc;
822 struct drm_crtc_state *crtc_state;
823 u32 src_x = state->src_x >> 16;
824 u32 src_y = state->src_y >> 16;
825 u32 src_w = state->src_w >> 16;
826 u32 src_h = state->src_h >> 16;
827 int crtc_x = state->crtc_x;
828 int crtc_y = state->crtc_y;
829 u32 crtc_w = state->crtc_w;
830 u32 crtc_h = state->crtc_h;
831 u32 fmt;
832
833 if (!crtc || !fb)
834 return 0;
835
836 fmt = ade_get_format(fb->format->format);
837 if (fmt == ADE_FORMAT_UNSUPPORT)
838 return -EINVAL;
839
840 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
841 if (IS_ERR(crtc_state))
842 return PTR_ERR(crtc_state);
843
844 if (src_w != crtc_w || src_h != crtc_h) {
845 DRM_ERROR("Scale not support!!!\n");
846 return -EINVAL;
847 }
848
849 if (src_x + src_w > fb->width ||
850 src_y + src_h > fb->height)
851 return -EINVAL;
852
853 if (crtc_x < 0 || crtc_y < 0)
854 return -EINVAL;
855
856 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||
857 crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay)
858 return -EINVAL;
859
860 return 0;
861}
862
863static void ade_plane_atomic_update(struct drm_plane *plane,
864 struct drm_plane_state *old_state)
865{
866 struct drm_plane_state *state = plane->state;
867 struct ade_plane *aplane = to_ade_plane(plane);
868
869 ade_update_channel(aplane, state->fb, state->crtc_x, state->crtc_y,
870 state->crtc_w, state->crtc_h,
871 state->src_x >> 16, state->src_y >> 16,
872 state->src_w >> 16, state->src_h >> 16);
873}
874
875static void ade_plane_atomic_disable(struct drm_plane *plane,
876 struct drm_plane_state *old_state)
877{
878 struct ade_plane *aplane = to_ade_plane(plane);
879
880 ade_disable_channel(aplane);
881}
882
883static const struct drm_plane_helper_funcs ade_plane_helper_funcs = {
884 .atomic_check = ade_plane_atomic_check,
885 .atomic_update = ade_plane_atomic_update,
886 .atomic_disable = ade_plane_atomic_disable,
887};
888
889static struct drm_plane_funcs ade_plane_funcs = {
890 .update_plane = drm_atomic_helper_update_plane,
891 .disable_plane = drm_atomic_helper_disable_plane,
892 .set_property = drm_atomic_helper_plane_set_property,
893 .destroy = drm_plane_cleanup,
894 .reset = drm_atomic_helper_plane_reset,
895 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
896 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
897};
898
899static int ade_plane_init(struct drm_device *dev, struct ade_plane *aplane,
900 enum drm_plane_type type)
901{
902 const u32 *fmts;
903 u32 fmts_cnt;
904 int ret = 0;
905
906
907 fmts_cnt = ade_get_channel_formats(aplane->ch, &fmts);
908 if (ret)
909 return ret;
910
911 ret = drm_universal_plane_init(dev, &aplane->base, 1, &ade_plane_funcs,
912 fmts, fmts_cnt, type, NULL);
913 if (ret) {
914 DRM_ERROR("fail to init plane, ch=%d\n", aplane->ch);
915 return ret;
916 }
917
918 drm_plane_helper_add(&aplane->base, &ade_plane_helper_funcs);
919
920 return 0;
921}
922
923static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx)
924{
925 struct resource *res;
926 struct device *dev = &pdev->dev;
927 struct device_node *np = pdev->dev.of_node;
928
929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
930 ctx->base = devm_ioremap_resource(dev, res);
931 if (IS_ERR(ctx->base)) {
932 DRM_ERROR("failed to remap ade io base\n");
933 return PTR_ERR(ctx->base);
934 }
935
936 ctx->reset = devm_reset_control_get(dev, NULL);
937 if (IS_ERR(ctx->reset))
938 return PTR_ERR(ctx->reset);
939
940 ctx->noc_regmap =
941 syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon");
942 if (IS_ERR(ctx->noc_regmap)) {
943 DRM_ERROR("failed to get noc regmap\n");
944 return PTR_ERR(ctx->noc_regmap);
945 }
946
947 ctx->irq = platform_get_irq(pdev, 0);
948 if (ctx->irq < 0) {
949 DRM_ERROR("failed to get irq\n");
950 return -ENODEV;
951 }
952
953 ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core");
954 if (IS_ERR(ctx->ade_core_clk)) {
955 DRM_ERROR("failed to parse clk ADE_CORE\n");
956 return PTR_ERR(ctx->ade_core_clk);
957 }
958
959 ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg");
960 if (IS_ERR(ctx->media_noc_clk)) {
961 DRM_ERROR("failed to parse clk CODEC_JPEG\n");
962 return PTR_ERR(ctx->media_noc_clk);
963 }
964
965 ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix");
966 if (IS_ERR(ctx->ade_pix_clk)) {
967 DRM_ERROR("failed to parse clk ADE_PIX\n");
968 return PTR_ERR(ctx->ade_pix_clk);
969 }
970
971 return 0;
972}
973
974static int ade_drm_init(struct platform_device *pdev)
975{
976 struct drm_device *dev = platform_get_drvdata(pdev);
977 struct ade_data *ade;
978 struct ade_hw_ctx *ctx;
979 struct ade_crtc *acrtc;
980 struct ade_plane *aplane;
981 enum drm_plane_type type;
982 int ret;
983 int i;
984
985 ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL);
986 if (!ade) {
987 DRM_ERROR("failed to alloc ade_data\n");
988 return -ENOMEM;
989 }
990 platform_set_drvdata(pdev, ade);
991
992 ctx = &ade->ctx;
993 acrtc = &ade->acrtc;
994 acrtc->ctx = ctx;
995 acrtc->out_format = LDI_OUT_RGB_888;
996
997 ret = ade_dts_parse(pdev, ctx);
998 if (ret)
999 return ret;
1000
1001
1002
1003
1004
1005
1006 for (i = 0; i < ADE_CH_NUM; i++) {
1007 aplane = &ade->aplane[i];
1008 aplane->ch = i;
1009 aplane->ctx = ctx;
1010 type = i == PRIMARY_CH ? DRM_PLANE_TYPE_PRIMARY :
1011 DRM_PLANE_TYPE_OVERLAY;
1012
1013 ret = ade_plane_init(dev, aplane, type);
1014 if (ret)
1015 return ret;
1016 }
1017
1018
1019 ret = ade_crtc_init(dev, &acrtc->base, &ade->aplane[PRIMARY_CH].base);
1020 if (ret)
1021 return ret;
1022
1023
1024 ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler,
1025 IRQF_SHARED, dev->driver->name, acrtc);
1026 if (ret)
1027 return ret;
1028
1029 return 0;
1030}
1031
1032static void ade_drm_cleanup(struct platform_device *pdev)
1033{
1034}
1035
1036const struct kirin_dc_ops ade_dc_ops = {
1037 .init = ade_drm_init,
1038 .cleanup = ade_drm_cleanup
1039};
1040
