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29#include "i915_drv.h"
30#include "intel_uc.h"
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55#define SKL_FW_MAJOR 6
56#define SKL_FW_MINOR 1
57
58#define BXT_FW_MAJOR 8
59#define BXT_FW_MINOR 7
60
61#define KBL_FW_MAJOR 9
62#define KBL_FW_MINOR 14
63
64#define GLK_FW_MAJOR 10
65#define GLK_FW_MINOR 56
66
67#define GUC_FW_PATH(platform, major, minor) \
68 "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
69
70#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
71MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
72
73#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
74MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
75
76#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
77MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
78
79#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
80
81
82static u32 get_gttype(struct drm_i915_private *dev_priv)
83{
84
85 return 0;
86}
87
88static u32 get_core_family(struct drm_i915_private *dev_priv)
89{
90 u32 gen = INTEL_GEN(dev_priv);
91
92 switch (gen) {
93 case 9:
94 return GUC_CORE_FAMILY_GEN9;
95
96 default:
97 MISSING_CASE(gen);
98 return GUC_CORE_FAMILY_UNKNOWN;
99 }
100}
101
102
103
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105
106
107static void guc_params_init(struct drm_i915_private *dev_priv)
108{
109 struct intel_guc *guc = &dev_priv->guc;
110 u32 params[GUC_CTL_MAX_DWORDS];
111 int i;
112
113 memset(¶ms, 0, sizeof(params));
114
115 params[GUC_CTL_DEVICE_INFO] |=
116 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
117 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
118
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122
123
124 params[GUC_CTL_ARAT_HIGH] = 0;
125 params[GUC_CTL_ARAT_LOW] = 100000000;
126
127 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
128
129 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
130 GUC_CTL_VCS2_ENABLED;
131
132 params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
133
134 if (i915.guc_log_level >= 0) {
135 params[GUC_CTL_DEBUG] =
136 i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
137 } else
138 params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
139
140
141 if (i915.enable_guc_submission) {
142 u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
143 u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
144 u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
145
146 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
147 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
148
149 pgs >>= PAGE_SHIFT;
150 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
151 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
152
153 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
154
155
156 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
157 }
158
159 I915_WRITE(SOFT_SCRATCH(0), 0);
160
161 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
162 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
163}
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173
174static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
175 u32 *status)
176{
177 u32 val = I915_READ(GUC_STATUS);
178 u32 uk_val = val & GS_UKERNEL_MASK;
179 *status = val;
180 return (uk_val == GS_UKERNEL_READY ||
181 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
182}
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193
194static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
195 struct i915_vma *vma)
196{
197 struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
198 unsigned long offset;
199 struct sg_table *sg = vma->pages;
200 u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
201 int i, ret = 0;
202
203
204 offset = guc_fw->rsa_offset;
205
206
207 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
208 for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
209 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
210
211
212
213 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
214
215
216 offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
217 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
218 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
219
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224 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
225 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
226
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228 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
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238 ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
239
240 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
241 I915_READ(DMA_CTRL), status);
242
243 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
244 DRM_ERROR("GuC firmware signature verification failed\n");
245 ret = -ENOEXEC;
246 }
247
248 DRM_DEBUG_DRIVER("returning %d\n", ret);
249
250 return ret;
251}
252
253u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
254{
255 u32 wopcm_size = GUC_WOPCM_TOP;
256
257
258 if (IS_GEN9_LP(dev_priv))
259 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
260
261 return wopcm_size;
262}
263
264
265
266
267static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
268{
269 struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
270 struct i915_vma *vma;
271 int ret;
272
273 ret = i915_gem_object_set_to_gtt_domain(guc_fw->obj, false);
274 if (ret) {
275 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
276 return ret;
277 }
278
279 vma = i915_gem_object_ggtt_pin(guc_fw->obj, NULL, 0, 0,
280 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
281 if (IS_ERR(vma)) {
282 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
283 return PTR_ERR(vma);
284 }
285
286 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
287
288
289 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
290
291
292 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
293 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
294 ~GUC_ENABLE_MIA_CLOCK_GATING));
295 }
296
297
298 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
299 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
300
301 if (IS_GEN9_LP(dev_priv))
302 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
303 else
304 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
305
306 if (IS_GEN9(dev_priv)) {
307
308 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
309 I915_READ(GEN7_MISCCPCTL)));
310
311
312 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
313 }
314
315 guc_params_init(dev_priv);
316
317 ret = guc_ucode_xfer_dma(dev_priv, vma);
318
319 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
320
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325 i915_vma_unpin(vma);
326
327 return ret;
328}
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342
343int intel_guc_init_hw(struct intel_guc *guc)
344{
345 struct drm_i915_private *dev_priv = guc_to_i915(guc);
346 const char *fw_path = guc->fw.path;
347 int ret;
348
349 DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
350 fw_path,
351 intel_uc_fw_status_repr(guc->fw.fetch_status),
352 intel_uc_fw_status_repr(guc->fw.load_status));
353
354 if (guc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
355 return -EIO;
356
357 guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
358
359 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
360 intel_uc_fw_status_repr(guc->fw.fetch_status),
361 intel_uc_fw_status_repr(guc->fw.load_status));
362
363 ret = guc_ucode_xfer(dev_priv);
364
365 if (ret)
366 return -EAGAIN;
367
368 guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;
369
370 DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
371 i915.enable_guc_submission ? "submission enabled" : "loaded",
372 guc->fw.path,
373 guc->fw.major_ver_found, guc->fw.minor_ver_found);
374
375 return 0;
376}
377
378
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381
382
383
384int intel_guc_select_fw(struct intel_guc *guc)
385{
386 struct drm_i915_private *dev_priv = guc_to_i915(guc);
387
388 guc->fw.path = NULL;
389 guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
390 guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
391 guc->fw.type = INTEL_UC_FW_TYPE_GUC;
392
393 if (i915.guc_firmware_path) {
394 guc->fw.path = i915.guc_firmware_path;
395 guc->fw.major_ver_wanted = 0;
396 guc->fw.minor_ver_wanted = 0;
397 } else if (IS_SKYLAKE(dev_priv)) {
398 guc->fw.path = I915_SKL_GUC_UCODE;
399 guc->fw.major_ver_wanted = SKL_FW_MAJOR;
400 guc->fw.minor_ver_wanted = SKL_FW_MINOR;
401 } else if (IS_BROXTON(dev_priv)) {
402 guc->fw.path = I915_BXT_GUC_UCODE;
403 guc->fw.major_ver_wanted = BXT_FW_MAJOR;
404 guc->fw.minor_ver_wanted = BXT_FW_MINOR;
405 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
406 guc->fw.path = I915_KBL_GUC_UCODE;
407 guc->fw.major_ver_wanted = KBL_FW_MAJOR;
408 guc->fw.minor_ver_wanted = KBL_FW_MINOR;
409 } else if (IS_GEMINILAKE(dev_priv)) {
410 guc->fw.path = I915_GLK_GUC_UCODE;
411 guc->fw.major_ver_wanted = GLK_FW_MAJOR;
412 guc->fw.minor_ver_wanted = GLK_FW_MINOR;
413 } else {
414 DRM_ERROR("No GuC firmware known for platform with GuC!\n");
415 return -ENOENT;
416 }
417
418 return 0;
419}
420