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14#include <drm/drmP.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h>
19#include <drm/drm_of.h>
20#include <linux/clk.h>
21#include <linux/component.h>
22#include <linux/iopoll.h>
23#include <linux/irq.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/phy/phy.h>
27#include <linux/platform_device.h>
28#include <video/mipi_display.h>
29#include <video/videomode.h>
30
31#include "mtk_drm_ddp_comp.h"
32
33#define DSI_START 0x00
34
35#define DSI_INTEN 0x08
36
37#define DSI_INTSTA 0x0c
38#define LPRX_RD_RDY_INT_FLAG BIT(0)
39#define CMD_DONE_INT_FLAG BIT(1)
40#define TE_RDY_INT_FLAG BIT(2)
41#define VM_DONE_INT_FLAG BIT(3)
42#define EXT_TE_RDY_INT_FLAG BIT(4)
43#define DSI_BUSY BIT(31)
44
45#define DSI_CON_CTRL 0x10
46#define DSI_RESET BIT(0)
47#define DSI_EN BIT(1)
48
49#define DSI_MODE_CTRL 0x14
50#define MODE (3)
51#define CMD_MODE 0
52#define SYNC_PULSE_MODE 1
53#define SYNC_EVENT_MODE 2
54#define BURST_MODE 3
55#define FRM_MODE BIT(16)
56#define MIX_MODE BIT(17)
57
58#define DSI_TXRX_CTRL 0x18
59#define VC_NUM BIT(1)
60#define LANE_NUM (0xf << 2)
61#define DIS_EOT BIT(6)
62#define NULL_EN BIT(7)
63#define TE_FREERUN BIT(8)
64#define EXT_TE_EN BIT(9)
65#define EXT_TE_EDGE BIT(10)
66#define MAX_RTN_SIZE (0xf << 12)
67#define HSTX_CKLP_EN BIT(16)
68
69#define DSI_PSCTRL 0x1c
70#define DSI_PS_WC 0x3fff
71#define DSI_PS_SEL (3 << 16)
72#define PACKED_PS_16BIT_RGB565 (0 << 16)
73#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
74#define PACKED_PS_18BIT_RGB666 (2 << 16)
75#define PACKED_PS_24BIT_RGB888 (3 << 16)
76
77#define DSI_VSA_NL 0x20
78#define DSI_VBP_NL 0x24
79#define DSI_VFP_NL 0x28
80#define DSI_VACT_NL 0x2C
81#define DSI_HSA_WC 0x50
82#define DSI_HBP_WC 0x54
83#define DSI_HFP_WC 0x58
84
85#define DSI_CMDQ_SIZE 0x60
86#define CMDQ_SIZE 0x3f
87
88#define DSI_HSTX_CKL_WC 0x64
89
90#define DSI_RX_DATA0 0x74
91#define DSI_RX_DATA1 0x78
92#define DSI_RX_DATA2 0x7c
93#define DSI_RX_DATA3 0x80
94
95#define DSI_RACK 0x84
96#define RACK BIT(0)
97
98#define DSI_PHY_LCCON 0x104
99#define LC_HS_TX_EN BIT(0)
100#define LC_ULPM_EN BIT(1)
101#define LC_WAKEUP_EN BIT(2)
102
103#define DSI_PHY_LD0CON 0x108
104#define LD0_HS_TX_EN BIT(0)
105#define LD0_ULPM_EN BIT(1)
106#define LD0_WAKEUP_EN BIT(2)
107
108#define DSI_PHY_TIMECON0 0x110
109#define LPX (0xff << 0)
110#define HS_PREP (0xff << 8)
111#define HS_ZERO (0xff << 16)
112#define HS_TRAIL (0xff << 24)
113
114#define DSI_PHY_TIMECON1 0x114
115#define TA_GO (0xff << 0)
116#define TA_SURE (0xff << 8)
117#define TA_GET (0xff << 16)
118#define DA_HS_EXIT (0xff << 24)
119
120#define DSI_PHY_TIMECON2 0x118
121#define CONT_DET (0xff << 0)
122#define CLK_ZERO (0xff << 16)
123#define CLK_TRAIL (0xff << 24)
124
125#define DSI_PHY_TIMECON3 0x11c
126#define CLK_HS_PREP (0xff << 0)
127#define CLK_HS_POST (0xff << 8)
128#define CLK_HS_EXIT (0xff << 16)
129
130#define DSI_VM_CMD_CON 0x130
131#define VM_CMD_EN BIT(0)
132#define TS_VFP_EN BIT(5)
133
134#define DSI_CMDQ0 0x180
135#define CONFIG (0xff << 0)
136#define SHORT_PACKET 0
137#define LONG_PACKET 2
138#define BTA BIT(2)
139#define DATA_ID (0xff << 8)
140#define DATA_0 (0xff << 16)
141#define DATA_1 (0xff << 24)
142
143#define T_LPX 5
144#define T_HS_PREP 6
145#define T_HS_TRAIL 8
146#define T_HS_EXIT 7
147#define T_HS_ZERO 10
148
149#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
150
151#define MTK_DSI_HOST_IS_READ(type) \
152 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
153 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
154 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
155 (type == MIPI_DSI_DCS_READ))
156
157struct phy;
158
159struct mtk_dsi {
160 struct mtk_ddp_comp ddp_comp;
161 struct device *dev;
162 struct mipi_dsi_host host;
163 struct drm_encoder encoder;
164 struct drm_connector conn;
165 struct drm_panel *panel;
166 struct drm_bridge *bridge;
167 struct phy *phy;
168
169 void __iomem *regs;
170
171 struct clk *engine_clk;
172 struct clk *digital_clk;
173 struct clk *hs_clk;
174
175 u32 data_rate;
176
177 unsigned long mode_flags;
178 enum mipi_dsi_pixel_format format;
179 unsigned int lanes;
180 struct videomode vm;
181 int refcount;
182 bool enabled;
183 u32 irq_data;
184 wait_queue_head_t irq_wait_queue;
185};
186
187static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
188{
189 return container_of(e, struct mtk_dsi, encoder);
190}
191
192static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
193{
194 return container_of(c, struct mtk_dsi, conn);
195}
196
197static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
198{
199 return container_of(h, struct mtk_dsi, host);
200}
201
202static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
203{
204 u32 temp = readl(dsi->regs + offset);
205
206 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
207}
208
209static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
210{
211 u32 timcon0, timcon1, timcon2, timcon3;
212 u32 ui, cycle_time;
213
214 ui = 1000 / dsi->data_rate + 0x01;
215 cycle_time = 8000 / dsi->data_rate + 0x01;
216
217 timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
218 timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
219 T_HS_EXIT << 24;
220 timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
221 (NS_TO_CYCLE(0x150, cycle_time) << 16);
222 timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
223 NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
224
225 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
226 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
227 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
228 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
229}
230
231static void mtk_dsi_enable(struct mtk_dsi *dsi)
232{
233 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
234}
235
236static void mtk_dsi_disable(struct mtk_dsi *dsi)
237{
238 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
239}
240
241static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
242{
243 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
244 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
245}
246
247static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
248{
249 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
250 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
251}
252
253static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
254{
255 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
256 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
257 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
258}
259
260static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
261{
262 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
263 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
264}
265
266static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
267{
268 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
269 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
270 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
271}
272
273static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
274{
275 u32 tmp_reg1;
276
277 tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
278 return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
279}
280
281static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
282{
283 if (enter && !mtk_dsi_clk_hs_state(dsi))
284 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
285 else if (!enter && mtk_dsi_clk_hs_state(dsi))
286 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
287}
288
289static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
290{
291 u32 vid_mode = CMD_MODE;
292
293 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
294 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
295 vid_mode = BURST_MODE;
296 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
297 vid_mode = SYNC_PULSE_MODE;
298 else
299 vid_mode = SYNC_EVENT_MODE;
300 }
301
302 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
303}
304
305static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
306{
307 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
308 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
309}
310
311static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
312{
313 struct videomode *vm = &dsi->vm;
314 u32 dsi_buf_bpp, ps_wc;
315 u32 ps_bpp_mode;
316
317 if (dsi->format == MIPI_DSI_FMT_RGB565)
318 dsi_buf_bpp = 2;
319 else
320 dsi_buf_bpp = 3;
321
322 ps_wc = vm->hactive * dsi_buf_bpp;
323 ps_bpp_mode = ps_wc;
324
325 switch (dsi->format) {
326 case MIPI_DSI_FMT_RGB888:
327 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
328 break;
329 case MIPI_DSI_FMT_RGB666:
330 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
331 break;
332 case MIPI_DSI_FMT_RGB666_PACKED:
333 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
334 break;
335 case MIPI_DSI_FMT_RGB565:
336 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
337 break;
338 }
339
340 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
341 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
342 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
343}
344
345static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
346{
347 u32 tmp_reg;
348
349 switch (dsi->lanes) {
350 case 1:
351 tmp_reg = 1 << 2;
352 break;
353 case 2:
354 tmp_reg = 3 << 2;
355 break;
356 case 3:
357 tmp_reg = 7 << 2;
358 break;
359 case 4:
360 tmp_reg = 0xf << 2;
361 break;
362 default:
363 tmp_reg = 0xf << 2;
364 break;
365 }
366
367 tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
368 tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
369
370 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
371}
372
373static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
374{
375 u32 dsi_tmp_buf_bpp;
376 u32 tmp_reg;
377
378 switch (dsi->format) {
379 case MIPI_DSI_FMT_RGB888:
380 tmp_reg = PACKED_PS_24BIT_RGB888;
381 dsi_tmp_buf_bpp = 3;
382 break;
383 case MIPI_DSI_FMT_RGB666:
384 tmp_reg = LOOSELY_PS_18BIT_RGB666;
385 dsi_tmp_buf_bpp = 3;
386 break;
387 case MIPI_DSI_FMT_RGB666_PACKED:
388 tmp_reg = PACKED_PS_18BIT_RGB666;
389 dsi_tmp_buf_bpp = 3;
390 break;
391 case MIPI_DSI_FMT_RGB565:
392 tmp_reg = PACKED_PS_16BIT_RGB565;
393 dsi_tmp_buf_bpp = 2;
394 break;
395 default:
396 tmp_reg = PACKED_PS_24BIT_RGB888;
397 dsi_tmp_buf_bpp = 3;
398 break;
399 }
400
401 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
402 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
403}
404
405static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
406{
407 u32 horizontal_sync_active_byte;
408 u32 horizontal_backporch_byte;
409 u32 horizontal_frontporch_byte;
410 u32 dsi_tmp_buf_bpp;
411
412 struct videomode *vm = &dsi->vm;
413
414 if (dsi->format == MIPI_DSI_FMT_RGB565)
415 dsi_tmp_buf_bpp = 2;
416 else
417 dsi_tmp_buf_bpp = 3;
418
419 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
420 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
421 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
422 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
423
424 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
425
426 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
427 horizontal_backporch_byte =
428 (vm->hback_porch * dsi_tmp_buf_bpp - 10);
429 else
430 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
431 dsi_tmp_buf_bpp - 10);
432
433 horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
434
435 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
436 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
437 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
438
439 mtk_dsi_ps_control(dsi);
440}
441
442static void mtk_dsi_start(struct mtk_dsi *dsi)
443{
444 writel(0, dsi->regs + DSI_START);
445 writel(1, dsi->regs + DSI_START);
446}
447
448static void mtk_dsi_stop(struct mtk_dsi *dsi)
449{
450 writel(0, dsi->regs + DSI_START);
451}
452
453static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
454{
455 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
456}
457
458static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
459{
460 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
461
462 writel(inten, dsi->regs + DSI_INTEN);
463}
464
465static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
466{
467 dsi->irq_data |= irq_bit;
468}
469
470static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
471{
472 dsi->irq_data &= ~irq_bit;
473}
474
475static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
476 unsigned int timeout)
477{
478 s32 ret = 0;
479 unsigned long jiffies = msecs_to_jiffies(timeout);
480
481 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
482 dsi->irq_data & irq_flag,
483 jiffies);
484 if (ret == 0) {
485 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
486
487 mtk_dsi_enable(dsi);
488 mtk_dsi_reset_engine(dsi);
489 }
490
491 return ret;
492}
493
494static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
495{
496 struct mtk_dsi *dsi = dev_id;
497 u32 status, tmp;
498 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
499
500 status = readl(dsi->regs + DSI_INTSTA) & flag;
501
502 if (status) {
503 do {
504 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
505 tmp = readl(dsi->regs + DSI_INTSTA);
506 } while (tmp & DSI_BUSY);
507
508 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
509 mtk_dsi_irq_data_set(dsi, status);
510 wake_up_interruptible(&dsi->irq_wait_queue);
511 }
512
513 return IRQ_HANDLED;
514}
515
516static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
517{
518 mtk_dsi_irq_data_clear(dsi, irq_flag);
519 mtk_dsi_set_cmd_mode(dsi);
520
521 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
522 DRM_ERROR("failed to switch cmd mode\n");
523 return -ETIME;
524 } else {
525 return 0;
526 }
527}
528
529static int mtk_dsi_poweron(struct mtk_dsi *dsi)
530{
531 struct device *dev = dsi->dev;
532 int ret;
533 u64 pixel_clock, total_bits;
534 u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
535
536 if (++dsi->refcount != 1)
537 return 0;
538
539 switch (dsi->format) {
540 case MIPI_DSI_FMT_RGB565:
541 bit_per_pixel = 16;
542 break;
543 case MIPI_DSI_FMT_RGB666_PACKED:
544 bit_per_pixel = 18;
545 break;
546 case MIPI_DSI_FMT_RGB666:
547 case MIPI_DSI_FMT_RGB888:
548 default:
549 bit_per_pixel = 24;
550 break;
551 }
552
553
554
555
556
557
558
559
560 pixel_clock = dsi->vm.pixelclock * 1000;
561 htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
562 dsi->vm.hsync_len;
563 htotal_bits = htotal * bit_per_pixel;
564
565 overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
566 T_HS_EXIT;
567 overhead_bits = overhead_cycles * dsi->lanes * 8;
568 total_bits = htotal_bits + overhead_bits;
569
570 dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
571 htotal * dsi->lanes);
572
573 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
574 if (ret < 0) {
575 dev_err(dev, "Failed to set data rate: %d\n", ret);
576 goto err_refcount;
577 }
578
579 phy_power_on(dsi->phy);
580
581 ret = clk_prepare_enable(dsi->engine_clk);
582 if (ret < 0) {
583 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
584 goto err_phy_power_off;
585 }
586
587 ret = clk_prepare_enable(dsi->digital_clk);
588 if (ret < 0) {
589 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
590 goto err_disable_engine_clk;
591 }
592
593 mtk_dsi_enable(dsi);
594 mtk_dsi_reset_engine(dsi);
595 mtk_dsi_phy_timconfig(dsi);
596
597 mtk_dsi_rxtx_control(dsi);
598 mtk_dsi_ps_control_vact(dsi);
599 mtk_dsi_set_vm_cmd(dsi);
600 mtk_dsi_config_vdo_timing(dsi);
601 mtk_dsi_set_interrupt_enable(dsi);
602
603 mtk_dsi_clk_ulp_mode_leave(dsi);
604 mtk_dsi_lane0_ulp_mode_leave(dsi);
605 mtk_dsi_clk_hs_mode(dsi, 0);
606
607 if (dsi->panel) {
608 if (drm_panel_prepare(dsi->panel)) {
609 DRM_ERROR("failed to prepare the panel\n");
610 goto err_disable_digital_clk;
611 }
612 }
613
614 return 0;
615err_disable_digital_clk:
616 clk_disable_unprepare(dsi->digital_clk);
617err_disable_engine_clk:
618 clk_disable_unprepare(dsi->engine_clk);
619err_phy_power_off:
620 phy_power_off(dsi->phy);
621err_refcount:
622 dsi->refcount--;
623 return ret;
624}
625
626static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
627{
628 if (WARN_ON(dsi->refcount == 0))
629 return;
630
631 if (--dsi->refcount != 0)
632 return;
633
634 if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
635 if (dsi->panel) {
636 if (drm_panel_unprepare(dsi->panel)) {
637 DRM_ERROR("failed to unprepare the panel\n");
638 return;
639 }
640 }
641 }
642
643 mtk_dsi_reset_engine(dsi);
644 mtk_dsi_lane0_ulp_mode_enter(dsi);
645 mtk_dsi_clk_ulp_mode_enter(dsi);
646
647 mtk_dsi_disable(dsi);
648
649 clk_disable_unprepare(dsi->engine_clk);
650 clk_disable_unprepare(dsi->digital_clk);
651
652 phy_power_off(dsi->phy);
653}
654
655static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
656{
657 int ret;
658
659 if (dsi->enabled)
660 return;
661
662 ret = mtk_dsi_poweron(dsi);
663 if (ret < 0) {
664 DRM_ERROR("failed to power on dsi\n");
665 return;
666 }
667
668 mtk_dsi_set_mode(dsi);
669 mtk_dsi_clk_hs_mode(dsi, 1);
670
671 mtk_dsi_start(dsi);
672
673 if (dsi->panel) {
674 if (drm_panel_enable(dsi->panel)) {
675 DRM_ERROR("failed to enable the panel\n");
676 goto err_dsi_power_off;
677 }
678 }
679
680 dsi->enabled = true;
681
682 return;
683err_dsi_power_off:
684 mtk_dsi_stop(dsi);
685 mtk_dsi_poweroff(dsi);
686}
687
688static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
689{
690 if (!dsi->enabled)
691 return;
692
693 if (dsi->panel) {
694 if (drm_panel_disable(dsi->panel)) {
695 DRM_ERROR("failed to disable the panel\n");
696 return;
697 }
698 }
699
700 mtk_dsi_stop(dsi);
701 mtk_dsi_poweroff(dsi);
702
703 dsi->enabled = false;
704}
705
706static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
707{
708 drm_encoder_cleanup(encoder);
709}
710
711static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
712 .destroy = mtk_dsi_encoder_destroy,
713};
714
715static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
716 const struct drm_display_mode *mode,
717 struct drm_display_mode *adjusted_mode)
718{
719 return true;
720}
721
722static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
723 struct drm_display_mode *mode,
724 struct drm_display_mode *adjusted)
725{
726 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
727
728 dsi->vm.pixelclock = adjusted->clock;
729 dsi->vm.hactive = adjusted->hdisplay;
730 dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end;
731 dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay;
732 dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start;
733
734 dsi->vm.vactive = adjusted->vdisplay;
735 dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end;
736 dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay;
737 dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start;
738}
739
740static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
741{
742 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
743
744 mtk_output_dsi_disable(dsi);
745}
746
747static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
748{
749 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
750
751 mtk_output_dsi_enable(dsi);
752}
753
754static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
755{
756 struct mtk_dsi *dsi = connector_to_dsi(connector);
757
758 return drm_panel_get_modes(dsi->panel);
759}
760
761static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
762 .mode_fixup = mtk_dsi_encoder_mode_fixup,
763 .mode_set = mtk_dsi_encoder_mode_set,
764 .disable = mtk_dsi_encoder_disable,
765 .enable = mtk_dsi_encoder_enable,
766};
767
768static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
769 .dpms = drm_atomic_helper_connector_dpms,
770 .fill_modes = drm_helper_probe_single_connector_modes,
771 .destroy = drm_connector_cleanup,
772 .reset = drm_atomic_helper_connector_reset,
773 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
774 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
775};
776
777static const struct drm_connector_helper_funcs
778 mtk_dsi_connector_helper_funcs = {
779 .get_modes = mtk_dsi_connector_get_modes,
780};
781
782static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
783{
784 int ret;
785
786 ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
787 DRM_MODE_CONNECTOR_DSI);
788 if (ret) {
789 DRM_ERROR("Failed to connector init to drm\n");
790 return ret;
791 }
792
793 drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
794
795 dsi->conn.dpms = DRM_MODE_DPMS_OFF;
796 drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder);
797
798 if (dsi->panel) {
799 ret = drm_panel_attach(dsi->panel, &dsi->conn);
800 if (ret) {
801 DRM_ERROR("Failed to attach panel to drm\n");
802 goto err_connector_cleanup;
803 }
804 }
805
806 return 0;
807
808err_connector_cleanup:
809 drm_connector_cleanup(&dsi->conn);
810 return ret;
811}
812
813static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
814{
815 int ret;
816
817 ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
818 DRM_MODE_ENCODER_DSI, NULL);
819 if (ret) {
820 DRM_ERROR("Failed to encoder init to drm\n");
821 return ret;
822 }
823 drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
824
825
826
827
828
829 dsi->encoder.possible_crtcs = 1;
830
831
832 ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
833 if (ret) {
834 DRM_ERROR("Failed to attach bridge to drm\n");
835
836
837 ret = mtk_dsi_create_connector(drm, dsi);
838 if (ret)
839 goto err_encoder_cleanup;
840 }
841
842 return 0;
843
844err_encoder_cleanup:
845 drm_encoder_cleanup(&dsi->encoder);
846 return ret;
847}
848
849static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
850{
851 drm_encoder_cleanup(&dsi->encoder);
852
853 if (dsi->conn.dev)
854 drm_connector_cleanup(&dsi->conn);
855}
856
857static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
858{
859 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
860
861 mtk_dsi_poweron(dsi);
862}
863
864static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
865{
866 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
867
868 mtk_dsi_poweroff(dsi);
869}
870
871static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
872 .start = mtk_dsi_ddp_start,
873 .stop = mtk_dsi_ddp_stop,
874};
875
876static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
877 struct mipi_dsi_device *device)
878{
879 struct mtk_dsi *dsi = host_to_dsi(host);
880
881 dsi->lanes = device->lanes;
882 dsi->format = device->format;
883 dsi->mode_flags = device->mode_flags;
884
885 if (dsi->conn.dev)
886 drm_helper_hpd_irq_event(dsi->conn.dev);
887
888 return 0;
889}
890
891static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
892 struct mipi_dsi_device *device)
893{
894 struct mtk_dsi *dsi = host_to_dsi(host);
895
896 if (dsi->conn.dev)
897 drm_helper_hpd_irq_event(dsi->conn.dev);
898
899 return 0;
900}
901
902static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
903{
904 int ret;
905 u32 val;
906
907 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
908 4, 2000000);
909 if (ret) {
910 DRM_WARN("polling dsi wait not busy timeout!\n");
911
912 mtk_dsi_enable(dsi);
913 mtk_dsi_reset_engine(dsi);
914 }
915}
916
917static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
918{
919 switch (type) {
920 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
921 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
922 return 1;
923 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
924 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
925 return 2;
926 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
927 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
928 return read_data[1] + read_data[2] * 16;
929 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
930 DRM_INFO("type is 0x02, try again\n");
931 break;
932 default:
933 DRM_INFO("type(0x%x) not recognized\n", type);
934 break;
935 }
936
937 return 0;
938}
939
940static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
941{
942 const char *tx_buf = msg->tx_buf;
943 u8 config, cmdq_size, cmdq_off, type = msg->type;
944 u32 reg_val, cmdq_mask, i;
945
946 if (MTK_DSI_HOST_IS_READ(type))
947 config = BTA;
948 else
949 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
950
951 if (msg->tx_len > 2) {
952 cmdq_size = 1 + (msg->tx_len + 3) / 4;
953 cmdq_off = 4;
954 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
955 reg_val = (msg->tx_len << 16) | (type << 8) | config;
956 } else {
957 cmdq_size = 1;
958 cmdq_off = 2;
959 cmdq_mask = CONFIG | DATA_ID;
960 reg_val = (type << 8) | config;
961 }
962
963 for (i = 0; i < msg->tx_len; i++)
964 writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
965
966 mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
967 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
968}
969
970static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
971 const struct mipi_dsi_msg *msg, u8 flag)
972{
973 mtk_dsi_wait_for_idle(dsi);
974 mtk_dsi_irq_data_clear(dsi, flag);
975 mtk_dsi_cmdq(dsi, msg);
976 mtk_dsi_start(dsi);
977
978 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
979 return -ETIME;
980 else
981 return 0;
982}
983
984static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
985 const struct mipi_dsi_msg *msg)
986{
987 struct mtk_dsi *dsi = host_to_dsi(host);
988 u32 recv_cnt, i;
989 u8 read_data[16];
990 void *src_addr;
991 u8 irq_flag = CMD_DONE_INT_FLAG;
992
993 if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
994 DRM_ERROR("dsi engine is not command mode\n");
995 return -EINVAL;
996 }
997
998 if (MTK_DSI_HOST_IS_READ(msg->type))
999 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1000
1001 if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
1002 return -ETIME;
1003
1004 if (!MTK_DSI_HOST_IS_READ(msg->type))
1005 return 0;
1006
1007 if (!msg->rx_buf) {
1008 DRM_ERROR("dsi receive buffer size may be NULL\n");
1009 return -EINVAL;
1010 }
1011
1012 for (i = 0; i < 16; i++)
1013 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1014
1015 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1016
1017 if (recv_cnt > 2)
1018 src_addr = &read_data[4];
1019 else
1020 src_addr = &read_data[1];
1021
1022 if (recv_cnt > 10)
1023 recv_cnt = 10;
1024
1025 if (recv_cnt > msg->rx_len)
1026 recv_cnt = msg->rx_len;
1027
1028 if (recv_cnt)
1029 memcpy(msg->rx_buf, src_addr, recv_cnt);
1030
1031 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1032 recv_cnt, *((u8 *)(msg->tx_buf)));
1033
1034 return recv_cnt;
1035}
1036
1037static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1038 .attach = mtk_dsi_host_attach,
1039 .detach = mtk_dsi_host_detach,
1040 .transfer = mtk_dsi_host_transfer,
1041};
1042
1043static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
1044{
1045 int ret;
1046 struct drm_device *drm = data;
1047 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1048
1049 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1050 if (ret < 0) {
1051 dev_err(dev, "Failed to register component %s: %d\n",
1052 dev->of_node->full_name, ret);
1053 return ret;
1054 }
1055
1056 ret = mipi_dsi_host_register(&dsi->host);
1057 if (ret < 0) {
1058 dev_err(dev, "failed to register DSI host: %d\n", ret);
1059 goto err_ddp_comp_unregister;
1060 }
1061
1062 ret = mtk_dsi_create_conn_enc(drm, dsi);
1063 if (ret) {
1064 DRM_ERROR("Encoder create failed with %d\n", ret);
1065 goto err_unregister;
1066 }
1067
1068 return 0;
1069
1070err_unregister:
1071 mipi_dsi_host_unregister(&dsi->host);
1072err_ddp_comp_unregister:
1073 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1074 return ret;
1075}
1076
1077static void mtk_dsi_unbind(struct device *dev, struct device *master,
1078 void *data)
1079{
1080 struct drm_device *drm = data;
1081 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1082
1083 mtk_dsi_destroy_conn_enc(dsi);
1084 mipi_dsi_host_unregister(&dsi->host);
1085 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1086}
1087
1088static const struct component_ops mtk_dsi_component_ops = {
1089 .bind = mtk_dsi_bind,
1090 .unbind = mtk_dsi_unbind,
1091};
1092
1093static int mtk_dsi_probe(struct platform_device *pdev)
1094{
1095 struct mtk_dsi *dsi;
1096 struct device *dev = &pdev->dev;
1097 struct resource *regs;
1098 int irq_num;
1099 int comp_id;
1100 int ret;
1101
1102 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1103 if (!dsi)
1104 return -ENOMEM;
1105
1106 dsi->host.ops = &mtk_dsi_ops;
1107 dsi->host.dev = dev;
1108
1109 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1110 &dsi->panel, &dsi->bridge);
1111 if (ret)
1112 return ret;
1113
1114 dsi->engine_clk = devm_clk_get(dev, "engine");
1115 if (IS_ERR(dsi->engine_clk)) {
1116 ret = PTR_ERR(dsi->engine_clk);
1117 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1118 return ret;
1119 }
1120
1121 dsi->digital_clk = devm_clk_get(dev, "digital");
1122 if (IS_ERR(dsi->digital_clk)) {
1123 ret = PTR_ERR(dsi->digital_clk);
1124 dev_err(dev, "Failed to get digital clock: %d\n", ret);
1125 return ret;
1126 }
1127
1128 dsi->hs_clk = devm_clk_get(dev, "hs");
1129 if (IS_ERR(dsi->hs_clk)) {
1130 ret = PTR_ERR(dsi->hs_clk);
1131 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1132 return ret;
1133 }
1134
1135 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1136 dsi->regs = devm_ioremap_resource(dev, regs);
1137 if (IS_ERR(dsi->regs)) {
1138 ret = PTR_ERR(dsi->regs);
1139 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1140 return ret;
1141 }
1142
1143 dsi->phy = devm_phy_get(dev, "dphy");
1144 if (IS_ERR(dsi->phy)) {
1145 ret = PTR_ERR(dsi->phy);
1146 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1147 return ret;
1148 }
1149
1150 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1151 if (comp_id < 0) {
1152 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1153 return comp_id;
1154 }
1155
1156 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1157 &mtk_dsi_funcs);
1158 if (ret) {
1159 dev_err(dev, "Failed to initialize component: %d\n", ret);
1160 return ret;
1161 }
1162
1163 irq_num = platform_get_irq(pdev, 0);
1164 if (irq_num < 0) {
1165 dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1166 return -EPROBE_DEFER;
1167 }
1168
1169 irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1170 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1171 IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1172 if (ret) {
1173 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1174 return -EPROBE_DEFER;
1175 }
1176
1177 init_waitqueue_head(&dsi->irq_wait_queue);
1178
1179 platform_set_drvdata(pdev, dsi);
1180
1181 return component_add(&pdev->dev, &mtk_dsi_component_ops);
1182}
1183
1184static int mtk_dsi_remove(struct platform_device *pdev)
1185{
1186 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1187
1188 mtk_output_dsi_disable(dsi);
1189 component_del(&pdev->dev, &mtk_dsi_component_ops);
1190
1191 return 0;
1192}
1193
1194static const struct of_device_id mtk_dsi_of_match[] = {
1195 { .compatible = "mediatek,mt2701-dsi" },
1196 { .compatible = "mediatek,mt8173-dsi" },
1197 { },
1198};
1199
1200struct platform_driver mtk_dsi_driver = {
1201 .probe = mtk_dsi_probe,
1202 .remove = mtk_dsi_remove,
1203 .driver = {
1204 .name = "mtk-dsi",
1205 .of_match_table = mtk_dsi_of_match,
1206 },
1207};
1208
