linux/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c
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   1/*
   2 * Copyright (C) 2014 Red Hat
   3 * Author: Rob Clark <robdclark@gmail.com>
   4 * Author: Vinay Simha <vinaysimha@inforcecomputing.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License version 2 as published by
   8 * the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along with
  16 * this program.  If not, see <http://www.gnu.org/licenses/>.
  17 */
  18
  19#include <drm/drm_crtc.h>
  20#include <drm/drm_crtc_helper.h>
  21
  22#include "mdp4_kms.h"
  23
  24struct mdp4_lcdc_encoder {
  25        struct drm_encoder base;
  26        struct device_node *panel_node;
  27        struct drm_panel *panel;
  28        struct clk *lcdc_clk;
  29        unsigned long int pixclock;
  30        struct regulator *regs[3];
  31        bool enabled;
  32        uint32_t bsc;
  33};
  34#define to_mdp4_lcdc_encoder(x) container_of(x, struct mdp4_lcdc_encoder, base)
  35
  36static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
  37{
  38        struct msm_drm_private *priv = encoder->dev->dev_private;
  39        return to_mdp4_kms(to_mdp_kms(priv->kms));
  40}
  41
  42#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
  43#include <mach/board.h>
  44static void bs_init(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder)
  45{
  46        struct drm_device *dev = mdp4_lcdc_encoder->base.dev;
  47        struct lcdc_platform_data *lcdc_pdata = mdp4_find_pdata("lvds.0");
  48
  49        if (!lcdc_pdata) {
  50                dev_err(dev->dev, "could not find lvds pdata\n");
  51                return;
  52        }
  53
  54        if (lcdc_pdata->bus_scale_table) {
  55                mdp4_lcdc_encoder->bsc = msm_bus_scale_register_client(
  56                                lcdc_pdata->bus_scale_table);
  57                DBG("lvds : bus scale client: %08x", mdp4_lcdc_encoder->bsc);
  58        }
  59}
  60
  61static void bs_fini(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder)
  62{
  63        if (mdp4_lcdc_encoder->bsc) {
  64                msm_bus_scale_unregister_client(mdp4_lcdc_encoder->bsc);
  65                mdp4_lcdc_encoder->bsc = 0;
  66        }
  67}
  68
  69static void bs_set(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder, int idx)
  70{
  71        if (mdp4_lcdc_encoder->bsc) {
  72                DBG("set bus scaling: %d", idx);
  73                msm_bus_scale_client_update_request(mdp4_lcdc_encoder->bsc, idx);
  74        }
  75}
  76#else
  77static void bs_init(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder) {}
  78static void bs_fini(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder) {}
  79static void bs_set(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder, int idx) {}
  80#endif
  81
  82static void mdp4_lcdc_encoder_destroy(struct drm_encoder *encoder)
  83{
  84        struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
  85                        to_mdp4_lcdc_encoder(encoder);
  86        bs_fini(mdp4_lcdc_encoder);
  87        drm_encoder_cleanup(encoder);
  88        kfree(mdp4_lcdc_encoder);
  89}
  90
  91static const struct drm_encoder_funcs mdp4_lcdc_encoder_funcs = {
  92        .destroy = mdp4_lcdc_encoder_destroy,
  93};
  94
  95/* this should probably be a helper: */
  96static struct drm_connector *get_connector(struct drm_encoder *encoder)
  97{
  98        struct drm_device *dev = encoder->dev;
  99        struct drm_connector *connector;
 100
 101        list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 102                if (connector->encoder == encoder)
 103                        return connector;
 104
 105        return NULL;
 106}
 107
 108static void setup_phy(struct drm_encoder *encoder)
 109{
 110        struct drm_device *dev = encoder->dev;
 111        struct drm_connector *connector = get_connector(encoder);
 112        struct mdp4_kms *mdp4_kms = get_kms(encoder);
 113        uint32_t lvds_intf = 0, lvds_phy_cfg0 = 0;
 114        int bpp, nchan, swap;
 115
 116        if (!connector)
 117                return;
 118
 119        bpp = 3 * connector->display_info.bpc;
 120
 121        if (!bpp)
 122                bpp = 18;
 123
 124        /* TODO, these should come from panel somehow: */
 125        nchan = 1;
 126        swap = 0;
 127
 128        switch (bpp) {
 129        case 24:
 130                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
 131                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x08) |
 132                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x05) |
 133                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x04) |
 134                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x03));
 135                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),
 136                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x02) |
 137                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x01) |
 138                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x00));
 139                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),
 140                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x11) |
 141                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x10) |
 142                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x0d) |
 143                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0c));
 144                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),
 145                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0b) |
 146                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x0a) |
 147                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x09));
 148                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),
 149                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1a) |
 150                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x19) |
 151                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x18) |
 152                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x15));
 153                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),
 154                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x14) |
 155                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x13) |
 156                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x12));
 157                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3),
 158                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1b) |
 159                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x17) |
 160                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x16) |
 161                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0f));
 162                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3),
 163                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0e) |
 164                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x07) |
 165                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x06));
 166                if (nchan == 2) {
 167                        lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN |
 168                                        MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN |
 169                                        MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN |
 170                                        MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN |
 171                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN |
 172                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
 173                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
 174                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
 175                } else {
 176                        lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN |
 177                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
 178                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
 179                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
 180                }
 181                break;
 182
 183        case 18:
 184                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
 185                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x0a) |
 186                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x07) |
 187                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x06) |
 188                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x05));
 189                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),
 190                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x04) |
 191                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x03) |
 192                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x02));
 193                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),
 194                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x13) |
 195                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x12) |
 196                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x0f) |
 197                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x0e));
 198                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),
 199                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x0d) |
 200                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x0c) |
 201                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x0b));
 202                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),
 203                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x1a) |
 204                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x19) |
 205                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(0x18) |
 206                                MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(0x17));
 207                mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),
 208                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(0x16) |
 209                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(0x15) |
 210                                MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(0x14));
 211                if (nchan == 2) {
 212                        lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN |
 213                                        MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN |
 214                                        MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN |
 215                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
 216                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
 217                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
 218                } else {
 219                        lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
 220                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN |
 221                                        MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN;
 222                }
 223                lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT;
 224                break;
 225
 226        default:
 227                dev_err(dev->dev, "unknown bpp: %d\n", bpp);
 228                return;
 229        }
 230
 231        switch (nchan) {
 232        case 1:
 233                lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0;
 234                lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN |
 235                                MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL;
 236                break;
 237        case 2:
 238                lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0 |
 239                                MDP4_LVDS_PHY_CFG0_CHANNEL1;
 240                lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN |
 241                                MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN;
 242                break;
 243        default:
 244                dev_err(dev->dev, "unknown # of channels: %d\n", nchan);
 245                return;
 246        }
 247
 248        if (swap)
 249                lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP;
 250
 251        lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_ENABLE;
 252
 253        mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);
 254        mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_INTF_CTL, lvds_intf);
 255        mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG2, 0x30);
 256
 257        mb();
 258        udelay(1);
 259        lvds_phy_cfg0 |= MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE;
 260        mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);
 261}
 262
 263static void mdp4_lcdc_encoder_mode_set(struct drm_encoder *encoder,
 264                struct drm_display_mode *mode,
 265                struct drm_display_mode *adjusted_mode)
 266{
 267        struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
 268                        to_mdp4_lcdc_encoder(encoder);
 269        struct mdp4_kms *mdp4_kms = get_kms(encoder);
 270        uint32_t lcdc_hsync_skew, vsync_period, vsync_len, ctrl_pol;
 271        uint32_t display_v_start, display_v_end;
 272        uint32_t hsync_start_x, hsync_end_x;
 273
 274        mode = adjusted_mode;
 275
 276        DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 277                        mode->base.id, mode->name,
 278                        mode->vrefresh, mode->clock,
 279                        mode->hdisplay, mode->hsync_start,
 280                        mode->hsync_end, mode->htotal,
 281                        mode->vdisplay, mode->vsync_start,
 282                        mode->vsync_end, mode->vtotal,
 283                        mode->type, mode->flags);
 284
 285        mdp4_lcdc_encoder->pixclock = mode->clock * 1000;
 286
 287        DBG("pixclock=%lu", mdp4_lcdc_encoder->pixclock);
 288
 289        ctrl_pol = 0;
 290        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 291                ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW;
 292        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 293                ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW;
 294        /* probably need to get DATA_EN polarity from panel.. */
 295
 296        lcdc_hsync_skew = 0;  /* get this from panel? */
 297
 298        hsync_start_x = (mode->htotal - mode->hsync_start);
 299        hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
 300
 301        vsync_period = mode->vtotal * mode->htotal;
 302        vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
 303        display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew;
 304        display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_skew - 1;
 305
 306        mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL,
 307                        MDP4_LCDC_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
 308                        MDP4_LCDC_HSYNC_CTRL_PERIOD(mode->htotal));
 309        mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_PERIOD, vsync_period);
 310        mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_LEN, vsync_len);
 311        mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL,
 312                        MDP4_LCDC_DISPLAY_HCTRL_START(hsync_start_x) |
 313                        MDP4_LCDC_DISPLAY_HCTRL_END(hsync_end_x));
 314        mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start);
 315        mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end);
 316        mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0);
 317        mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR,
 318                        MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY |
 319                        MDP4_LCDC_UNDERFLOW_CLR_COLOR(0xff));
 320        mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_SKEW, lcdc_hsync_skew);
 321        mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol);
 322        mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL,
 323                        MDP4_LCDC_ACTIVE_HCTL_START(0) |
 324                        MDP4_LCDC_ACTIVE_HCTL_END(0));
 325        mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VSTART, 0);
 326        mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VEND, 0);
 327}
 328
 329static void mdp4_lcdc_encoder_disable(struct drm_encoder *encoder)
 330{
 331        struct drm_device *dev = encoder->dev;
 332        struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
 333                        to_mdp4_lcdc_encoder(encoder);
 334        struct mdp4_kms *mdp4_kms = get_kms(encoder);
 335        struct drm_panel *panel;
 336        int i, ret;
 337
 338        if (WARN_ON(!mdp4_lcdc_encoder->enabled))
 339                return;
 340
 341        mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 342
 343        panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node);
 344        if (panel) {
 345                drm_panel_disable(panel);
 346                drm_panel_unprepare(panel);
 347        }
 348
 349        /*
 350         * Wait for a vsync so we know the ENABLE=0 latched before
 351         * the (connector) source of the vsync's gets disabled,
 352         * otherwise we end up in a funny state if we re-enable
 353         * before the disable latches, which results that some of
 354         * the settings changes for the new modeset (like new
 355         * scanout buffer) don't latch properly..
 356         */
 357        mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC);
 358
 359        clk_disable_unprepare(mdp4_lcdc_encoder->lcdc_clk);
 360
 361        for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
 362                ret = regulator_disable(mdp4_lcdc_encoder->regs[i]);
 363                if (ret)
 364                        dev_err(dev->dev, "failed to disable regulator: %d\n", ret);
 365        }
 366
 367        bs_set(mdp4_lcdc_encoder, 0);
 368
 369        mdp4_lcdc_encoder->enabled = false;
 370}
 371
 372static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)
 373{
 374        struct drm_device *dev = encoder->dev;
 375        struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
 376                        to_mdp4_lcdc_encoder(encoder);
 377        unsigned long pc = mdp4_lcdc_encoder->pixclock;
 378        struct mdp4_kms *mdp4_kms = get_kms(encoder);
 379        struct drm_panel *panel;
 380        int i, ret;
 381
 382        if (WARN_ON(mdp4_lcdc_encoder->enabled))
 383                return;
 384
 385        /* TODO: hard-coded for 18bpp: */
 386        mdp4_crtc_set_config(encoder->crtc,
 387                        MDP4_DMA_CONFIG_R_BPC(BPC6) |
 388                        MDP4_DMA_CONFIG_G_BPC(BPC6) |
 389                        MDP4_DMA_CONFIG_B_BPC(BPC6) |
 390                        MDP4_DMA_CONFIG_PACK_ALIGN_MSB |
 391                        MDP4_DMA_CONFIG_PACK(0x21) |
 392                        MDP4_DMA_CONFIG_DEFLKR_EN |
 393                        MDP4_DMA_CONFIG_DITHER_EN);
 394        mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0);
 395
 396        bs_set(mdp4_lcdc_encoder, 1);
 397
 398        for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
 399                ret = regulator_enable(mdp4_lcdc_encoder->regs[i]);
 400                if (ret)
 401                        dev_err(dev->dev, "failed to enable regulator: %d\n", ret);
 402        }
 403
 404        DBG("setting lcdc_clk=%lu", pc);
 405        ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
 406        if (ret)
 407                dev_err(dev->dev, "failed to configure lcdc_clk: %d\n", ret);
 408        ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
 409        if (ret)
 410                dev_err(dev->dev, "failed to enable lcdc_clk: %d\n", ret);
 411
 412        panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node);
 413        if (panel) {
 414                drm_panel_prepare(panel);
 415                drm_panel_enable(panel);
 416        }
 417
 418        setup_phy(encoder);
 419
 420        mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);
 421
 422        mdp4_lcdc_encoder->enabled = true;
 423}
 424
 425static const struct drm_encoder_helper_funcs mdp4_lcdc_encoder_helper_funcs = {
 426        .mode_set = mdp4_lcdc_encoder_mode_set,
 427        .disable = mdp4_lcdc_encoder_disable,
 428        .enable = mdp4_lcdc_encoder_enable,
 429};
 430
 431long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate)
 432{
 433        struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
 434                        to_mdp4_lcdc_encoder(encoder);
 435        return clk_round_rate(mdp4_lcdc_encoder->lcdc_clk, rate);
 436}
 437
 438/* initialize encoder */
 439struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
 440                struct device_node *panel_node)
 441{
 442        struct drm_encoder *encoder = NULL;
 443        struct mdp4_lcdc_encoder *mdp4_lcdc_encoder;
 444        struct regulator *reg;
 445        int ret;
 446
 447        mdp4_lcdc_encoder = kzalloc(sizeof(*mdp4_lcdc_encoder), GFP_KERNEL);
 448        if (!mdp4_lcdc_encoder) {
 449                ret = -ENOMEM;
 450                goto fail;
 451        }
 452
 453        mdp4_lcdc_encoder->panel_node = panel_node;
 454
 455        encoder = &mdp4_lcdc_encoder->base;
 456
 457        drm_encoder_init(dev, encoder, &mdp4_lcdc_encoder_funcs,
 458                         DRM_MODE_ENCODER_LVDS, NULL);
 459        drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs);
 460
 461        /* TODO: do we need different pll in other cases? */
 462        mdp4_lcdc_encoder->lcdc_clk = mpd4_lvds_pll_init(dev);
 463        if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) {
 464                dev_err(dev->dev, "failed to get lvds_clk\n");
 465                ret = PTR_ERR(mdp4_lcdc_encoder->lcdc_clk);
 466                goto fail;
 467        }
 468
 469        /* TODO: different regulators in other cases? */
 470        reg = devm_regulator_get(dev->dev, "lvds-vccs-3p3v");
 471        if (IS_ERR(reg)) {
 472                ret = PTR_ERR(reg);
 473                dev_err(dev->dev, "failed to get lvds-vccs-3p3v: %d\n", ret);
 474                goto fail;
 475        }
 476        mdp4_lcdc_encoder->regs[0] = reg;
 477
 478        reg = devm_regulator_get(dev->dev, "lvds-pll-vdda");
 479        if (IS_ERR(reg)) {
 480                ret = PTR_ERR(reg);
 481                dev_err(dev->dev, "failed to get lvds-pll-vdda: %d\n", ret);
 482                goto fail;
 483        }
 484        mdp4_lcdc_encoder->regs[1] = reg;
 485
 486        reg = devm_regulator_get(dev->dev, "lvds-vdda");
 487        if (IS_ERR(reg)) {
 488                ret = PTR_ERR(reg);
 489                dev_err(dev->dev, "failed to get lvds-vdda: %d\n", ret);
 490                goto fail;
 491        }
 492        mdp4_lcdc_encoder->regs[2] = reg;
 493
 494        bs_init(mdp4_lcdc_encoder);
 495
 496        return encoder;
 497
 498fail:
 499        if (encoder)
 500                mdp4_lcdc_encoder_destroy(encoder);
 501
 502        return ERR_PTR(ret);
 503}
 504