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11#define DSS_SUBSYS_NAME "HDMIWP"
12
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17#include <linux/seq_file.h>
18
19#include "omapdss.h"
20#include "dss.h"
21#include "hdmi.h"
22
23void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
24{
25#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
26
27 DUMPREG(HDMI_WP_REVISION);
28 DUMPREG(HDMI_WP_SYSCONFIG);
29 DUMPREG(HDMI_WP_IRQSTATUS_RAW);
30 DUMPREG(HDMI_WP_IRQSTATUS);
31 DUMPREG(HDMI_WP_IRQENABLE_SET);
32 DUMPREG(HDMI_WP_IRQENABLE_CLR);
33 DUMPREG(HDMI_WP_IRQWAKEEN);
34 DUMPREG(HDMI_WP_PWR_CTRL);
35 DUMPREG(HDMI_WP_DEBOUNCE);
36 DUMPREG(HDMI_WP_VIDEO_CFG);
37 DUMPREG(HDMI_WP_VIDEO_SIZE);
38 DUMPREG(HDMI_WP_VIDEO_TIMING_H);
39 DUMPREG(HDMI_WP_VIDEO_TIMING_V);
40 DUMPREG(HDMI_WP_CLK);
41 DUMPREG(HDMI_WP_AUDIO_CFG);
42 DUMPREG(HDMI_WP_AUDIO_CFG2);
43 DUMPREG(HDMI_WP_AUDIO_CTRL);
44 DUMPREG(HDMI_WP_AUDIO_DATA);
45}
46
47u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
48{
49 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
50}
51
52void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
53{
54 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
55
56 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
57}
58
59void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
60{
61 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
62}
63
64void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
65{
66 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
67}
68
69
70int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
71{
72
73 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
74 return 0;
75
76
77 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
78
79
80 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
81 != val) {
82 DSSERR("Failed to set PHY power mode to %d\n", val);
83 return -ETIMEDOUT;
84 }
85
86 return 0;
87}
88
89
90int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
91{
92
93 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
94
95
96 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
97 != val) {
98 DSSERR("Failed to set PLL_PWR_STATUS\n");
99 return -ETIMEDOUT;
100 }
101
102 return 0;
103}
104
105int hdmi_wp_video_start(struct hdmi_wp_data *wp)
106{
107 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
108
109 return 0;
110}
111
112void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
113{
114 int i;
115
116 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
117
118 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
119
120 for (i = 0; i < 50; ++i) {
121 u32 v;
122
123 msleep(20);
124
125 v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
126 if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
127 return;
128 }
129
130 DSSERR("no HDMI FRAMEDONE when disabling output\n");
131}
132
133void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
134 struct hdmi_video_format *video_fmt)
135{
136 u32 l = 0;
137
138 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
139 10, 8);
140
141 l |= FLD_VAL(video_fmt->y_res, 31, 16);
142 l |= FLD_VAL(video_fmt->x_res, 15, 0);
143 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
144}
145
146void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
147 struct videomode *vm)
148{
149 u32 r;
150 bool vsync_inv, hsync_inv;
151 DSSDBG("Enter hdmi_wp_video_config_interface\n");
152
153 vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW);
154 hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);
155
156 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
157 r = FLD_MOD(r, 1, 7, 7);
158 r = FLD_MOD(r, 1, 6, 6);
159 r = FLD_MOD(r, vsync_inv, 5, 5);
160 r = FLD_MOD(r, hsync_inv, 4, 4);
161 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
162 r = FLD_MOD(r, 1, 1, 0);
163 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
164}
165
166void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
167 struct videomode *vm)
168{
169 u32 timing_h = 0;
170 u32 timing_v = 0;
171 unsigned hsync_len_offset = 1;
172
173 DSSDBG("Enter hdmi_wp_video_config_timing\n");
174
175
176
177
178
179
180
181 if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
182 omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
183 omapdss_get_version() == OMAPDSS_VER_OMAP4)
184 hsync_len_offset = 0;
185
186 timing_h |= FLD_VAL(vm->hback_porch, 31, 20);
187 timing_h |= FLD_VAL(vm->hfront_porch, 19, 8);
188 timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0);
189 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
190
191 timing_v |= FLD_VAL(vm->vback_porch, 31, 20);
192 timing_v |= FLD_VAL(vm->vfront_porch, 19, 8);
193 timing_v |= FLD_VAL(vm->vsync_len, 7, 0);
194 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
195}
196
197void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
198 struct videomode *vm, struct hdmi_config *param)
199{
200 DSSDBG("Enter hdmi_wp_video_init_format\n");
201
202 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
203 video_fmt->y_res = param->vm.vactive;
204 video_fmt->x_res = param->vm.hactive;
205
206 vm->hback_porch = param->vm.hback_porch;
207 vm->hfront_porch = param->vm.hfront_porch;
208 vm->hsync_len = param->vm.hsync_len;
209 vm->vback_porch = param->vm.vback_porch;
210 vm->vfront_porch = param->vm.vfront_porch;
211 vm->vsync_len = param->vm.vsync_len;
212
213 vm->flags = param->vm.flags;
214
215 if (param->vm.flags & DISPLAY_FLAGS_INTERLACED) {
216 video_fmt->y_res /= 2;
217 vm->vback_porch /= 2;
218 vm->vfront_porch /= 2;
219 vm->vsync_len /= 2;
220 }
221
222 if (param->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
223 video_fmt->x_res *= 2;
224 vm->hfront_porch *= 2;
225 vm->hsync_len *= 2;
226 vm->hback_porch *= 2;
227 }
228}
229
230void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
231 struct hdmi_audio_format *aud_fmt)
232{
233 u32 r;
234
235 DSSDBG("Enter hdmi_wp_audio_config_format\n");
236
237 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
238 if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
239 omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
240 omapdss_get_version() == OMAPDSS_VER_OMAP4) {
241 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
242 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
243 }
244 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
245 r = FLD_MOD(r, aud_fmt->type, 4, 4);
246 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
247 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
248 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
249 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
250 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
251}
252
253void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
254 struct hdmi_audio_dma *aud_dma)
255{
256 u32 r;
257
258 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
259
260 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
261 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
262 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
263 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
264
265 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
266 r = FLD_MOD(r, aud_dma->mode, 9, 9);
267 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
268 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
269}
270
271int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
272{
273 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
274
275 return 0;
276}
277
278int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
279{
280 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
281
282 return 0;
283}
284
285int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
286{
287 struct resource *res;
288
289 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
290 wp->base = devm_ioremap_resource(&pdev->dev, res);
291 if (IS_ERR(wp->base))
292 return PTR_ERR(wp->base);
293
294 wp->phys_base = res->start;
295
296 return 0;
297}
298
299phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
300{
301 return wp->phys_base + HDMI_WP_AUDIO_DATA;
302}
303
