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9#include <linux/reservation.h>
10#include <drm/drmP.h>
11#include <drm/drm_encoder.h>
12#include <drm/drm_gem_cma_helper.h>
13
14struct vc4_dev {
15 struct drm_device *dev;
16
17 struct vc4_hdmi *hdmi;
18 struct vc4_hvs *hvs;
19 struct vc4_v3d *v3d;
20 struct vc4_dpi *dpi;
21 struct vc4_dsi *dsi1;
22 struct vc4_vec *vec;
23
24 struct drm_fbdev_cma *fbdev;
25
26 struct vc4_hang_state *hang_state;
27
28
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30
31
32 struct vc4_bo_cache {
33
34
35
36
37 struct list_head *size_list;
38 uint32_t size_list_size;
39
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42
43
44 struct list_head time_list;
45 struct work_struct time_work;
46 struct timer_list time_timer;
47 } bo_cache;
48
49 struct vc4_bo_stats {
50 u32 num_allocated;
51 u32 size_allocated;
52 u32 num_cached;
53 u32 size_cached;
54 } bo_stats;
55
56
57 struct mutex bo_lock;
58
59 uint64_t dma_fence_context;
60
61
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63
64 uint64_t emit_seqno;
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68
69 uint64_t finished_seqno;
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74
75 struct list_head bin_job_list;
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82 struct list_head render_job_list;
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86
87 struct list_head job_done_list;
88
89
90
91 spinlock_t job_lock;
92 wait_queue_head_t job_wait_queue;
93 struct work_struct job_done_work;
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96
97
98 struct list_head seqno_cb_list;
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102
103
104 struct vc4_bo *bin_bo;
105
106
107 uint32_t bin_alloc_size;
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111
112 uint32_t bin_alloc_used;
113
114
115 uint32_t bin_alloc_overflow;
116
117 struct work_struct overflow_mem_work;
118
119 int power_refcount;
120
121
122 struct mutex power_lock;
123
124 struct {
125 struct timer_list timer;
126 struct work_struct reset_work;
127 } hangcheck;
128
129 struct semaphore async_modeset;
130};
131
132static inline struct vc4_dev *
133to_vc4_dev(struct drm_device *dev)
134{
135 return (struct vc4_dev *)dev->dev_private;
136}
137
138struct vc4_bo {
139 struct drm_gem_cma_object base;
140
141
142 uint64_t seqno;
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148
149 uint64_t write_seqno;
150
151 bool t_format;
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154
155
156 struct list_head unref_head;
157
158
159 unsigned long free_time;
160
161
162 struct list_head size_head;
163
164
165
166
167 struct vc4_validated_shader_info *validated_shader;
168
169
170 struct reservation_object *resv;
171 struct reservation_object _resv;
172};
173
174static inline struct vc4_bo *
175to_vc4_bo(struct drm_gem_object *bo)
176{
177 return (struct vc4_bo *)bo;
178}
179
180struct vc4_fence {
181 struct dma_fence base;
182 struct drm_device *dev;
183
184 uint64_t seqno;
185};
186
187static inline struct vc4_fence *
188to_vc4_fence(struct dma_fence *fence)
189{
190 return (struct vc4_fence *)fence;
191}
192
193struct vc4_seqno_cb {
194 struct work_struct work;
195 uint64_t seqno;
196 void (*func)(struct vc4_seqno_cb *cb);
197};
198
199struct vc4_v3d {
200 struct vc4_dev *vc4;
201 struct platform_device *pdev;
202 void __iomem *regs;
203 struct clk *clk;
204};
205
206struct vc4_hvs {
207 struct platform_device *pdev;
208 void __iomem *regs;
209 u32 __iomem *dlist;
210
211
212
213
214 struct drm_mm dlist_mm;
215
216 struct drm_mm lbm_mm;
217 spinlock_t mm_lock;
218
219 struct drm_mm_node mitchell_netravali_filter;
220};
221
222struct vc4_plane {
223 struct drm_plane base;
224};
225
226static inline struct vc4_plane *
227to_vc4_plane(struct drm_plane *plane)
228{
229 return (struct vc4_plane *)plane;
230}
231
232enum vc4_encoder_type {
233 VC4_ENCODER_TYPE_NONE,
234 VC4_ENCODER_TYPE_HDMI,
235 VC4_ENCODER_TYPE_VEC,
236 VC4_ENCODER_TYPE_DSI0,
237 VC4_ENCODER_TYPE_DSI1,
238 VC4_ENCODER_TYPE_SMI,
239 VC4_ENCODER_TYPE_DPI,
240};
241
242struct vc4_encoder {
243 struct drm_encoder base;
244 enum vc4_encoder_type type;
245 u32 clock_select;
246};
247
248static inline struct vc4_encoder *
249to_vc4_encoder(struct drm_encoder *encoder)
250{
251 return container_of(encoder, struct vc4_encoder, base);
252}
253
254#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
255#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
256#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
257#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
258
259struct vc4_exec_info {
260
261 uint64_t seqno;
262
263
264 uint64_t bin_dep_seqno;
265
266 struct dma_fence *fence;
267
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270
271 uint32_t last_ct0ca, last_ct1ca;
272
273
274 struct drm_vc4_submit_cl *args;
275
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279 struct drm_gem_cma_object **bo;
280 uint32_t bo_count;
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285
286 struct drm_gem_cma_object *rcl_write_bo[4];
287 uint32_t rcl_write_bo_count;
288
289
290 struct list_head head;
291
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294
295 struct list_head unref_list;
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300 uint32_t bo_index[2];
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305 struct drm_gem_cma_object *exec_bo;
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312
313 struct vc4_shader_state {
314 uint32_t addr;
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317
318 uint32_t max_index;
319 } *shader_state;
320
321
322 uint32_t shader_state_size;
323
324 uint32_t shader_state_count;
325
326 bool found_tile_binning_mode_config_packet;
327 bool found_start_tile_binning_packet;
328 bool found_increment_semaphore_packet;
329 bool found_flush;
330 uint8_t bin_tiles_x, bin_tiles_y;
331
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334 uint32_t tile_alloc_offset;
335
336 uint32_t bin_slots;
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342 uint32_t ct0ca, ct0ea;
343 uint32_t ct1ca, ct1ea;
344
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346 void *bin_u;
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353 void *shader_rec_u;
354 void *shader_rec_v;
355 uint32_t shader_rec_p;
356 uint32_t shader_rec_size;
357
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361 void *uniforms_u;
362 void *uniforms_v;
363 uint32_t uniforms_p;
364 uint32_t uniforms_size;
365};
366
367static inline struct vc4_exec_info *
368vc4_first_bin_job(struct vc4_dev *vc4)
369{
370 return list_first_entry_or_null(&vc4->bin_job_list,
371 struct vc4_exec_info, head);
372}
373
374static inline struct vc4_exec_info *
375vc4_first_render_job(struct vc4_dev *vc4)
376{
377 return list_first_entry_or_null(&vc4->render_job_list,
378 struct vc4_exec_info, head);
379}
380
381static inline struct vc4_exec_info *
382vc4_last_render_job(struct vc4_dev *vc4)
383{
384 if (list_empty(&vc4->render_job_list))
385 return NULL;
386 return list_last_entry(&vc4->render_job_list,
387 struct vc4_exec_info, head);
388}
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404struct vc4_texture_sample_info {
405 bool is_direct;
406 uint32_t p_offset[4];
407};
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418
419struct vc4_validated_shader_info {
420 uint32_t uniforms_size;
421 uint32_t uniforms_src_size;
422 uint32_t num_texture_samples;
423 struct vc4_texture_sample_info *texture_samples;
424
425 uint32_t num_uniform_addr_offsets;
426 uint32_t *uniform_addr_offsets;
427
428 bool is_threaded;
429};
430
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437
438
439#define _wait_for(COND, MS, W) ({ \
440 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
441 int ret__ = 0; \
442 while (!(COND)) { \
443 if (time_after(jiffies, timeout__)) { \
444 if (!(COND)) \
445 ret__ = -ETIMEDOUT; \
446 break; \
447 } \
448 if (W && drm_can_sleep()) { \
449 msleep(W); \
450 } else { \
451 cpu_relax(); \
452 } \
453 } \
454 ret__; \
455})
456
457#define wait_for(COND, MS) _wait_for(COND, MS, 1)
458
459
460struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
461void vc4_free_object(struct drm_gem_object *gem_obj);
462struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
463 bool from_cache);
464int vc4_dumb_create(struct drm_file *file_priv,
465 struct drm_device *dev,
466 struct drm_mode_create_dumb *args);
467struct dma_buf *vc4_prime_export(struct drm_device *dev,
468 struct drm_gem_object *obj, int flags);
469int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv);
471int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv);
473int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
474 struct drm_file *file_priv);
475int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
476 struct drm_file *file_priv);
477int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
478 struct drm_file *file_priv);
479int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
480 struct drm_file *file_priv);
481int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
482struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj);
483int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
484struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
485 struct dma_buf_attachment *attach,
486 struct sg_table *sgt);
487void *vc4_prime_vmap(struct drm_gem_object *obj);
488void vc4_bo_cache_init(struct drm_device *dev);
489void vc4_bo_cache_destroy(struct drm_device *dev);
490int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
491
492
493extern struct platform_driver vc4_crtc_driver;
494bool vc4_event_pending(struct drm_crtc *crtc);
495int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
496bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
497 bool in_vblank_irq, int *vpos, int *hpos,
498 ktime_t *stime, ktime_t *etime,
499 const struct drm_display_mode *mode);
500
501
502int vc4_debugfs_init(struct drm_minor *minor);
503
504
505void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
506
507
508extern struct platform_driver vc4_dpi_driver;
509int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
510
511
512extern struct platform_driver vc4_dsi_driver;
513int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
514
515
516extern const struct dma_fence_ops vc4_fence_ops;
517
518
519void vc4_gem_init(struct drm_device *dev);
520void vc4_gem_destroy(struct drm_device *dev);
521int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
522 struct drm_file *file_priv);
523int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
524 struct drm_file *file_priv);
525int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
526 struct drm_file *file_priv);
527void vc4_submit_next_bin_job(struct drm_device *dev);
528void vc4_submit_next_render_job(struct drm_device *dev);
529void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
530int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
531 uint64_t timeout_ns, bool interruptible);
532void vc4_job_handle_completed(struct vc4_dev *vc4);
533int vc4_queue_seqno_cb(struct drm_device *dev,
534 struct vc4_seqno_cb *cb, uint64_t seqno,
535 void (*func)(struct vc4_seqno_cb *cb));
536
537
538extern struct platform_driver vc4_hdmi_driver;
539int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
540
541
542extern struct platform_driver vc4_vec_driver;
543int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
544
545
546irqreturn_t vc4_irq(int irq, void *arg);
547void vc4_irq_preinstall(struct drm_device *dev);
548int vc4_irq_postinstall(struct drm_device *dev);
549void vc4_irq_uninstall(struct drm_device *dev);
550void vc4_irq_reset(struct drm_device *dev);
551
552
553extern struct platform_driver vc4_hvs_driver;
554void vc4_hvs_dump_state(struct drm_device *dev);
555int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
556
557
558int vc4_kms_load(struct drm_device *dev);
559
560
561struct drm_plane *vc4_plane_init(struct drm_device *dev,
562 enum drm_plane_type type);
563u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
564u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
565void vc4_plane_async_set_fb(struct drm_plane *plane,
566 struct drm_framebuffer *fb);
567
568
569extern struct platform_driver vc4_v3d_driver;
570int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
571int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
572int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
573
574
575int
576vc4_validate_bin_cl(struct drm_device *dev,
577 void *validated,
578 void *unvalidated,
579 struct vc4_exec_info *exec);
580
581int
582vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
583
584struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
585 uint32_t hindex);
586
587int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
588
589bool vc4_check_tex_size(struct vc4_exec_info *exec,
590 struct drm_gem_cma_object *fbo,
591 uint32_t offset, uint8_t tiling_format,
592 uint32_t width, uint32_t height, uint8_t cpp);
593
594
595struct vc4_validated_shader_info *
596vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
597