1
2
3
4
5
6
7
8
9#include <linux/clk.h>
10#include <linux/errno.h>
11#include <linux/gpio/consumer.h>
12#include <linux/delay.h>
13#include <linux/hwmon.h>
14#include <linux/hwmon-sysfs.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of_platform.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/sysfs.h>
22#include <linux/regmap.h>
23
24
25#define ASPEED_PTCR_CTRL 0x00
26#define ASPEED_PTCR_CLK_CTRL 0x04
27#define ASPEED_PTCR_DUTY0_CTRL 0x08
28#define ASPEED_PTCR_DUTY1_CTRL 0x0c
29#define ASPEED_PTCR_TYPEM_CTRL 0x10
30#define ASPEED_PTCR_TYPEM_CTRL1 0x14
31#define ASPEED_PTCR_TYPEN_CTRL 0x18
32#define ASPEED_PTCR_TYPEN_CTRL1 0x1c
33#define ASPEED_PTCR_TACH_SOURCE 0x20
34#define ASPEED_PTCR_TRIGGER 0x28
35#define ASPEED_PTCR_RESULT 0x2c
36#define ASPEED_PTCR_INTR_CTRL 0x30
37#define ASPEED_PTCR_INTR_STS 0x34
38#define ASPEED_PTCR_TYPEM_LIMIT 0x38
39#define ASPEED_PTCR_TYPEN_LIMIT 0x3C
40#define ASPEED_PTCR_CTRL_EXT 0x40
41#define ASPEED_PTCR_CLK_CTRL_EXT 0x44
42#define ASPEED_PTCR_DUTY2_CTRL 0x48
43#define ASPEED_PTCR_DUTY3_CTRL 0x4c
44#define ASPEED_PTCR_TYPEO_CTRL 0x50
45#define ASPEED_PTCR_TYPEO_CTRL1 0x54
46#define ASPEED_PTCR_TACH_SOURCE_EXT 0x60
47#define ASPEED_PTCR_TYPEO_LIMIT 0x78
48
49
50#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15
51#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6
52#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15))
53
54#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14
55#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5
56#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14))
57
58#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13
59#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4
60#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13))
61
62#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12
63#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3
64#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12))
65
66#define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x))
67
68#define ASPEED_PTCR_CTRL_PWMD_EN BIT(11)
69#define ASPEED_PTCR_CTRL_PWMC_EN BIT(10)
70#define ASPEED_PTCR_CTRL_PWMB_EN BIT(9)
71#define ASPEED_PTCR_CTRL_PWMA_EN BIT(8)
72
73#define ASPEED_PTCR_CTRL_CLK_SRC BIT(1)
74#define ASPEED_PTCR_CTRL_CLK_EN BIT(0)
75
76
77
78#define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16)
79#define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24
80#define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20
81#define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16
82
83#define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0)
84#define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8
85#define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4
86#define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0
87
88
89
90
91
92#define DUTY_CTRL_PWM2_FALL_POINT 24
93#define DUTY_CTRL_PWM2_RISE_POINT 16
94#define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16)
95#define DUTY_CTRL_PWM1_FALL_POINT 8
96#define DUTY_CTRL_PWM1_RISE_POINT 0
97#define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0)
98
99
100#define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16))
101#define TYPE_CTRL_FAN1_MASK GENMASK(31, 0)
102#define TYPE_CTRL_FAN_PERIOD 16
103#define TYPE_CTRL_FAN_MODE 4
104#define TYPE_CTRL_FAN_DIVISION 1
105#define TYPE_CTRL_FAN_TYPE_EN 1
106
107
108
109#define TACH_PWM_SOURCE_BIT01(x) ((x) * 2)
110#define TACH_PWM_SOURCE_BIT2(x) ((x) * 2)
111#define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2))
112#define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2)
113
114
115#define RESULT_STATUS_MASK BIT(31)
116#define RESULT_VALUE_MASK 0xfffff
117
118
119#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15
120#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6
121#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15))
122
123#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14
124#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5
125#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14))
126
127#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13
128#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4
129#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13))
130
131#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12
132#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3
133#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12))
134
135#define ASPEED_PTCR_CTRL_PWMH_EN BIT(11)
136#define ASPEED_PTCR_CTRL_PWMG_EN BIT(10)
137#define ASPEED_PTCR_CTRL_PWMF_EN BIT(9)
138#define ASPEED_PTCR_CTRL_PWME_EN BIT(8)
139
140
141
142#define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0)
143#define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8
144#define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4
145#define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0
146
147#define PWM_MAX 255
148
149#define BOTH_EDGES 0x02
150
151#define M_PWM_DIV_H 0x00
152#define M_PWM_DIV_L 0x05
153#define M_PWM_PERIOD 0x5F
154#define M_TACH_CLK_DIV 0x00
155
156
157
158
159
160
161
162#define M_TACH_MODE 0x02
163#define M_TACH_UNIT 0x00c0
164#define INIT_FAN_CTRL 0xFF
165
166
167#define ASPEED_RPM_STATUS_SLEEP_USEC 500
168
169struct aspeed_pwm_tacho_data {
170 struct regmap *regmap;
171 unsigned long clk_freq;
172 bool pwm_present[8];
173 bool fan_tach_present[16];
174 u8 type_pwm_clock_unit[3];
175 u8 type_pwm_clock_division_h[3];
176 u8 type_pwm_clock_division_l[3];
177 u8 type_fan_tach_clock_division[3];
178 u8 type_fan_tach_mode[3];
179 u16 type_fan_tach_unit[3];
180 u8 pwm_port_type[8];
181 u8 pwm_port_fan_ctrl[8];
182 u8 fan_tach_ch_source[16];
183 const struct attribute_group *groups[3];
184};
185
186enum type { TYPEM, TYPEN, TYPEO };
187
188struct type_params {
189 u32 l_value;
190 u32 h_value;
191 u32 unit_value;
192 u32 clk_ctrl_mask;
193 u32 clk_ctrl_reg;
194 u32 ctrl_reg;
195 u32 ctrl_reg1;
196};
197
198static const struct type_params type_params[] = {
199 [TYPEM] = {
200 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
201 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
202 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
203 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
204 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
205 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
206 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
207 },
208 [TYPEN] = {
209 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
210 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
211 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
212 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
213 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
214 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
215 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
216 },
217 [TYPEO] = {
218 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
219 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
220 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
221 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
222 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
223 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
224 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
225 }
226};
227
228enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
229
230struct pwm_port_params {
231 u32 pwm_en;
232 u32 ctrl_reg;
233 u32 type_part1;
234 u32 type_part2;
235 u32 type_mask;
236 u32 duty_ctrl_rise_point;
237 u32 duty_ctrl_fall_point;
238 u32 duty_ctrl_reg;
239 u32 duty_ctrl_rise_fall_mask;
240};
241
242static const struct pwm_port_params pwm_port_params[] = {
243 [PWMA] = {
244 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
245 .ctrl_reg = ASPEED_PTCR_CTRL,
246 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
247 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
248 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
249 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
250 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
251 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
252 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
253 },
254 [PWMB] = {
255 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
256 .ctrl_reg = ASPEED_PTCR_CTRL,
257 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
258 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
259 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
260 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
261 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
262 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
263 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
264 },
265 [PWMC] = {
266 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
267 .ctrl_reg = ASPEED_PTCR_CTRL,
268 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
269 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
270 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
271 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
272 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
273 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
274 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
275 },
276 [PWMD] = {
277 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
278 .ctrl_reg = ASPEED_PTCR_CTRL,
279 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
280 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
281 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
282 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
283 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
284 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
285 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
286 },
287 [PWME] = {
288 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
289 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
290 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
291 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
292 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
293 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
294 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
295 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
296 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
297 },
298 [PWMF] = {
299 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
300 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
301 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
302 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
303 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
304 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
305 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
306 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
307 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
308 },
309 [PWMG] = {
310 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
311 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
312 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
313 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
314 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
315 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
316 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
317 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
318 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
319 },
320 [PWMH] = {
321 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
322 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
323 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
324 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
325 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
326 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
327 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
328 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
329 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
330 }
331};
332
333static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
334 unsigned int val)
335{
336 void __iomem *regs = (void __iomem *)context;
337
338 writel(val, regs + reg);
339 return 0;
340}
341
342static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
343 unsigned int *val)
344{
345 void __iomem *regs = (void __iomem *)context;
346
347 *val = readl(regs + reg);
348 return 0;
349}
350
351static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
352 .reg_bits = 32,
353 .val_bits = 32,
354 .reg_stride = 4,
355 .max_register = ASPEED_PTCR_TYPEO_LIMIT,
356 .reg_write = regmap_aspeed_pwm_tacho_reg_write,
357 .reg_read = regmap_aspeed_pwm_tacho_reg_read,
358 .fast_io = true,
359};
360
361static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
362{
363 regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
364 ASPEED_PTCR_CTRL_CLK_EN,
365 val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
366}
367
368static void aspeed_set_clock_source(struct regmap *regmap, int val)
369{
370 regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
371 ASPEED_PTCR_CTRL_CLK_SRC,
372 val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
373}
374
375static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
376 u8 div_high, u8 div_low, u8 unit)
377{
378 u32 reg_value = ((div_high << type_params[type].h_value) |
379 (div_low << type_params[type].l_value) |
380 (unit << type_params[type].unit_value));
381
382 regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
383 type_params[type].clk_ctrl_mask, reg_value);
384}
385
386static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
387 bool enable)
388{
389 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
390 pwm_port_params[pwm_port].pwm_en,
391 enable ? pwm_port_params[pwm_port].pwm_en : 0);
392}
393
394static void aspeed_set_pwm_port_type(struct regmap *regmap,
395 u8 pwm_port, u8 type)
396{
397 u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
398
399 reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
400
401 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
402 pwm_port_params[pwm_port].type_mask, reg_value);
403}
404
405static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
406 u8 pwm_port, u8 rising,
407 u8 falling)
408{
409 u32 reg_value = (rising <<
410 pwm_port_params[pwm_port].duty_ctrl_rise_point);
411 reg_value |= (falling <<
412 pwm_port_params[pwm_port].duty_ctrl_fall_point);
413
414 regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
415 pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
416 reg_value);
417}
418
419static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
420 bool enable)
421{
422 regmap_update_bits(regmap, type_params[type].ctrl_reg,
423 TYPE_CTRL_FAN_TYPE_EN,
424 enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
425}
426
427static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
428 u8 mode, u16 unit, u8 division)
429{
430 u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
431 (unit << TYPE_CTRL_FAN_PERIOD) |
432 (division << TYPE_CTRL_FAN_DIVISION));
433
434 regmap_update_bits(regmap, type_params[type].ctrl_reg,
435 TYPE_CTRL_FAN_MASK, reg_value);
436 regmap_update_bits(regmap, type_params[type].ctrl_reg1,
437 TYPE_CTRL_FAN1_MASK, unit << 16);
438}
439
440static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
441 bool enable)
442{
443 regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
444 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
445 enable ?
446 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
447}
448
449static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
450 u8 fan_tach_ch_source)
451{
452 u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
453 TACH_PWM_SOURCE_BIT01(fan_tach_ch));
454 u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
455 TACH_PWM_SOURCE_BIT2(fan_tach_ch));
456
457 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
458 TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
459 reg_value1);
460
461 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
462 TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
463 reg_value2);
464}
465
466static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
467 u8 index, u8 fan_ctrl)
468{
469 u16 period, dc_time_on;
470
471 period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
472 period += 1;
473 dc_time_on = (fan_ctrl * period) / PWM_MAX;
474
475 if (dc_time_on == 0) {
476 aspeed_set_pwm_port_enable(priv->regmap, index, false);
477 } else {
478 if (dc_time_on == period)
479 dc_time_on = 0;
480
481 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
482 dc_time_on);
483 aspeed_set_pwm_port_enable(priv->regmap, index, true);
484 }
485}
486
487static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
488 *priv, u8 type)
489{
490 u32 clk;
491 u16 tacho_unit;
492 u8 clk_unit, div_h, div_l, tacho_div;
493
494 clk = priv->clk_freq;
495 clk_unit = priv->type_pwm_clock_unit[type];
496 div_h = priv->type_pwm_clock_division_h[type];
497 div_h = 0x1 << div_h;
498 div_l = priv->type_pwm_clock_division_l[type];
499 if (div_l == 0)
500 div_l = 1;
501 else
502 div_l = div_l * 2;
503
504 tacho_unit = priv->type_fan_tach_unit[type];
505 tacho_div = priv->type_fan_tach_clock_division[type];
506
507 tacho_div = 0x4 << (tacho_div * 2);
508 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
509}
510
511static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
512 u8 fan_tach_ch)
513{
514 u32 raw_data, tach_div, clk_source, msec, usec, val;
515 u8 fan_tach_ch_source, type, mode, both;
516 int ret;
517
518 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
519 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
520
521 fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
522 type = priv->pwm_port_type[fan_tach_ch_source];
523
524 msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
525 usec = msec * 1000;
526
527 ret = regmap_read_poll_timeout(
528 priv->regmap,
529 ASPEED_PTCR_RESULT,
530 val,
531 (val & RESULT_STATUS_MASK),
532 ASPEED_RPM_STATUS_SLEEP_USEC,
533 usec);
534
535
536 if (ret)
537 return ret;
538
539 raw_data = val & RESULT_VALUE_MASK;
540 tach_div = priv->type_fan_tach_clock_division[type];
541
542
543
544
545 mode = priv->type_fan_tach_mode[type];
546 both = (mode & BOTH_EDGES) ? 1 : 0;
547
548 tach_div = (0x4 << both) << (tach_div * 2);
549 clk_source = priv->clk_freq;
550
551 if (raw_data == 0)
552 return 0;
553
554 return (clk_source * 60) / (2 * raw_data * tach_div);
555}
556
557static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
558 const char *buf, size_t count)
559{
560 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
561 int index = sensor_attr->index;
562 int ret;
563 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
564 long fan_ctrl;
565
566 ret = kstrtol(buf, 10, &fan_ctrl);
567 if (ret != 0)
568 return ret;
569
570 if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
571 return -EINVAL;
572
573 if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
574 return count;
575
576 priv->pwm_port_fan_ctrl[index] = fan_ctrl;
577 aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
578
579 return count;
580}
581
582static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
583 char *buf)
584{
585 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
586 int index = sensor_attr->index;
587 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
588
589 return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
590}
591
592static ssize_t show_rpm(struct device *dev, struct device_attribute *attr,
593 char *buf)
594{
595 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
596 int index = sensor_attr->index;
597 int rpm;
598 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
599
600 rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
601 if (rpm < 0)
602 return rpm;
603
604 return sprintf(buf, "%d\n", rpm);
605}
606
607static umode_t pwm_is_visible(struct kobject *kobj,
608 struct attribute *a, int index)
609{
610 struct device *dev = container_of(kobj, struct device, kobj);
611 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
612
613 if (!priv->pwm_present[index])
614 return 0;
615 return a->mode;
616}
617
618static umode_t fan_dev_is_visible(struct kobject *kobj,
619 struct attribute *a, int index)
620{
621 struct device *dev = container_of(kobj, struct device, kobj);
622 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
623
624 if (!priv->fan_tach_present[index])
625 return 0;
626 return a->mode;
627}
628
629static SENSOR_DEVICE_ATTR(pwm1, 0644,
630 show_pwm, set_pwm, 0);
631static SENSOR_DEVICE_ATTR(pwm2, 0644,
632 show_pwm, set_pwm, 1);
633static SENSOR_DEVICE_ATTR(pwm3, 0644,
634 show_pwm, set_pwm, 2);
635static SENSOR_DEVICE_ATTR(pwm4, 0644,
636 show_pwm, set_pwm, 3);
637static SENSOR_DEVICE_ATTR(pwm5, 0644,
638 show_pwm, set_pwm, 4);
639static SENSOR_DEVICE_ATTR(pwm6, 0644,
640 show_pwm, set_pwm, 5);
641static SENSOR_DEVICE_ATTR(pwm7, 0644,
642 show_pwm, set_pwm, 6);
643static SENSOR_DEVICE_ATTR(pwm8, 0644,
644 show_pwm, set_pwm, 7);
645static struct attribute *pwm_dev_attrs[] = {
646 &sensor_dev_attr_pwm1.dev_attr.attr,
647 &sensor_dev_attr_pwm2.dev_attr.attr,
648 &sensor_dev_attr_pwm3.dev_attr.attr,
649 &sensor_dev_attr_pwm4.dev_attr.attr,
650 &sensor_dev_attr_pwm5.dev_attr.attr,
651 &sensor_dev_attr_pwm6.dev_attr.attr,
652 &sensor_dev_attr_pwm7.dev_attr.attr,
653 &sensor_dev_attr_pwm8.dev_attr.attr,
654 NULL,
655};
656
657static const struct attribute_group pwm_dev_group = {
658 .attrs = pwm_dev_attrs,
659 .is_visible = pwm_is_visible,
660};
661
662static SENSOR_DEVICE_ATTR(fan1_input, 0444,
663 show_rpm, NULL, 0);
664static SENSOR_DEVICE_ATTR(fan2_input, 0444,
665 show_rpm, NULL, 1);
666static SENSOR_DEVICE_ATTR(fan3_input, 0444,
667 show_rpm, NULL, 2);
668static SENSOR_DEVICE_ATTR(fan4_input, 0444,
669 show_rpm, NULL, 3);
670static SENSOR_DEVICE_ATTR(fan5_input, 0444,
671 show_rpm, NULL, 4);
672static SENSOR_DEVICE_ATTR(fan6_input, 0444,
673 show_rpm, NULL, 5);
674static SENSOR_DEVICE_ATTR(fan7_input, 0444,
675 show_rpm, NULL, 6);
676static SENSOR_DEVICE_ATTR(fan8_input, 0444,
677 show_rpm, NULL, 7);
678static SENSOR_DEVICE_ATTR(fan9_input, 0444,
679 show_rpm, NULL, 8);
680static SENSOR_DEVICE_ATTR(fan10_input, 0444,
681 show_rpm, NULL, 9);
682static SENSOR_DEVICE_ATTR(fan11_input, 0444,
683 show_rpm, NULL, 10);
684static SENSOR_DEVICE_ATTR(fan12_input, 0444,
685 show_rpm, NULL, 11);
686static SENSOR_DEVICE_ATTR(fan13_input, 0444,
687 show_rpm, NULL, 12);
688static SENSOR_DEVICE_ATTR(fan14_input, 0444,
689 show_rpm, NULL, 13);
690static SENSOR_DEVICE_ATTR(fan15_input, 0444,
691 show_rpm, NULL, 14);
692static SENSOR_DEVICE_ATTR(fan16_input, 0444,
693 show_rpm, NULL, 15);
694static struct attribute *fan_dev_attrs[] = {
695 &sensor_dev_attr_fan1_input.dev_attr.attr,
696 &sensor_dev_attr_fan2_input.dev_attr.attr,
697 &sensor_dev_attr_fan3_input.dev_attr.attr,
698 &sensor_dev_attr_fan4_input.dev_attr.attr,
699 &sensor_dev_attr_fan5_input.dev_attr.attr,
700 &sensor_dev_attr_fan6_input.dev_attr.attr,
701 &sensor_dev_attr_fan7_input.dev_attr.attr,
702 &sensor_dev_attr_fan8_input.dev_attr.attr,
703 &sensor_dev_attr_fan9_input.dev_attr.attr,
704 &sensor_dev_attr_fan10_input.dev_attr.attr,
705 &sensor_dev_attr_fan11_input.dev_attr.attr,
706 &sensor_dev_attr_fan12_input.dev_attr.attr,
707 &sensor_dev_attr_fan13_input.dev_attr.attr,
708 &sensor_dev_attr_fan14_input.dev_attr.attr,
709 &sensor_dev_attr_fan15_input.dev_attr.attr,
710 &sensor_dev_attr_fan16_input.dev_attr.attr,
711 NULL
712};
713
714static const struct attribute_group fan_dev_group = {
715 .attrs = fan_dev_attrs,
716 .is_visible = fan_dev_is_visible,
717};
718
719
720
721
722
723
724static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
725{
726 priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
727 priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
728 priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
729 aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
730 M_PWM_DIV_L, M_PWM_PERIOD);
731 aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
732 priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
733 priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
734 priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
735 aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
736 M_TACH_UNIT, M_TACH_CLK_DIV);
737}
738
739static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
740 u8 pwm_port)
741{
742 aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
743 priv->pwm_present[pwm_port] = true;
744
745 priv->pwm_port_type[pwm_port] = TYPEM;
746 aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
747
748 priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
749 aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
750}
751
752static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
753 u8 *fan_tach_ch,
754 int count,
755 u8 pwm_source)
756{
757 u8 val, index;
758
759 for (val = 0; val < count; val++) {
760 index = fan_tach_ch[val];
761 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
762 priv->fan_tach_present[index] = true;
763 priv->fan_tach_ch_source[index] = pwm_source;
764 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
765 }
766}
767
768static int aspeed_create_fan(struct device *dev,
769 struct device_node *child,
770 struct aspeed_pwm_tacho_data *priv)
771{
772 u8 *fan_tach_ch;
773 u32 pwm_port;
774 int ret, count;
775
776 ret = of_property_read_u32(child, "reg", &pwm_port);
777 if (ret)
778 return ret;
779 aspeed_create_pwm_port(priv, (u8)pwm_port);
780
781 count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
782 if (count < 1)
783 return -EINVAL;
784 fan_tach_ch = devm_kzalloc(dev, sizeof(*fan_tach_ch) * count,
785 GFP_KERNEL);
786 if (!fan_tach_ch)
787 return -ENOMEM;
788 ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
789 fan_tach_ch, count);
790 if (ret)
791 return ret;
792 aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
793
794 return 0;
795}
796
797static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
798{
799 struct device *dev = &pdev->dev;
800 struct device_node *np, *child;
801 struct aspeed_pwm_tacho_data *priv;
802 void __iomem *regs;
803 struct resource *res;
804 struct device *hwmon;
805 struct clk *clk;
806 int ret;
807
808 np = dev->of_node;
809
810 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
811 if (!res)
812 return -ENOENT;
813 regs = devm_ioremap_resource(dev, res);
814 if (IS_ERR(regs))
815 return PTR_ERR(regs);
816 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
817 if (!priv)
818 return -ENOMEM;
819 priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
820 &aspeed_pwm_tacho_regmap_config);
821 if (IS_ERR(priv->regmap))
822 return PTR_ERR(priv->regmap);
823 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
824 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
825
826 clk = devm_clk_get(dev, NULL);
827 if (IS_ERR(clk))
828 return -ENODEV;
829 priv->clk_freq = clk_get_rate(clk);
830 aspeed_set_clock_enable(priv->regmap, true);
831 aspeed_set_clock_source(priv->regmap, 0);
832
833 aspeed_create_type(priv);
834
835 for_each_child_of_node(np, child) {
836 ret = aspeed_create_fan(dev, child, priv);
837 of_node_put(child);
838 if (ret)
839 return ret;
840 }
841
842 priv->groups[0] = &pwm_dev_group;
843 priv->groups[1] = &fan_dev_group;
844 priv->groups[2] = NULL;
845 hwmon = devm_hwmon_device_register_with_groups(dev,
846 "aspeed_pwm_tacho",
847 priv, priv->groups);
848 return PTR_ERR_OR_ZERO(hwmon);
849}
850
851static const struct of_device_id of_pwm_tacho_match_table[] = {
852 { .compatible = "aspeed,ast2400-pwm-tacho", },
853 { .compatible = "aspeed,ast2500-pwm-tacho", },
854 {},
855};
856MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
857
858static struct platform_driver aspeed_pwm_tacho_driver = {
859 .probe = aspeed_pwm_tacho_probe,
860 .driver = {
861 .name = "aspeed_pwm_tacho",
862 .of_match_table = of_pwm_tacho_match_table,
863 },
864};
865
866module_platform_driver(aspeed_pwm_tacho_driver);
867
868MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
869MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
870MODULE_LICENSE("GPL");
871
