linux/drivers/ide/pmac.c
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   1/*
   2 * Support for IDE interfaces on PowerMacs.
   3 *
   4 * These IDE interfaces are memory-mapped and have a DBDMA channel
   5 * for doing DMA.
   6 *
   7 *  Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
   8 *  Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
   9 *
  10 *  This program is free software; you can redistribute it and/or
  11 *  modify it under the terms of the GNU General Public License
  12 *  as published by the Free Software Foundation; either version
  13 *  2 of the License, or (at your option) any later version.
  14 *
  15 * Some code taken from drivers/ide/ide-dma.c:
  16 *
  17 *  Copyright (c) 1995-1998  Mark Lord
  18 *
  19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
  20 * get rid of the "rounded" tables used previously, so we have the
  21 * same table format for all controllers and can then just have one
  22 * big table
  23 * 
  24 */
  25#include <linux/types.h>
  26#include <linux/kernel.h>
  27#include <linux/init.h>
  28#include <linux/delay.h>
  29#include <linux/ide.h>
  30#include <linux/notifier.h>
  31#include <linux/module.h>
  32#include <linux/reboot.h>
  33#include <linux/pci.h>
  34#include <linux/adb.h>
  35#include <linux/pmu.h>
  36#include <linux/scatterlist.h>
  37#include <linux/slab.h>
  38
  39#include <asm/prom.h>
  40#include <asm/io.h>
  41#include <asm/dbdma.h>
  42#include <asm/ide.h>
  43#include <asm/machdep.h>
  44#include <asm/pmac_feature.h>
  45#include <asm/sections.h>
  46#include <asm/irq.h>
  47#include <asm/mediabay.h>
  48
  49#define DRV_NAME "ide-pmac"
  50
  51#undef IDE_PMAC_DEBUG
  52
  53#define DMA_WAIT_TIMEOUT        50
  54
  55typedef struct pmac_ide_hwif {
  56        unsigned long                   regbase;
  57        int                             irq;
  58        int                             kind;
  59        int                             aapl_bus_id;
  60        unsigned                        broken_dma : 1;
  61        unsigned                        broken_dma_warn : 1;
  62        struct device_node*             node;
  63        struct macio_dev                *mdev;
  64        u32                             timings[4];
  65        volatile u32 __iomem *          *kauai_fcr;
  66        ide_hwif_t                      *hwif;
  67
  68        /* Those fields are duplicating what is in hwif. We currently
  69         * can't use the hwif ones because of some assumptions that are
  70         * beeing done by the generic code about the kind of dma controller
  71         * and format of the dma table. This will have to be fixed though.
  72         */
  73        volatile struct dbdma_regs __iomem *    dma_regs;
  74        struct dbdma_cmd*               dma_table_cpu;
  75} pmac_ide_hwif_t;
  76
  77enum {
  78        controller_ohare,       /* OHare based */
  79        controller_heathrow,    /* Heathrow/Paddington */
  80        controller_kl_ata3,     /* KeyLargo ATA-3 */
  81        controller_kl_ata4,     /* KeyLargo ATA-4 */
  82        controller_un_ata6,     /* UniNorth2 ATA-6 */
  83        controller_k2_ata6,     /* K2 ATA-6 */
  84        controller_sh_ata6,     /* Shasta ATA-6 */
  85};
  86
  87static const char* model_name[] = {
  88        "OHare ATA",            /* OHare based */
  89        "Heathrow ATA",         /* Heathrow/Paddington */
  90        "KeyLargo ATA-3",       /* KeyLargo ATA-3 (MDMA only) */
  91        "KeyLargo ATA-4",       /* KeyLargo ATA-4 (UDMA/66) */
  92        "UniNorth ATA-6",       /* UniNorth2 ATA-6 (UDMA/100) */
  93        "K2 ATA-6",             /* K2 ATA-6 (UDMA/100) */
  94        "Shasta ATA-6",         /* Shasta ATA-6 (UDMA/133) */
  95};
  96
  97/*
  98 * Extra registers, both 32-bit little-endian
  99 */
 100#define IDE_TIMING_CONFIG       0x200
 101#define IDE_INTERRUPT           0x300
 102
 103/* Kauai (U2) ATA has different register setup */
 104#define IDE_KAUAI_PIO_CONFIG    0x200
 105#define IDE_KAUAI_ULTRA_CONFIG  0x210
 106#define IDE_KAUAI_POLL_CONFIG   0x220
 107
 108/*
 109 * Timing configuration register definitions
 110 */
 111
 112/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
 113#define SYSCLK_TICKS(t)         (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
 114#define SYSCLK_TICKS_66(t)      (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
 115#define IDE_SYSCLK_NS           30      /* 33Mhz cell */
 116#define IDE_SYSCLK_66_NS        15      /* 66Mhz cell */
 117
 118/* 133Mhz cell, found in shasta.
 119 * See comments about 100 Mhz Uninorth 2...
 120 * Note that PIO_MASK and MDMA_MASK seem to overlap
 121 */
 122#define TR_133_PIOREG_PIO_MASK          0xff000fff
 123#define TR_133_PIOREG_MDMA_MASK         0x00fff800
 124#define TR_133_UDMAREG_UDMA_MASK        0x0003ffff
 125#define TR_133_UDMAREG_UDMA_EN          0x00000001
 126
 127/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
 128 * this one yet, it appears as a pci device (106b/0033) on uninorth
 129 * internal PCI bus and it's clock is controlled like gem or fw. It
 130 * appears to be an evolution of keylargo ATA4 with a timing register
 131 * extended to 2 32bits registers and a similar DBDMA channel. Other
 132 * registers seem to exist but I can't tell much about them.
 133 * 
 134 * So far, I'm using pre-calculated tables for this extracted from
 135 * the values used by the MacOS X driver.
 136 * 
 137 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
 138 * register controls the UDMA timings. At least, it seems bit 0
 139 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
 140 * cycle time in units of 10ns. Bits 8..15 are used by I don't
 141 * know their meaning yet
 142 */
 143#define TR_100_PIOREG_PIO_MASK          0xff000fff
 144#define TR_100_PIOREG_MDMA_MASK         0x00fff000
 145#define TR_100_UDMAREG_UDMA_MASK        0x0000ffff
 146#define TR_100_UDMAREG_UDMA_EN          0x00000001
 147
 148
 149/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
 150 * 40 connector cable and to 4 on 80 connector one.
 151 * Clock unit is 15ns (66Mhz)
 152 * 
 153 * 3 Values can be programmed:
 154 *  - Write data setup, which appears to match the cycle time. They
 155 *    also call it DIOW setup.
 156 *  - Ready to pause time (from spec)
 157 *  - Address setup. That one is weird. I don't see where exactly
 158 *    it fits in UDMA cycles, I got it's name from an obscure piece
 159 *    of commented out code in Darwin. They leave it to 0, we do as
 160 *    well, despite a comment that would lead to think it has a
 161 *    min value of 45ns.
 162 * Apple also add 60ns to the write data setup (or cycle time ?) on
 163 * reads.
 164 */
 165#define TR_66_UDMA_MASK                 0xfff00000
 166#define TR_66_UDMA_EN                   0x00100000 /* Enable Ultra mode for DMA */
 167#define TR_66_UDMA_ADDRSETUP_MASK       0xe0000000 /* Address setup */
 168#define TR_66_UDMA_ADDRSETUP_SHIFT      29
 169#define TR_66_UDMA_RDY2PAUS_MASK        0x1e000000 /* Ready 2 pause time */
 170#define TR_66_UDMA_RDY2PAUS_SHIFT       25
 171#define TR_66_UDMA_WRDATASETUP_MASK     0x01e00000 /* Write data setup time */
 172#define TR_66_UDMA_WRDATASETUP_SHIFT    21
 173#define TR_66_MDMA_MASK                 0x000ffc00
 174#define TR_66_MDMA_RECOVERY_MASK        0x000f8000
 175#define TR_66_MDMA_RECOVERY_SHIFT       15
 176#define TR_66_MDMA_ACCESS_MASK          0x00007c00
 177#define TR_66_MDMA_ACCESS_SHIFT         10
 178#define TR_66_PIO_MASK                  0x000003ff
 179#define TR_66_PIO_RECOVERY_MASK         0x000003e0
 180#define TR_66_PIO_RECOVERY_SHIFT        5
 181#define TR_66_PIO_ACCESS_MASK           0x0000001f
 182#define TR_66_PIO_ACCESS_SHIFT          0
 183
 184/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
 185 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
 186 * 
 187 * The access time and recovery time can be programmed. Some older
 188 * Darwin code base limit OHare to 150ns cycle time. I decided to do
 189 * the same here fore safety against broken old hardware ;)
 190 * The HalfTick bit, when set, adds half a clock (15ns) to the access
 191 * time and removes one from recovery. It's not supported on KeyLargo
 192 * implementation afaik. The E bit appears to be set for PIO mode 0 and
 193 * is used to reach long timings used in this mode.
 194 */
 195#define TR_33_MDMA_MASK                 0x003ff800
 196#define TR_33_MDMA_RECOVERY_MASK        0x001f0000
 197#define TR_33_MDMA_RECOVERY_SHIFT       16
 198#define TR_33_MDMA_ACCESS_MASK          0x0000f800
 199#define TR_33_MDMA_ACCESS_SHIFT         11
 200#define TR_33_MDMA_HALFTICK             0x00200000
 201#define TR_33_PIO_MASK                  0x000007ff
 202#define TR_33_PIO_E                     0x00000400
 203#define TR_33_PIO_RECOVERY_MASK         0x000003e0
 204#define TR_33_PIO_RECOVERY_SHIFT        5
 205#define TR_33_PIO_ACCESS_MASK           0x0000001f
 206#define TR_33_PIO_ACCESS_SHIFT          0
 207
 208/*
 209 * Interrupt register definitions
 210 */
 211#define IDE_INTR_DMA                    0x80000000
 212#define IDE_INTR_DEVICE                 0x40000000
 213
 214/*
 215 * FCR Register on Kauai. Not sure what bit 0x4 is  ...
 216 */
 217#define KAUAI_FCR_UATA_MAGIC            0x00000004
 218#define KAUAI_FCR_UATA_RESET_N          0x00000002
 219#define KAUAI_FCR_UATA_ENABLE           0x00000001
 220
 221/* Rounded Multiword DMA timings
 222 * 
 223 * I gave up finding a generic formula for all controller
 224 * types and instead, built tables based on timing values
 225 * used by Apple in Darwin's implementation.
 226 */
 227struct mdma_timings_t {
 228        int     accessTime;
 229        int     recoveryTime;
 230        int     cycleTime;
 231};
 232
 233struct mdma_timings_t mdma_timings_33[] =
 234{
 235    { 240, 240, 480 },
 236    { 180, 180, 360 },
 237    { 135, 135, 270 },
 238    { 120, 120, 240 },
 239    { 105, 105, 210 },
 240    {  90,  90, 180 },
 241    {  75,  75, 150 },
 242    {  75,  45, 120 },
 243    {   0,   0,   0 }
 244};
 245
 246struct mdma_timings_t mdma_timings_33k[] =
 247{
 248    { 240, 240, 480 },
 249    { 180, 180, 360 },
 250    { 150, 150, 300 },
 251    { 120, 120, 240 },
 252    {  90, 120, 210 },
 253    {  90,  90, 180 },
 254    {  90,  60, 150 },
 255    {  90,  30, 120 },
 256    {   0,   0,   0 }
 257};
 258
 259struct mdma_timings_t mdma_timings_66[] =
 260{
 261    { 240, 240, 480 },
 262    { 180, 180, 360 },
 263    { 135, 135, 270 },
 264    { 120, 120, 240 },
 265    { 105, 105, 210 },
 266    {  90,  90, 180 },
 267    {  90,  75, 165 },
 268    {  75,  45, 120 },
 269    {   0,   0,   0 }
 270};
 271
 272/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
 273struct {
 274        int     addrSetup; /* ??? */
 275        int     rdy2pause;
 276        int     wrDataSetup;
 277} kl66_udma_timings[] =
 278{
 279    {   0, 180,  120 }, /* Mode 0 */
 280    {   0, 150,  90 },  /*      1 */
 281    {   0, 120,  60 },  /*      2 */
 282    {   0, 90,   45 },  /*      3 */
 283    {   0, 90,   30 }   /*      4 */
 284};
 285
 286/* UniNorth 2 ATA/100 timings */
 287struct kauai_timing {
 288        int     cycle_time;
 289        u32     timing_reg;
 290};
 291
 292static struct kauai_timing      kauai_pio_timings[] =
 293{
 294        { 930   , 0x08000fff },
 295        { 600   , 0x08000a92 },
 296        { 383   , 0x0800060f },
 297        { 360   , 0x08000492 },
 298        { 330   , 0x0800048f },
 299        { 300   , 0x080003cf },
 300        { 270   , 0x080003cc },
 301        { 240   , 0x0800038b },
 302        { 239   , 0x0800030c },
 303        { 180   , 0x05000249 },
 304        { 120   , 0x04000148 },
 305        { 0     , 0 },
 306};
 307
 308static struct kauai_timing      kauai_mdma_timings[] =
 309{
 310        { 1260  , 0x00fff000 },
 311        { 480   , 0x00618000 },
 312        { 360   , 0x00492000 },
 313        { 270   , 0x0038e000 },
 314        { 240   , 0x0030c000 },
 315        { 210   , 0x002cb000 },
 316        { 180   , 0x00249000 },
 317        { 150   , 0x00209000 },
 318        { 120   , 0x00148000 },
 319        { 0     , 0 },
 320};
 321
 322static struct kauai_timing      kauai_udma_timings[] =
 323{
 324        { 120   , 0x000070c0 },
 325        { 90    , 0x00005d80 },
 326        { 60    , 0x00004a60 },
 327        { 45    , 0x00003a50 },
 328        { 30    , 0x00002a30 },
 329        { 20    , 0x00002921 },
 330        { 0     , 0 },
 331};
 332
 333static struct kauai_timing      shasta_pio_timings[] =
 334{
 335        { 930   , 0x08000fff },
 336        { 600   , 0x0A000c97 },
 337        { 383   , 0x07000712 },
 338        { 360   , 0x040003cd },
 339        { 330   , 0x040003cd },
 340        { 300   , 0x040003cd },
 341        { 270   , 0x040003cd },
 342        { 240   , 0x040003cd },
 343        { 239   , 0x040003cd },
 344        { 180   , 0x0400028b },
 345        { 120   , 0x0400010a },
 346        { 0     , 0 },
 347};
 348
 349static struct kauai_timing      shasta_mdma_timings[] =
 350{
 351        { 1260  , 0x00fff000 },
 352        { 480   , 0x00820800 },
 353        { 360   , 0x00820800 },
 354        { 270   , 0x00820800 },
 355        { 240   , 0x00820800 },
 356        { 210   , 0x00820800 },
 357        { 180   , 0x00820800 },
 358        { 150   , 0x0028b000 },
 359        { 120   , 0x001ca000 },
 360        { 0     , 0 },
 361};
 362
 363static struct kauai_timing      shasta_udma133_timings[] =
 364{
 365        { 120   , 0x00035901, },
 366        { 90    , 0x000348b1, },
 367        { 60    , 0x00033881, },
 368        { 45    , 0x00033861, },
 369        { 30    , 0x00033841, },
 370        { 20    , 0x00033031, },
 371        { 15    , 0x00033021, },
 372        { 0     , 0 },
 373};
 374
 375
 376static inline u32
 377kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
 378{
 379        int i;
 380        
 381        for (i=0; table[i].cycle_time; i++)
 382                if (cycle_time > table[i+1].cycle_time)
 383                        return table[i].timing_reg;
 384        BUG();
 385        return 0;
 386}
 387
 388/* allow up to 256 DBDMA commands per xfer */
 389#define MAX_DCMDS               256
 390
 391/* 
 392 * Wait 1s for disk to answer on IDE bus after a hard reset
 393 * of the device (via GPIO/FCR).
 394 * 
 395 * Some devices seem to "pollute" the bus even after dropping
 396 * the BSY bit (typically some combo drives slave on the UDMA
 397 * bus) after a hard reset. Since we hard reset all drives on
 398 * KeyLargo ATA66, we have to keep that delay around. I may end
 399 * up not hard resetting anymore on these and keep the delay only
 400 * for older interfaces instead (we have to reset when coming
 401 * from MacOS...) --BenH. 
 402 */
 403#define IDE_WAKEUP_DELAY        (1*HZ)
 404
 405static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
 406
 407#define PMAC_IDE_REG(x) \
 408        ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
 409
 410/*
 411 * Apply the timings of the proper unit (master/slave) to the shared
 412 * timing register when selecting that unit. This version is for
 413 * ASICs with a single timing register
 414 */
 415static void pmac_ide_apply_timings(ide_drive_t *drive)
 416{
 417        ide_hwif_t *hwif = drive->hwif;
 418        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 419
 420        if (drive->dn & 1)
 421                writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
 422        else
 423                writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
 424        (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
 425}
 426
 427/*
 428 * Apply the timings of the proper unit (master/slave) to the shared
 429 * timing register when selecting that unit. This version is for
 430 * ASICs with a dual timing register (Kauai)
 431 */
 432static void pmac_ide_kauai_apply_timings(ide_drive_t *drive)
 433{
 434        ide_hwif_t *hwif = drive->hwif;
 435        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 436
 437        if (drive->dn & 1) {
 438                writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
 439                writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
 440        } else {
 441                writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
 442                writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
 443        }
 444        (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
 445}
 446
 447/*
 448 * Force an update of controller timing values for a given drive
 449 */
 450static void
 451pmac_ide_do_update_timings(ide_drive_t *drive)
 452{
 453        ide_hwif_t *hwif = drive->hwif;
 454        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 455
 456        if (pmif->kind == controller_sh_ata6 ||
 457            pmif->kind == controller_un_ata6 ||
 458            pmif->kind == controller_k2_ata6)
 459                pmac_ide_kauai_apply_timings(drive);
 460        else
 461                pmac_ide_apply_timings(drive);
 462}
 463
 464static void pmac_dev_select(ide_drive_t *drive)
 465{
 466        pmac_ide_apply_timings(drive);
 467
 468        writeb(drive->select | ATA_DEVICE_OBS,
 469               (void __iomem *)drive->hwif->io_ports.device_addr);
 470}
 471
 472static void pmac_kauai_dev_select(ide_drive_t *drive)
 473{
 474        pmac_ide_kauai_apply_timings(drive);
 475
 476        writeb(drive->select | ATA_DEVICE_OBS,
 477               (void __iomem *)drive->hwif->io_ports.device_addr);
 478}
 479
 480static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
 481{
 482        writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
 483        (void)readl((void __iomem *)(hwif->io_ports.data_addr
 484                                     + IDE_TIMING_CONFIG));
 485}
 486
 487static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl)
 488{
 489        writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
 490        (void)readl((void __iomem *)(hwif->io_ports.data_addr
 491                                     + IDE_TIMING_CONFIG));
 492}
 493
 494/*
 495 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
 496 */
 497static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 498{
 499        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 500        const u8 pio = drive->pio_mode - XFER_PIO_0;
 501        struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
 502        u32 *timings, t;
 503        unsigned accessTicks, recTicks;
 504        unsigned accessTime, recTime;
 505        unsigned int cycle_time;
 506
 507        /* which drive is it ? */
 508        timings = &pmif->timings[drive->dn & 1];
 509        t = *timings;
 510
 511        cycle_time = ide_pio_cycle_time(drive, pio);
 512
 513        switch (pmif->kind) {
 514        case controller_sh_ata6: {
 515                /* 133Mhz cell */
 516                u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
 517                t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
 518                break;
 519                }
 520        case controller_un_ata6:
 521        case controller_k2_ata6: {
 522                /* 100Mhz cell */
 523                u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
 524                t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
 525                break;
 526                }
 527        case controller_kl_ata4:
 528                /* 66Mhz cell */
 529                recTime = cycle_time - tim->active - tim->setup;
 530                recTime = max(recTime, 150U);
 531                accessTime = tim->active;
 532                accessTime = max(accessTime, 150U);
 533                accessTicks = SYSCLK_TICKS_66(accessTime);
 534                accessTicks = min(accessTicks, 0x1fU);
 535                recTicks = SYSCLK_TICKS_66(recTime);
 536                recTicks = min(recTicks, 0x1fU);
 537                t = (t & ~TR_66_PIO_MASK) |
 538                        (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
 539                        (recTicks << TR_66_PIO_RECOVERY_SHIFT);
 540                break;
 541        default: {
 542                /* 33Mhz cell */
 543                int ebit = 0;
 544                recTime = cycle_time - tim->active - tim->setup;
 545                recTime = max(recTime, 150U);
 546                accessTime = tim->active;
 547                accessTime = max(accessTime, 150U);
 548                accessTicks = SYSCLK_TICKS(accessTime);
 549                accessTicks = min(accessTicks, 0x1fU);
 550                accessTicks = max(accessTicks, 4U);
 551                recTicks = SYSCLK_TICKS(recTime);
 552                recTicks = min(recTicks, 0x1fU);
 553                recTicks = max(recTicks, 5U) - 4;
 554                if (recTicks > 9) {
 555                        recTicks--; /* guess, but it's only for PIO0, so... */
 556                        ebit = 1;
 557                }
 558                t = (t & ~TR_33_PIO_MASK) |
 559                                (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
 560                                (recTicks << TR_33_PIO_RECOVERY_SHIFT);
 561                if (ebit)
 562                        t |= TR_33_PIO_E;
 563                break;
 564                }
 565        }
 566
 567#ifdef IDE_PMAC_DEBUG
 568        printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
 569                drive->name, pio,  *timings);
 570#endif  
 571
 572        *timings = t;
 573        pmac_ide_do_update_timings(drive);
 574}
 575
 576/*
 577 * Calculate KeyLargo ATA/66 UDMA timings
 578 */
 579static int
 580set_timings_udma_ata4(u32 *timings, u8 speed)
 581{
 582        unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
 583
 584        if (speed > XFER_UDMA_4)
 585                return 1;
 586
 587        rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
 588        wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
 589        addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
 590
 591        *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
 592                        (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | 
 593                        (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
 594                        (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
 595                        TR_66_UDMA_EN;
 596#ifdef IDE_PMAC_DEBUG
 597        printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
 598                speed & 0xf,  *timings);
 599#endif  
 600
 601        return 0;
 602}
 603
 604/*
 605 * Calculate Kauai ATA/100 UDMA timings
 606 */
 607static int
 608set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
 609{
 610        struct ide_timing *t = ide_timing_find_mode(speed);
 611        u32 tr;
 612
 613        if (speed > XFER_UDMA_5 || t == NULL)
 614                return 1;
 615        tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
 616        *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
 617        *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
 618
 619        return 0;
 620}
 621
 622/*
 623 * Calculate Shasta ATA/133 UDMA timings
 624 */
 625static int
 626set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
 627{
 628        struct ide_timing *t = ide_timing_find_mode(speed);
 629        u32 tr;
 630
 631        if (speed > XFER_UDMA_6 || t == NULL)
 632                return 1;
 633        tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
 634        *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
 635        *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
 636
 637        return 0;
 638}
 639
 640/*
 641 * Calculate MDMA timings for all cells
 642 */
 643static void
 644set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
 645                        u8 speed)
 646{
 647        u16 *id = drive->id;
 648        int cycleTime, accessTime = 0, recTime = 0;
 649        unsigned accessTicks, recTicks;
 650        struct mdma_timings_t* tm = NULL;
 651        int i;
 652
 653        /* Get default cycle time for mode */
 654        switch(speed & 0xf) {
 655                case 0: cycleTime = 480; break;
 656                case 1: cycleTime = 150; break;
 657                case 2: cycleTime = 120; break;
 658                default:
 659                        BUG();
 660                        break;
 661        }
 662
 663        /* Check if drive provides explicit DMA cycle time */
 664        if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
 665                cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
 666
 667        /* OHare limits according to some old Apple sources */  
 668        if ((intf_type == controller_ohare) && (cycleTime < 150))
 669                cycleTime = 150;
 670        /* Get the proper timing array for this controller */
 671        switch(intf_type) {
 672                case controller_sh_ata6:
 673                case controller_un_ata6:
 674                case controller_k2_ata6:
 675                        break;
 676                case controller_kl_ata4:
 677                        tm = mdma_timings_66;
 678                        break;
 679                case controller_kl_ata3:
 680                        tm = mdma_timings_33k;
 681                        break;
 682                default:
 683                        tm = mdma_timings_33;
 684                        break;
 685        }
 686        if (tm != NULL) {
 687                /* Lookup matching access & recovery times */
 688                i = -1;
 689                for (;;) {
 690                        if (tm[i+1].cycleTime < cycleTime)
 691                                break;
 692                        i++;
 693                }
 694                cycleTime = tm[i].cycleTime;
 695                accessTime = tm[i].accessTime;
 696                recTime = tm[i].recoveryTime;
 697
 698#ifdef IDE_PMAC_DEBUG
 699                printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
 700                        drive->name, cycleTime, accessTime, recTime);
 701#endif
 702        }
 703        switch(intf_type) {
 704        case controller_sh_ata6: {
 705                /* 133Mhz cell */
 706                u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
 707                *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
 708                *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
 709                }
 710                break;
 711        case controller_un_ata6:
 712        case controller_k2_ata6: {
 713                /* 100Mhz cell */
 714                u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
 715                *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
 716                *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
 717                }
 718                break;
 719        case controller_kl_ata4:
 720                /* 66Mhz cell */
 721                accessTicks = SYSCLK_TICKS_66(accessTime);
 722                accessTicks = min(accessTicks, 0x1fU);
 723                accessTicks = max(accessTicks, 0x1U);
 724                recTicks = SYSCLK_TICKS_66(recTime);
 725                recTicks = min(recTicks, 0x1fU);
 726                recTicks = max(recTicks, 0x3U);
 727                /* Clear out mdma bits and disable udma */
 728                *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
 729                        (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
 730                        (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
 731                break;
 732        case controller_kl_ata3:
 733                /* 33Mhz cell on KeyLargo */
 734                accessTicks = SYSCLK_TICKS(accessTime);
 735                accessTicks = max(accessTicks, 1U);
 736                accessTicks = min(accessTicks, 0x1fU);
 737                accessTime = accessTicks * IDE_SYSCLK_NS;
 738                recTicks = SYSCLK_TICKS(recTime);
 739                recTicks = max(recTicks, 1U);
 740                recTicks = min(recTicks, 0x1fU);
 741                *timings = ((*timings) & ~TR_33_MDMA_MASK) |
 742                                (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
 743                                (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
 744                break;
 745        default: {
 746                /* 33Mhz cell on others */
 747                int halfTick = 0;
 748                int origAccessTime = accessTime;
 749                int origRecTime = recTime;
 750                
 751                accessTicks = SYSCLK_TICKS(accessTime);
 752                accessTicks = max(accessTicks, 1U);
 753                accessTicks = min(accessTicks, 0x1fU);
 754                accessTime = accessTicks * IDE_SYSCLK_NS;
 755                recTicks = SYSCLK_TICKS(recTime);
 756                recTicks = max(recTicks, 2U) - 1;
 757                recTicks = min(recTicks, 0x1fU);
 758                recTime = (recTicks + 1) * IDE_SYSCLK_NS;
 759                if ((accessTicks > 1) &&
 760                    ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
 761                    ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
 762                        halfTick = 1;
 763                        accessTicks--;
 764                }
 765                *timings = ((*timings) & ~TR_33_MDMA_MASK) |
 766                                (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
 767                                (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
 768                if (halfTick)
 769                        *timings |= TR_33_MDMA_HALFTICK;
 770                }
 771        }
 772#ifdef IDE_PMAC_DEBUG
 773        printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
 774                drive->name, speed & 0xf,  *timings);
 775#endif  
 776}
 777
 778static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 779{
 780        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 781        int ret = 0;
 782        u32 *timings, *timings2, tl[2];
 783        u8 unit = drive->dn & 1;
 784        const u8 speed = drive->dma_mode;
 785
 786        timings = &pmif->timings[unit];
 787        timings2 = &pmif->timings[unit+2];
 788
 789        /* Copy timings to local image */
 790        tl[0] = *timings;
 791        tl[1] = *timings2;
 792
 793        if (speed >= XFER_UDMA_0) {
 794                if (pmif->kind == controller_kl_ata4)
 795                        ret = set_timings_udma_ata4(&tl[0], speed);
 796                else if (pmif->kind == controller_un_ata6
 797                         || pmif->kind == controller_k2_ata6)
 798                        ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
 799                else if (pmif->kind == controller_sh_ata6)
 800                        ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
 801                else
 802                        ret = -1;
 803        } else
 804                set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
 805
 806        if (ret)
 807                return;
 808
 809        /* Apply timings to controller */
 810        *timings = tl[0];
 811        *timings2 = tl[1];
 812
 813        pmac_ide_do_update_timings(drive);      
 814}
 815
 816/*
 817 * Blast some well known "safe" values to the timing registers at init or
 818 * wakeup from sleep time, before we do real calculation
 819 */
 820static void
 821sanitize_timings(pmac_ide_hwif_t *pmif)
 822{
 823        unsigned int value, value2 = 0;
 824        
 825        switch(pmif->kind) {
 826                case controller_sh_ata6:
 827                        value = 0x0a820c97;
 828                        value2 = 0x00033031;
 829                        break;
 830                case controller_un_ata6:
 831                case controller_k2_ata6:
 832                        value = 0x08618a92;
 833                        value2 = 0x00002921;
 834                        break;
 835                case controller_kl_ata4:
 836                        value = 0x0008438c;
 837                        break;
 838                case controller_kl_ata3:
 839                        value = 0x00084526;
 840                        break;
 841                case controller_heathrow:
 842                case controller_ohare:
 843                default:
 844                        value = 0x00074526;
 845                        break;
 846        }
 847        pmif->timings[0] = pmif->timings[1] = value;
 848        pmif->timings[2] = pmif->timings[3] = value2;
 849}
 850
 851static int on_media_bay(pmac_ide_hwif_t *pmif)
 852{
 853        return pmif->mdev && pmif->mdev->media_bay != NULL;
 854}
 855
 856/* Suspend call back, should be called after the child devices
 857 * have actually been suspended
 858 */
 859static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
 860{
 861        /* We clear the timings */
 862        pmif->timings[0] = 0;
 863        pmif->timings[1] = 0;
 864        
 865        disable_irq(pmif->irq);
 866
 867        /* The media bay will handle itself just fine */
 868        if (on_media_bay(pmif))
 869                return 0;
 870        
 871        /* Kauai has bus control FCRs directly here */
 872        if (pmif->kauai_fcr) {
 873                u32 fcr = readl(pmif->kauai_fcr);
 874                fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
 875                writel(fcr, pmif->kauai_fcr);
 876        }
 877
 878        /* Disable the bus on older machines and the cell on kauai */
 879        ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
 880                            0);
 881
 882        return 0;
 883}
 884
 885/* Resume call back, should be called before the child devices
 886 * are resumed
 887 */
 888static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
 889{
 890        /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
 891        if (!on_media_bay(pmif)) {
 892                ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
 893                ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
 894                msleep(10);
 895                ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
 896
 897                /* Kauai has it different */
 898                if (pmif->kauai_fcr) {
 899                        u32 fcr = readl(pmif->kauai_fcr);
 900                        fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
 901                        writel(fcr, pmif->kauai_fcr);
 902                }
 903
 904                msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
 905        }
 906
 907        /* Sanitize drive timings */
 908        sanitize_timings(pmif);
 909
 910        enable_irq(pmif->irq);
 911
 912        return 0;
 913}
 914
 915static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
 916{
 917        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 918        struct device_node *np = pmif->node;
 919        const char *cable = of_get_property(np, "cable-type", NULL);
 920        struct device_node *root = of_find_node_by_path("/");
 921        const char *model = of_get_property(root, "model", NULL);
 922
 923        /* Get cable type from device-tree. */
 924        if (cable && !strncmp(cable, "80-", 3)) {
 925                /* Some drives fail to detect 80c cable in PowerBook */
 926                /* These machine use proprietary short IDE cable anyway */
 927                if (!strncmp(model, "PowerBook", 9))
 928                        return ATA_CBL_PATA40_SHORT;
 929                else
 930                        return ATA_CBL_PATA80;
 931        }
 932
 933        /*
 934         * G5's seem to have incorrect cable type in device-tree.
 935         * Let's assume they have a 80 conductor cable, this seem
 936         * to be always the case unless the user mucked around.
 937         */
 938        if (of_device_is_compatible(np, "K2-UATA") ||
 939            of_device_is_compatible(np, "shasta-ata"))
 940                return ATA_CBL_PATA80;
 941
 942        return ATA_CBL_PATA40;
 943}
 944
 945static void pmac_ide_init_dev(ide_drive_t *drive)
 946{
 947        ide_hwif_t *hwif = drive->hwif;
 948        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 949
 950        if (on_media_bay(pmif)) {
 951                if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
 952                        drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
 953                        return;
 954                }
 955                drive->dev_flags |= IDE_DFLAG_NOPROBE;
 956        }
 957}
 958
 959static const struct ide_tp_ops pmac_tp_ops = {
 960        .exec_command           = pmac_exec_command,
 961        .read_status            = ide_read_status,
 962        .read_altstatus         = ide_read_altstatus,
 963        .write_devctl           = pmac_write_devctl,
 964
 965        .dev_select             = pmac_dev_select,
 966        .tf_load                = ide_tf_load,
 967        .tf_read                = ide_tf_read,
 968
 969        .input_data             = ide_input_data,
 970        .output_data            = ide_output_data,
 971};
 972
 973static const struct ide_tp_ops pmac_ata6_tp_ops = {
 974        .exec_command           = pmac_exec_command,
 975        .read_status            = ide_read_status,
 976        .read_altstatus         = ide_read_altstatus,
 977        .write_devctl           = pmac_write_devctl,
 978
 979        .dev_select             = pmac_kauai_dev_select,
 980        .tf_load                = ide_tf_load,
 981        .tf_read                = ide_tf_read,
 982
 983        .input_data             = ide_input_data,
 984        .output_data            = ide_output_data,
 985};
 986
 987static const struct ide_port_ops pmac_ide_ata4_port_ops = {
 988        .init_dev               = pmac_ide_init_dev,
 989        .set_pio_mode           = pmac_ide_set_pio_mode,
 990        .set_dma_mode           = pmac_ide_set_dma_mode,
 991        .cable_detect           = pmac_ide_cable_detect,
 992};
 993
 994static const struct ide_port_ops pmac_ide_port_ops = {
 995        .init_dev               = pmac_ide_init_dev,
 996        .set_pio_mode           = pmac_ide_set_pio_mode,
 997        .set_dma_mode           = pmac_ide_set_dma_mode,
 998};
 999
1000static const struct ide_dma_ops pmac_dma_ops;
1001
1002static const struct ide_port_info pmac_port_info = {
1003        .name                   = DRV_NAME,
1004        .init_dma               = pmac_ide_init_dma,
1005        .chipset                = ide_pmac,
1006        .tp_ops                 = &pmac_tp_ops,
1007        .port_ops               = &pmac_ide_port_ops,
1008        .dma_ops                = &pmac_dma_ops,
1009        .host_flags             = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1010                                  IDE_HFLAG_POST_SET_MODE |
1011                                  IDE_HFLAG_MMIO |
1012                                  IDE_HFLAG_UNMASK_IRQS,
1013        .pio_mask               = ATA_PIO4,
1014        .mwdma_mask             = ATA_MWDMA2,
1015};
1016
1017/*
1018 * Setup, register & probe an IDE channel driven by this driver, this is
1019 * called by one of the 2 probe functions (macio or PCI).
1020 */
1021static int pmac_ide_setup_device(pmac_ide_hwif_t *pmif, struct ide_hw *hw)
1022{
1023        struct device_node *np = pmif->node;
1024        const int *bidp;
1025        struct ide_host *host;
1026        ide_hwif_t *hwif;
1027        struct ide_hw *hws[] = { hw };
1028        struct ide_port_info d = pmac_port_info;
1029        int rc;
1030
1031        pmif->broken_dma = pmif->broken_dma_warn = 0;
1032        if (of_device_is_compatible(np, "shasta-ata")) {
1033                pmif->kind = controller_sh_ata6;
1034                d.tp_ops = &pmac_ata6_tp_ops;
1035                d.port_ops = &pmac_ide_ata4_port_ops;
1036                d.udma_mask = ATA_UDMA6;
1037        } else if (of_device_is_compatible(np, "kauai-ata")) {
1038                pmif->kind = controller_un_ata6;
1039                d.tp_ops = &pmac_ata6_tp_ops;
1040                d.port_ops = &pmac_ide_ata4_port_ops;
1041                d.udma_mask = ATA_UDMA5;
1042        } else if (of_device_is_compatible(np, "K2-UATA")) {
1043                pmif->kind = controller_k2_ata6;
1044                d.tp_ops = &pmac_ata6_tp_ops;
1045                d.port_ops = &pmac_ide_ata4_port_ops;
1046                d.udma_mask = ATA_UDMA5;
1047        } else if (of_device_is_compatible(np, "keylargo-ata")) {
1048                if (strcmp(np->name, "ata-4") == 0) {
1049                        pmif->kind = controller_kl_ata4;
1050                        d.port_ops = &pmac_ide_ata4_port_ops;
1051                        d.udma_mask = ATA_UDMA4;
1052                } else
1053                        pmif->kind = controller_kl_ata3;
1054        } else if (of_device_is_compatible(np, "heathrow-ata")) {
1055                pmif->kind = controller_heathrow;
1056        } else {
1057                pmif->kind = controller_ohare;
1058                pmif->broken_dma = 1;
1059        }
1060
1061        bidp = of_get_property(np, "AAPL,bus-id", NULL);
1062        pmif->aapl_bus_id =  bidp ? *bidp : 0;
1063
1064        /* On Kauai-type controllers, we make sure the FCR is correct */
1065        if (pmif->kauai_fcr)
1066                writel(KAUAI_FCR_UATA_MAGIC |
1067                       KAUAI_FCR_UATA_RESET_N |
1068                       KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1069        
1070        /* Make sure we have sane timings */
1071        sanitize_timings(pmif);
1072
1073        /* If we are on a media bay, wait for it to settle and lock it */
1074        if (pmif->mdev)
1075                lock_media_bay(pmif->mdev->media_bay);
1076
1077        host = ide_host_alloc(&d, hws, 1);
1078        if (host == NULL) {
1079                rc = -ENOMEM;
1080                goto bail;
1081        }
1082        hwif = pmif->hwif = host->ports[0];
1083
1084        if (on_media_bay(pmif)) {
1085                /* Fixup bus ID for media bay */
1086                if (!bidp)
1087                        pmif->aapl_bus_id = 1;
1088        } else if (pmif->kind == controller_ohare) {
1089                /* The code below is having trouble on some ohare machines
1090                 * (timing related ?). Until I can put my hand on one of these
1091                 * units, I keep the old way
1092                 */
1093                ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1094        } else {
1095                /* This is necessary to enable IDE when net-booting */
1096                ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1097                ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1098                msleep(10);
1099                ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1100                msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1101        }
1102
1103        printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1104               "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1105               pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1106               on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
1107
1108        rc = ide_host_register(host, &d, hws);
1109        if (rc)
1110                pmif->hwif = NULL;
1111
1112        if (pmif->mdev)
1113                unlock_media_bay(pmif->mdev->media_bay);
1114
1115 bail:
1116        if (rc && host)
1117                ide_host_free(host);
1118        return rc;
1119}
1120
1121static void pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
1122{
1123        int i;
1124
1125        for (i = 0; i < 8; ++i)
1126                hw->io_ports_array[i] = base + i * 0x10;
1127
1128        hw->io_ports.ctl_addr = base + 0x160;
1129}
1130
1131/*
1132 * Attach to a macio probed interface
1133 */
1134static int pmac_ide_macio_attach(struct macio_dev *mdev,
1135                                 const struct of_device_id *match)
1136{
1137        void __iomem *base;
1138        unsigned long regbase;
1139        pmac_ide_hwif_t *pmif;
1140        int irq, rc;
1141        struct ide_hw hw;
1142
1143        pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1144        if (pmif == NULL)
1145                return -ENOMEM;
1146
1147        if (macio_resource_count(mdev) == 0) {
1148                printk(KERN_WARNING "ide-pmac: no address for %s\n",
1149                                    mdev->ofdev.dev.of_node->full_name);
1150                rc = -ENXIO;
1151                goto out_free_pmif;
1152        }
1153
1154        /* Request memory resource for IO ports */
1155        if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1156                printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1157                                "%s!\n", mdev->ofdev.dev.of_node->full_name);
1158                rc = -EBUSY;
1159                goto out_free_pmif;
1160        }
1161                        
1162        /* XXX This is bogus. Should be fixed in the registry by checking
1163         * the kind of host interrupt controller, a bit like gatwick
1164         * fixes in irq.c. That works well enough for the single case
1165         * where that happens though...
1166         */
1167        if (macio_irq_count(mdev) == 0) {
1168                printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1169                                    "13\n", mdev->ofdev.dev.of_node->full_name);
1170                irq = irq_create_mapping(NULL, 13);
1171        } else
1172                irq = macio_irq(mdev, 0);
1173
1174        base = ioremap(macio_resource_start(mdev, 0), 0x400);
1175        regbase = (unsigned long) base;
1176
1177        pmif->mdev = mdev;
1178        pmif->node = mdev->ofdev.dev.of_node;
1179        pmif->regbase = regbase;
1180        pmif->irq = irq;
1181        pmif->kauai_fcr = NULL;
1182
1183        if (macio_resource_count(mdev) >= 2) {
1184                if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1185                        printk(KERN_WARNING "ide-pmac: can't request DMA "
1186                                            "resource for %s!\n",
1187                                            mdev->ofdev.dev.of_node->full_name);
1188                else
1189                        pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1190        } else
1191                pmif->dma_regs = NULL;
1192
1193        dev_set_drvdata(&mdev->ofdev.dev, pmif);
1194
1195        memset(&hw, 0, sizeof(hw));
1196        pmac_ide_init_ports(&hw, pmif->regbase);
1197        hw.irq = irq;
1198        hw.dev = &mdev->bus->pdev->dev;
1199        hw.parent = &mdev->ofdev.dev;
1200
1201        rc = pmac_ide_setup_device(pmif, &hw);
1202        if (rc != 0) {
1203                /* The inteface is released to the common IDE layer */
1204                dev_set_drvdata(&mdev->ofdev.dev, NULL);
1205                iounmap(base);
1206                if (pmif->dma_regs) {
1207                        iounmap(pmif->dma_regs);
1208                        macio_release_resource(mdev, 1);
1209                }
1210                macio_release_resource(mdev, 0);
1211                kfree(pmif);
1212        }
1213
1214        return rc;
1215
1216out_free_pmif:
1217        kfree(pmif);
1218        return rc;
1219}
1220
1221static int
1222pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1223{
1224        pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1225        int rc = 0;
1226
1227        if (mesg.event != mdev->ofdev.dev.power.power_state.event
1228                        && (mesg.event & PM_EVENT_SLEEP)) {
1229                rc = pmac_ide_do_suspend(pmif);
1230                if (rc == 0)
1231                        mdev->ofdev.dev.power.power_state = mesg;
1232        }
1233
1234        return rc;
1235}
1236
1237static int
1238pmac_ide_macio_resume(struct macio_dev *mdev)
1239{
1240        pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1241        int rc = 0;
1242
1243        if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1244                rc = pmac_ide_do_resume(pmif);
1245                if (rc == 0)
1246                        mdev->ofdev.dev.power.power_state = PMSG_ON;
1247        }
1248
1249        return rc;
1250}
1251
1252/*
1253 * Attach to a PCI probed interface
1254 */
1255static int pmac_ide_pci_attach(struct pci_dev *pdev,
1256                               const struct pci_device_id *id)
1257{
1258        struct device_node *np;
1259        pmac_ide_hwif_t *pmif;
1260        void __iomem *base;
1261        unsigned long rbase, rlen;
1262        int rc;
1263        struct ide_hw hw;
1264
1265        np = pci_device_to_OF_node(pdev);
1266        if (np == NULL) {
1267                printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1268                return -ENODEV;
1269        }
1270
1271        pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1272        if (pmif == NULL)
1273                return -ENOMEM;
1274
1275        if (pci_enable_device(pdev)) {
1276                printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1277                                    "%s\n", np->full_name);
1278                rc = -ENXIO;
1279                goto out_free_pmif;
1280        }
1281        pci_set_master(pdev);
1282                        
1283        if (pci_request_regions(pdev, "Kauai ATA")) {
1284                printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1285                                "%s\n", np->full_name);
1286                rc = -ENXIO;
1287                goto out_free_pmif;
1288        }
1289
1290        pmif->mdev = NULL;
1291        pmif->node = np;
1292
1293        rbase = pci_resource_start(pdev, 0);
1294        rlen = pci_resource_len(pdev, 0);
1295
1296        base = ioremap(rbase, rlen);
1297        pmif->regbase = (unsigned long) base + 0x2000;
1298        pmif->dma_regs = base + 0x1000;
1299        pmif->kauai_fcr = base;
1300        pmif->irq = pdev->irq;
1301
1302        pci_set_drvdata(pdev, pmif);
1303
1304        memset(&hw, 0, sizeof(hw));
1305        pmac_ide_init_ports(&hw, pmif->regbase);
1306        hw.irq = pdev->irq;
1307        hw.dev = &pdev->dev;
1308
1309        rc = pmac_ide_setup_device(pmif, &hw);
1310        if (rc != 0) {
1311                /* The inteface is released to the common IDE layer */
1312                iounmap(base);
1313                pci_release_regions(pdev);
1314                kfree(pmif);
1315        }
1316
1317        return rc;
1318
1319out_free_pmif:
1320        kfree(pmif);
1321        return rc;
1322}
1323
1324static int
1325pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1326{
1327        pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1328        int rc = 0;
1329
1330        if (mesg.event != pdev->dev.power.power_state.event
1331                        && (mesg.event & PM_EVENT_SLEEP)) {
1332                rc = pmac_ide_do_suspend(pmif);
1333                if (rc == 0)
1334                        pdev->dev.power.power_state = mesg;
1335        }
1336
1337        return rc;
1338}
1339
1340static int
1341pmac_ide_pci_resume(struct pci_dev *pdev)
1342{
1343        pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1344        int rc = 0;
1345
1346        if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1347                rc = pmac_ide_do_resume(pmif);
1348                if (rc == 0)
1349                        pdev->dev.power.power_state = PMSG_ON;
1350        }
1351
1352        return rc;
1353}
1354
1355#ifdef CONFIG_PMAC_MEDIABAY
1356static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
1357{
1358        pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1359
1360        switch(mb_state) {
1361        case MB_CD:
1362                if (!pmif->hwif->present)
1363                        ide_port_scan(pmif->hwif);
1364                break;
1365        default:
1366                if (pmif->hwif->present)
1367                        ide_port_unregister_devices(pmif->hwif);
1368        }
1369}
1370#endif /* CONFIG_PMAC_MEDIABAY */
1371
1372
1373static struct of_device_id pmac_ide_macio_match[] = 
1374{
1375        {
1376        .name           = "IDE",
1377        },
1378        {
1379        .name           = "ATA",
1380        },
1381        {
1382        .type           = "ide",
1383        },
1384        {
1385        .type           = "ata",
1386        },
1387        {},
1388};
1389
1390static struct macio_driver pmac_ide_macio_driver = 
1391{
1392        .driver = {
1393                .name           = "ide-pmac",
1394                .owner          = THIS_MODULE,
1395                .of_match_table = pmac_ide_macio_match,
1396        },
1397        .probe          = pmac_ide_macio_attach,
1398        .suspend        = pmac_ide_macio_suspend,
1399        .resume         = pmac_ide_macio_resume,
1400#ifdef CONFIG_PMAC_MEDIABAY
1401        .mediabay_event = pmac_ide_macio_mb_event,
1402#endif
1403};
1404
1405static const struct pci_device_id pmac_ide_pci_match[] = {
1406        { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA),    0 },
1407        { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100),  0 },
1408        { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100),    0 },
1409        { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA),       0 },
1410        { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA),    0 },
1411        {},
1412};
1413
1414static struct pci_driver pmac_ide_pci_driver = {
1415        .name           = "ide-pmac",
1416        .id_table       = pmac_ide_pci_match,
1417        .probe          = pmac_ide_pci_attach,
1418        .suspend        = pmac_ide_pci_suspend,
1419        .resume         = pmac_ide_pci_resume,
1420};
1421MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1422
1423int __init pmac_ide_probe(void)
1424{
1425        int error;
1426
1427        if (!machine_is(powermac))
1428                return -ENODEV;
1429
1430#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1431        error = pci_register_driver(&pmac_ide_pci_driver);
1432        if (error)
1433                goto out;
1434        error = macio_register_driver(&pmac_ide_macio_driver);
1435        if (error) {
1436                pci_unregister_driver(&pmac_ide_pci_driver);
1437                goto out;
1438        }
1439#else
1440        error = macio_register_driver(&pmac_ide_macio_driver);
1441        if (error)
1442                goto out;
1443        error = pci_register_driver(&pmac_ide_pci_driver);
1444        if (error) {
1445                macio_unregister_driver(&pmac_ide_macio_driver);
1446                goto out;
1447        }
1448#endif
1449out:
1450        return error;
1451}
1452
1453/*
1454 * pmac_ide_build_dmatable builds the DBDMA command list
1455 * for a transfer and sets the DBDMA channel to point to it.
1456 */
1457static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
1458{
1459        ide_hwif_t *hwif = drive->hwif;
1460        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1461        struct dbdma_cmd *table;
1462        volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1463        struct scatterlist *sg;
1464        int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1465        int i = cmd->sg_nents, count = 0;
1466
1467        /* DMA table is already aligned */
1468        table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1469
1470        /* Make sure DMA controller is stopped (necessary ?) */
1471        writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1472        while (readl(&dma->status) & RUN)
1473                udelay(1);
1474
1475        /* Build DBDMA commands list */
1476        sg = hwif->sg_table;
1477        while (i && sg_dma_len(sg)) {
1478                u32 cur_addr;
1479                u32 cur_len;
1480
1481                cur_addr = sg_dma_address(sg);
1482                cur_len = sg_dma_len(sg);
1483
1484                if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1485                        if (pmif->broken_dma_warn == 0) {
1486                                printk(KERN_WARNING "%s: DMA on non aligned address, "
1487                                       "switching to PIO on Ohare chipset\n", drive->name);
1488                                pmif->broken_dma_warn = 1;
1489                        }
1490                        return 0;
1491                }
1492                while (cur_len) {
1493                        unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1494
1495                        if (count++ >= MAX_DCMDS) {
1496                                printk(KERN_WARNING "%s: DMA table too small\n",
1497                                       drive->name);
1498                                return 0;
1499                        }
1500                        table->command = cpu_to_le16(wr? OUTPUT_MORE: INPUT_MORE);
1501                        table->req_count = cpu_to_le16(tc);
1502                        table->phy_addr = cpu_to_le32(cur_addr);
1503                        table->cmd_dep = 0;
1504                        table->xfer_status = 0;
1505                        table->res_count = 0;
1506                        cur_addr += tc;
1507                        cur_len -= tc;
1508                        ++table;
1509                }
1510                sg = sg_next(sg);
1511                i--;
1512        }
1513
1514        /* convert the last command to an input/output last command */
1515        if (count) {
1516                table[-1].command = cpu_to_le16(wr? OUTPUT_LAST: INPUT_LAST);
1517                /* add the stop command to the end of the list */
1518                memset(table, 0, sizeof(struct dbdma_cmd));
1519                table->command = cpu_to_le16(DBDMA_STOP);
1520                mb();
1521                writel(hwif->dmatable_dma, &dma->cmdptr);
1522                return 1;
1523        }
1524
1525        printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1526
1527        return 0; /* revert to PIO for this request */
1528}
1529
1530/*
1531 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1532 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1533 */
1534static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
1535{
1536        ide_hwif_t *hwif = drive->hwif;
1537        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1538        u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
1539        u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1540
1541        if (pmac_ide_build_dmatable(drive, cmd) == 0)
1542                return 1;
1543
1544        /* Apple adds 60ns to wrDataSetup on reads */
1545        if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1546                writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),
1547                        PMAC_IDE_REG(IDE_TIMING_CONFIG));
1548                (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1549        }
1550
1551        return 0;
1552}
1553
1554/*
1555 * Kick the DMA controller into life after the DMA command has been issued
1556 * to the drive.
1557 */
1558static void
1559pmac_ide_dma_start(ide_drive_t *drive)
1560{
1561        ide_hwif_t *hwif = drive->hwif;
1562        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1563        volatile struct dbdma_regs __iomem *dma;
1564
1565        dma = pmif->dma_regs;
1566
1567        writel((RUN << 16) | RUN, &dma->control);
1568        /* Make sure it gets to the controller right now */
1569        (void)readl(&dma->control);
1570}
1571
1572/*
1573 * After a DMA transfer, make sure the controller is stopped
1574 */
1575static int
1576pmac_ide_dma_end (ide_drive_t *drive)
1577{
1578        ide_hwif_t *hwif = drive->hwif;
1579        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1580        volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1581        u32 dstat;
1582
1583        dstat = readl(&dma->status);
1584        writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1585
1586        /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1587         * in theory, but with ATAPI decices doing buffer underruns, that would
1588         * cause us to disable DMA, which isn't what we want
1589         */
1590        return (dstat & (RUN|DEAD)) != RUN;
1591}
1592
1593/*
1594 * Check out that the interrupt we got was for us. We can't always know this
1595 * for sure with those Apple interfaces (well, we could on the recent ones but
1596 * that's not implemented yet), on the other hand, we don't have shared interrupts
1597 * so it's not really a problem
1598 */
1599static int
1600pmac_ide_dma_test_irq (ide_drive_t *drive)
1601{
1602        ide_hwif_t *hwif = drive->hwif;
1603        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1604        volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1605        unsigned long status, timeout;
1606
1607        /* We have to things to deal with here:
1608         * 
1609         * - The dbdma won't stop if the command was started
1610         * but completed with an error without transferring all
1611         * datas. This happens when bad blocks are met during
1612         * a multi-block transfer.
1613         * 
1614         * - The dbdma fifo hasn't yet finished flushing to
1615         * to system memory when the disk interrupt occurs.
1616         * 
1617         */
1618
1619        /* If ACTIVE is cleared, the STOP command have passed and
1620         * transfer is complete.
1621         */
1622        status = readl(&dma->status);
1623        if (!(status & ACTIVE))
1624                return 1;
1625
1626        /* If dbdma didn't execute the STOP command yet, the
1627         * active bit is still set. We consider that we aren't
1628         * sharing interrupts (which is hopefully the case with
1629         * those controllers) and so we just try to flush the
1630         * channel for pending data in the fifo
1631         */
1632        udelay(1);
1633        writel((FLUSH << 16) | FLUSH, &dma->control);
1634        timeout = 0;
1635        for (;;) {
1636                udelay(1);
1637                status = readl(&dma->status);
1638                if ((status & FLUSH) == 0)
1639                        break;
1640                if (++timeout > 100) {
1641                        printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
1642                               hwif->index);
1643                        break;
1644                }
1645        }       
1646        return 1;
1647}
1648
1649static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1650{
1651}
1652
1653static void
1654pmac_ide_dma_lost_irq (ide_drive_t *drive)
1655{
1656        ide_hwif_t *hwif = drive->hwif;
1657        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1658        volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1659        unsigned long status = readl(&dma->status);
1660
1661        printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1662}
1663
1664static const struct ide_dma_ops pmac_dma_ops = {
1665        .dma_host_set           = pmac_ide_dma_host_set,
1666        .dma_setup              = pmac_ide_dma_setup,
1667        .dma_start              = pmac_ide_dma_start,
1668        .dma_end                = pmac_ide_dma_end,
1669        .dma_test_irq           = pmac_ide_dma_test_irq,
1670        .dma_lost_irq           = pmac_ide_dma_lost_irq,
1671};
1672
1673/*
1674 * Allocate the data structures needed for using DMA with an interface
1675 * and fill the proper list of functions pointers
1676 */
1677static int pmac_ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
1678{
1679        pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1680        struct pci_dev *dev = to_pci_dev(hwif->dev);
1681
1682        /* We won't need pci_dev if we switch to generic consistent
1683         * DMA routines ...
1684         */
1685        if (dev == NULL || pmif->dma_regs == 0)
1686                return -ENODEV;
1687        /*
1688         * Allocate space for the DBDMA commands.
1689         * The +2 is +1 for the stop command and +1 to allow for
1690         * aligning the start address to a multiple of 16 bytes.
1691         */
1692        pmif->dma_table_cpu = dma_alloc_coherent(&dev->dev,
1693                (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1694                &hwif->dmatable_dma, GFP_KERNEL);
1695        if (pmif->dma_table_cpu == NULL) {
1696                printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1697                       hwif->name);
1698                return -ENOMEM;
1699        }
1700
1701        hwif->sg_max_nents = MAX_DCMDS;
1702
1703        return 0;
1704}
1705
1706module_init(pmac_ide_probe);
1707
1708MODULE_LICENSE("GPL");
1709