1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <linux/interrupt.h>
19#include <linux/device.h>
20#include <linux/kernel.h>
21#include <linux/sysfs.h>
22#include <linux/list.h>
23#include <linux/i2c.h>
24#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
26#include <linux/err.h>
27#include <linux/module.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30
31#include <linux/iio/iio.h>
32#include <linux/iio/sysfs.h>
33#include <linux/iio/events.h>
34#include <linux/iio/buffer.h>
35#include <linux/iio/driver.h>
36#include <linux/iio/kfifo_buf.h>
37#include <linux/iio/trigger_consumer.h>
38#include <linux/iio/triggered_buffer.h>
39
40#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
41
42
43
44
45
46
47
48#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
49#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
50#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
51#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
52#define MAX1363_SETUP_POWER_UP_INT_REF 0x10
53#define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
54
55
56#define MAX1363_SETUP_EXT_CLOCK 0x08
57#define MAX1363_SETUP_INT_CLOCK 0x00
58#define MAX1363_SETUP_UNIPOLAR 0x00
59#define MAX1363_SETUP_BIPOLAR 0x04
60#define MAX1363_SETUP_RESET 0x00
61#define MAX1363_SETUP_NORESET 0x02
62
63
64
65
66
67#define MAX1363_SETUP_MONITOR_SETUP 0x01
68
69
70#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
71#define MAX1363_MON_INT_ENABLE 0x01
72
73
74
75#define MAX1363_CONFIG_BYTE(a) ((a))
76
77#define MAX1363_CONFIG_SE 0x01
78#define MAX1363_CONFIG_DE 0x00
79#define MAX1363_CONFIG_SCAN_TO_CS 0x00
80#define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
81#define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
82#define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
83
84#define MAX1236_SCAN_MID_TO_CHANNEL 0x40
85
86
87#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
88
89#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
90
91
92#define MAX1363_CHANNEL_SEL_MASK 0x1E
93#define MAX1363_SCAN_MASK 0x60
94#define MAX1363_SE_DE_MASK 0x01
95
96#define MAX1363_MAX_CHANNELS 25
97
98
99
100
101
102struct max1363_mode {
103 int8_t conf;
104 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
105};
106
107
108enum max1363_modes {
109
110 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
111
112 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
113 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
114
115 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
116 s6to7, s0to7, s6to8, s0to8, s6to9,
117 s0to9, s6to10, s0to10, s6to11, s0to11,
118
119 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
120 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
121 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
122 d7m6to11m10, d1m0to11m10,
123};
124
125
126
127
128
129
130
131
132
133
134
135
136struct max1363_chip_info {
137 const struct iio_info *info;
138 const struct iio_chan_spec *channels;
139 int num_channels;
140 const enum max1363_modes *mode_list;
141 enum max1363_modes default_mode;
142 u16 int_vref_mv;
143 u8 num_modes;
144 u8 bits;
145};
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167struct max1363_state {
168 struct i2c_client *client;
169 u8 setupbyte;
170 u8 configbyte;
171 const struct max1363_chip_info *chip_info;
172 const struct max1363_mode *current_mode;
173 u32 requestedmask;
174 struct regulator *reg;
175
176
177
178 bool monitor_on;
179 unsigned int monitor_speed:3;
180 u8 mask_high;
181 u8 mask_low;
182
183 s16 thresh_high[8];
184 s16 thresh_low[8];
185 struct regulator *vref;
186 u32 vref_uv;
187 int (*send)(const struct i2c_client *client,
188 const char *buf, int count);
189 int (*recv)(const struct i2c_client *client,
190 char *buf, int count);
191};
192
193#define MAX1363_MODE_SINGLE(_num, _mask) { \
194 .conf = MAX1363_CHANNEL_SEL(_num) \
195 | MAX1363_CONFIG_SCAN_SINGLE_1 \
196 | MAX1363_CONFIG_SE, \
197 .modemask[0] = _mask, \
198 }
199
200#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
201 .conf = MAX1363_CHANNEL_SEL(_num) \
202 | MAX1363_CONFIG_SCAN_TO_CS \
203 | MAX1363_CONFIG_SE, \
204 .modemask[0] = _mask, \
205 }
206
207
208#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
209 .conf = MAX1363_CHANNEL_SEL(_num) \
210 | MAX1236_SCAN_MID_TO_CHANNEL \
211 | MAX1363_CONFIG_SE, \
212 .modemask[0] = _mask \
213}
214
215#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
216 .conf = MAX1363_CHANNEL_SEL(_nump) \
217 | MAX1363_CONFIG_SCAN_SINGLE_1 \
218 | MAX1363_CONFIG_DE, \
219 .modemask[0] = _mask \
220 }
221
222
223#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
224 .conf = MAX1363_CHANNEL_SEL(_num) \
225 | MAX1363_CONFIG_SCAN_TO_CS \
226 | MAX1363_CONFIG_DE, \
227 .modemask[0] = _mask \
228 }
229
230
231#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
232 .conf = MAX1363_CHANNEL_SEL(_num) \
233 | MAX1236_SCAN_MID_TO_CHANNEL \
234 | MAX1363_CONFIG_SE, \
235 .modemask[0] = _mask \
236}
237
238static const struct max1363_mode max1363_mode_table[] = {
239
240 MAX1363_MODE_SINGLE(0, 1 << 0),
241 MAX1363_MODE_SINGLE(1, 1 << 1),
242 MAX1363_MODE_SINGLE(2, 1 << 2),
243 MAX1363_MODE_SINGLE(3, 1 << 3),
244 MAX1363_MODE_SINGLE(4, 1 << 4),
245 MAX1363_MODE_SINGLE(5, 1 << 5),
246 MAX1363_MODE_SINGLE(6, 1 << 6),
247 MAX1363_MODE_SINGLE(7, 1 << 7),
248 MAX1363_MODE_SINGLE(8, 1 << 8),
249 MAX1363_MODE_SINGLE(9, 1 << 9),
250 MAX1363_MODE_SINGLE(10, 1 << 10),
251 MAX1363_MODE_SINGLE(11, 1 << 11),
252
253 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
254 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
255 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
256 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
257 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
258 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
259 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
260 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
261 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
262 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
263 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
264 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
265
266
267 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
268 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
269 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
270 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
271 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
272 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
273 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
281 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
282 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
283 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
284
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
290 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
293 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
297 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
298 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
299};
300
301static const struct max1363_mode
302*max1363_match_mode(const unsigned long *mask,
303 const struct max1363_chip_info *ci)
304{
305 int i;
306 if (mask)
307 for (i = 0; i < ci->num_modes; i++)
308 if (bitmap_subset(mask,
309 max1363_mode_table[ci->mode_list[i]].
310 modemask,
311 MAX1363_MAX_CHANNELS))
312 return &max1363_mode_table[ci->mode_list[i]];
313 return NULL;
314}
315
316static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
317 int count)
318{
319 int i, err;
320
321 for (i = err = 0; err == 0 && i < count; ++i)
322 err = i2c_smbus_write_byte(client, buf[i]);
323
324 return err ? err : count;
325}
326
327static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
328 int count)
329{
330 int i, ret;
331
332 for (i = 0; i < count; ++i) {
333 ret = i2c_smbus_read_byte(client);
334 if (ret < 0)
335 return ret;
336 buf[i] = ret;
337 }
338
339 return count;
340}
341
342static int max1363_write_basic_config(struct max1363_state *st)
343{
344 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
345
346 return st->send(st->client, tx_buf, 2);
347}
348
349static int max1363_set_scan_mode(struct max1363_state *st)
350{
351 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
352 | MAX1363_SCAN_MASK
353 | MAX1363_SE_DE_MASK);
354 st->configbyte |= st->current_mode->conf;
355
356 return max1363_write_basic_config(st);
357}
358
359static int max1363_read_single_chan(struct iio_dev *indio_dev,
360 struct iio_chan_spec const *chan,
361 int *val,
362 long m)
363{
364 int ret = 0;
365 s32 data;
366 u8 rxbuf[2];
367 struct max1363_state *st = iio_priv(indio_dev);
368 struct i2c_client *client = st->client;
369
370 mutex_lock(&indio_dev->mlock);
371
372
373
374
375
376
377
378 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
379 ret = -EBUSY;
380 goto error_ret;
381 }
382
383
384 if (st->current_mode != &max1363_mode_table[chan->address]) {
385
386 st->current_mode = &max1363_mode_table[chan->address];
387 ret = max1363_set_scan_mode(st);
388 if (ret < 0)
389 goto error_ret;
390 }
391 if (st->chip_info->bits != 8) {
392
393 data = st->recv(client, rxbuf, 2);
394 if (data < 0) {
395 ret = data;
396 goto error_ret;
397 }
398 data = (rxbuf[1] | rxbuf[0] << 8) &
399 ((1 << st->chip_info->bits) - 1);
400 } else {
401
402 data = st->recv(client, rxbuf, 1);
403 if (data < 0) {
404 ret = data;
405 goto error_ret;
406 }
407 data = rxbuf[0];
408 }
409 *val = data;
410error_ret:
411 mutex_unlock(&indio_dev->mlock);
412 return ret;
413
414}
415
416static int max1363_read_raw(struct iio_dev *indio_dev,
417 struct iio_chan_spec const *chan,
418 int *val,
419 int *val2,
420 long m)
421{
422 struct max1363_state *st = iio_priv(indio_dev);
423 int ret;
424
425 switch (m) {
426 case IIO_CHAN_INFO_RAW:
427 ret = max1363_read_single_chan(indio_dev, chan, val, m);
428 if (ret < 0)
429 return ret;
430 return IIO_VAL_INT;
431 case IIO_CHAN_INFO_SCALE:
432 *val = st->vref_uv / 1000;
433 *val2 = st->chip_info->bits;
434 return IIO_VAL_FRACTIONAL_LOG2;
435 default:
436 return -EINVAL;
437 }
438 return 0;
439}
440
441
442static const enum max1363_modes max1363_mode_list[] = {
443 _s0, _s1, _s2, _s3,
444 s0to1, s0to2, s0to3,
445 d0m1, d2m3, d1m0, d3m2,
446 d0m1to2m3, d1m0to3m2,
447};
448
449static const struct iio_event_spec max1363_events[] = {
450 {
451 .type = IIO_EV_TYPE_THRESH,
452 .dir = IIO_EV_DIR_RISING,
453 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
454 BIT(IIO_EV_INFO_ENABLE),
455 }, {
456 .type = IIO_EV_TYPE_THRESH,
457 .dir = IIO_EV_DIR_FALLING,
458 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
459 BIT(IIO_EV_INFO_ENABLE),
460 },
461};
462
463#define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
464 { \
465 .type = IIO_VOLTAGE, \
466 .indexed = 1, \
467 .channel = num, \
468 .address = addr, \
469 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
470 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
471 .datasheet_name = "AIN"#num, \
472 .scan_type = { \
473 .sign = 'u', \
474 .realbits = bits, \
475 .storagebits = (bits > 8) ? 16 : 8, \
476 .endianness = IIO_BE, \
477 }, \
478 .scan_index = si, \
479 .event_spec = ev_spec, \
480 .num_event_specs = num_ev_spec, \
481 }
482
483
484#define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
485 { \
486 .type = IIO_VOLTAGE, \
487 .differential = 1, \
488 .indexed = 1, \
489 .channel = num, \
490 .channel2 = num2, \
491 .address = addr, \
492 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
493 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
494 .datasheet_name = "AIN"#num"-AIN"#num2, \
495 .scan_type = { \
496 .sign = 's', \
497 .realbits = bits, \
498 .storagebits = (bits > 8) ? 16 : 8, \
499 .endianness = IIO_BE, \
500 }, \
501 .scan_index = si, \
502 .event_spec = ev_spec, \
503 .num_event_specs = num_ev_spec, \
504 }
505
506#define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
507 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
512 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
513 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
514 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
515 IIO_CHAN_SOFT_TIMESTAMP(8) \
516 }
517
518static const struct iio_chan_spec max1036_channels[] =
519 MAX1363_4X_CHANS(8, NULL, 0);
520static const struct iio_chan_spec max1136_channels[] =
521 MAX1363_4X_CHANS(10, NULL, 0);
522static const struct iio_chan_spec max1236_channels[] =
523 MAX1363_4X_CHANS(12, NULL, 0);
524static const struct iio_chan_spec max1361_channels[] =
525 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
526static const struct iio_chan_spec max1363_channels[] =
527 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
528
529
530static const enum max1363_modes max1236_mode_list[] = {
531 _s0, _s1, _s2, _s3,
532 s0to1, s0to2, s0to3,
533 d0m1, d2m3, d1m0, d3m2,
534 d0m1to2m3, d1m0to3m2,
535 s2to3,
536};
537
538
539static const enum max1363_modes max1238_mode_list[] = {
540 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
541 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
542 s0to7, s0to8, s0to9, s0to10, s0to11,
543 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
544 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
545 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
546 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
547 s6to7, s6to8, s6to9, s6to10, s6to11,
548 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
549};
550
551#define MAX1363_12X_CHANS(bits) { \
552 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
553 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
554 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
555 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
556 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
557 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
558 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
559 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
560 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
561 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
562 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
563 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
564 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
565 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
566 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
567 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
568 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
569 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
570 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
571 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
572 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
573 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
574 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
575 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
576 IIO_CHAN_SOFT_TIMESTAMP(24) \
577 }
578static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
579static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
580static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
581
582static const enum max1363_modes max11607_mode_list[] = {
583 _s0, _s1, _s2, _s3,
584 s0to1, s0to2, s0to3,
585 s2to3,
586 d0m1, d2m3, d1m0, d3m2,
587 d0m1to2m3, d1m0to3m2,
588};
589
590static const enum max1363_modes max11608_mode_list[] = {
591 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
592 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
593 s6to7,
594 d0m1, d2m3, d4m5, d6m7,
595 d1m0, d3m2, d5m4, d7m6,
596 d0m1to2m3, d0m1to4m5, d0m1to6m7,
597 d1m0to3m2, d1m0to5m4, d1m0to7m6,
598};
599
600#define MAX1363_8X_CHANS(bits) { \
601 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
602 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
603 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
604 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
605 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
606 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
607 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
608 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
609 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
610 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
611 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
612 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
613 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
614 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
615 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
616 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
617 IIO_CHAN_SOFT_TIMESTAMP(16) \
618}
619static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
620static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
621static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
622
623static const enum max1363_modes max11644_mode_list[] = {
624 _s0, _s1, s0to1, d0m1, d1m0,
625};
626
627#define MAX1363_2X_CHANS(bits) { \
628 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
629 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
630 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
631 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
632 IIO_CHAN_SOFT_TIMESTAMP(4) \
633 }
634
635static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
636static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
637
638enum { max1361,
639 max1362,
640 max1363,
641 max1364,
642 max1036,
643 max1037,
644 max1038,
645 max1039,
646 max1136,
647 max1137,
648 max1138,
649 max1139,
650 max1236,
651 max1237,
652 max1238,
653 max1239,
654 max11600,
655 max11601,
656 max11602,
657 max11603,
658 max11604,
659 max11605,
660 max11606,
661 max11607,
662 max11608,
663 max11609,
664 max11610,
665 max11611,
666 max11612,
667 max11613,
668 max11614,
669 max11615,
670 max11616,
671 max11617,
672 max11644,
673 max11645,
674 max11646,
675 max11647
676};
677
678static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
679 8300, 4200, 2000, 1000 };
680
681static ssize_t max1363_monitor_show_freq(struct device *dev,
682 struct device_attribute *attr,
683 char *buf)
684{
685 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
686 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
687}
688
689static ssize_t max1363_monitor_store_freq(struct device *dev,
690 struct device_attribute *attr,
691 const char *buf,
692 size_t len)
693{
694 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
695 struct max1363_state *st = iio_priv(indio_dev);
696 int i, ret;
697 unsigned long val;
698 bool found = false;
699
700 ret = kstrtoul(buf, 10, &val);
701 if (ret)
702 return -EINVAL;
703 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
704 if (val == max1363_monitor_speeds[i]) {
705 found = true;
706 break;
707 }
708 if (!found)
709 return -EINVAL;
710
711 mutex_lock(&indio_dev->mlock);
712 st->monitor_speed = i;
713 mutex_unlock(&indio_dev->mlock);
714
715 return 0;
716}
717
718static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
719 max1363_monitor_show_freq,
720 max1363_monitor_store_freq);
721
722static IIO_CONST_ATTR(sampling_frequency_available,
723 "133000 665000 33300 16600 8300 4200 2000 1000");
724
725static int max1363_read_thresh(struct iio_dev *indio_dev,
726 const struct iio_chan_spec *chan, enum iio_event_type type,
727 enum iio_event_direction dir, enum iio_event_info info, int *val,
728 int *val2)
729{
730 struct max1363_state *st = iio_priv(indio_dev);
731 if (dir == IIO_EV_DIR_FALLING)
732 *val = st->thresh_low[chan->channel];
733 else
734 *val = st->thresh_high[chan->channel];
735 return IIO_VAL_INT;
736}
737
738static int max1363_write_thresh(struct iio_dev *indio_dev,
739 const struct iio_chan_spec *chan, enum iio_event_type type,
740 enum iio_event_direction dir, enum iio_event_info info, int val,
741 int val2)
742{
743 struct max1363_state *st = iio_priv(indio_dev);
744
745 switch (st->chip_info->bits) {
746 case 10:
747 if (val > 0x3FF)
748 return -EINVAL;
749 break;
750 case 12:
751 if (val > 0xFFF)
752 return -EINVAL;
753 break;
754 }
755
756 switch (dir) {
757 case IIO_EV_DIR_FALLING:
758 st->thresh_low[chan->channel] = val;
759 break;
760 case IIO_EV_DIR_RISING:
761 st->thresh_high[chan->channel] = val;
762 break;
763 default:
764 return -EINVAL;
765 }
766
767 return 0;
768}
769
770static const u64 max1363_event_codes[] = {
771 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
772 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
785 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
786 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
787};
788
789static irqreturn_t max1363_event_handler(int irq, void *private)
790{
791 struct iio_dev *indio_dev = private;
792 struct max1363_state *st = iio_priv(indio_dev);
793 s64 timestamp = iio_get_time_ns(indio_dev);
794 unsigned long mask, loc;
795 u8 rx;
796 u8 tx[2] = { st->setupbyte,
797 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
798
799 st->recv(st->client, &rx, 1);
800 mask = rx;
801 for_each_set_bit(loc, &mask, 8)
802 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
803 st->send(st->client, tx, 2);
804
805 return IRQ_HANDLED;
806}
807
808static int max1363_read_event_config(struct iio_dev *indio_dev,
809 const struct iio_chan_spec *chan, enum iio_event_type type,
810 enum iio_event_direction dir)
811{
812 struct max1363_state *st = iio_priv(indio_dev);
813 int val;
814 int number = chan->channel;
815
816 mutex_lock(&indio_dev->mlock);
817 if (dir == IIO_EV_DIR_FALLING)
818 val = (1 << number) & st->mask_low;
819 else
820 val = (1 << number) & st->mask_high;
821 mutex_unlock(&indio_dev->mlock);
822
823 return val;
824}
825
826static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
827{
828 u8 *tx_buf;
829 int ret, i = 3, j;
830 unsigned long numelements;
831 int len;
832 const long *modemask;
833
834 if (!enabled) {
835
836 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
837 st->configbyte &= ~MAX1363_SCAN_MASK;
838 st->monitor_on = false;
839 return max1363_write_basic_config(st);
840 }
841
842
843 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
844 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
845 | MAX1363_SCAN_MASK
846 | MAX1363_SE_DE_MASK);
847 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
848 if ((st->mask_low | st->mask_high) & 0x0F) {
849 st->configbyte |= max1363_mode_table[s0to3].conf;
850 modemask = max1363_mode_table[s0to3].modemask;
851 } else if ((st->mask_low | st->mask_high) & 0x30) {
852 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
853 modemask = max1363_mode_table[d0m1to2m3].modemask;
854 } else {
855 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
856 modemask = max1363_mode_table[d1m0to3m2].modemask;
857 }
858 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
859 len = 3 * numelements + 3;
860 tx_buf = kmalloc(len, GFP_KERNEL);
861 if (!tx_buf) {
862 ret = -ENOMEM;
863 goto error_ret;
864 }
865 tx_buf[0] = st->configbyte;
866 tx_buf[1] = st->setupbyte;
867 tx_buf[2] = (st->monitor_speed << 1);
868
869
870
871
872
873 for (j = 0; j < 8; j++)
874 if (test_bit(j, modemask)) {
875
876 if (st->mask_low & (1 << j)) {
877 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
878 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
879 } else if (j < 4) {
880 tx_buf[i] = 0;
881 tx_buf[i + 1] = 0;
882 } else {
883 tx_buf[i] = 0x80;
884 tx_buf[i + 1] = 0;
885 }
886 if (st->mask_high & (1 << j)) {
887 tx_buf[i + 1] |=
888 (st->thresh_high[j] >> 8) & 0x0F;
889 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
890 } else if (j < 4) {
891 tx_buf[i + 1] |= 0x0F;
892 tx_buf[i + 2] = 0xFF;
893 } else {
894 tx_buf[i + 1] |= 0x07;
895 tx_buf[i + 2] = 0xFF;
896 }
897 i += 3;
898 }
899
900
901 ret = st->send(st->client, tx_buf, len);
902 if (ret < 0)
903 goto error_ret;
904 if (ret != len) {
905 ret = -EIO;
906 goto error_ret;
907 }
908
909
910
911
912
913
914
915
916 tx_buf[0] = st->setupbyte;
917 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
918 ret = st->send(st->client, tx_buf, 2);
919 if (ret < 0)
920 goto error_ret;
921 if (ret != 2) {
922 ret = -EIO;
923 goto error_ret;
924 }
925 ret = 0;
926 st->monitor_on = true;
927error_ret:
928
929 kfree(tx_buf);
930
931 return ret;
932}
933
934
935
936
937
938
939static inline int __max1363_check_event_mask(int thismask, int checkmask)
940{
941 int ret = 0;
942
943 if (thismask < 4) {
944 if (checkmask & ~0x0F) {
945 ret = -EBUSY;
946 goto error_ret;
947 }
948 } else if (thismask < 6) {
949 if (checkmask & ~0x30) {
950 ret = -EBUSY;
951 goto error_ret;
952 }
953 } else if (checkmask & ~0xC0)
954 ret = -EBUSY;
955error_ret:
956 return ret;
957}
958
959static int max1363_write_event_config(struct iio_dev *indio_dev,
960 const struct iio_chan_spec *chan, enum iio_event_type type,
961 enum iio_event_direction dir, int state)
962{
963 int ret = 0;
964 struct max1363_state *st = iio_priv(indio_dev);
965 u16 unifiedmask;
966 int number = chan->channel;
967
968 mutex_lock(&indio_dev->mlock);
969 unifiedmask = st->mask_low | st->mask_high;
970 if (dir == IIO_EV_DIR_FALLING) {
971
972 if (state == 0)
973 st->mask_low &= ~(1 << number);
974 else {
975 ret = __max1363_check_event_mask((1 << number),
976 unifiedmask);
977 if (ret)
978 goto error_ret;
979 st->mask_low |= (1 << number);
980 }
981 } else {
982 if (state == 0)
983 st->mask_high &= ~(1 << number);
984 else {
985 ret = __max1363_check_event_mask((1 << number),
986 unifiedmask);
987 if (ret)
988 goto error_ret;
989 st->mask_high |= (1 << number);
990 }
991 }
992
993 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
994error_ret:
995 mutex_unlock(&indio_dev->mlock);
996
997 return ret;
998}
999
1000
1001
1002
1003
1004static struct attribute *max1363_event_attributes[] = {
1005 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1006 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1007 NULL,
1008};
1009
1010static const struct attribute_group max1363_event_attribute_group = {
1011 .attrs = max1363_event_attributes,
1012};
1013
1014static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1015 const unsigned long *scan_mask)
1016{
1017 struct max1363_state *st = iio_priv(indio_dev);
1018
1019
1020
1021
1022
1023 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1024 if (!st->current_mode)
1025 return -EINVAL;
1026 max1363_set_scan_mode(st);
1027 return 0;
1028}
1029
1030static const struct iio_info max1238_info = {
1031 .read_raw = &max1363_read_raw,
1032 .driver_module = THIS_MODULE,
1033 .update_scan_mode = &max1363_update_scan_mode,
1034};
1035
1036static const struct iio_info max1363_info = {
1037 .read_event_value = &max1363_read_thresh,
1038 .write_event_value = &max1363_write_thresh,
1039 .read_event_config = &max1363_read_event_config,
1040 .write_event_config = &max1363_write_event_config,
1041 .read_raw = &max1363_read_raw,
1042 .update_scan_mode = &max1363_update_scan_mode,
1043 .driver_module = THIS_MODULE,
1044 .event_attrs = &max1363_event_attribute_group,
1045};
1046
1047
1048static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1049 [max1361] = {
1050 .bits = 10,
1051 .int_vref_mv = 2048,
1052 .mode_list = max1363_mode_list,
1053 .num_modes = ARRAY_SIZE(max1363_mode_list),
1054 .default_mode = s0to3,
1055 .channels = max1361_channels,
1056 .num_channels = ARRAY_SIZE(max1361_channels),
1057 .info = &max1363_info,
1058 },
1059 [max1362] = {
1060 .bits = 10,
1061 .int_vref_mv = 4096,
1062 .mode_list = max1363_mode_list,
1063 .num_modes = ARRAY_SIZE(max1363_mode_list),
1064 .default_mode = s0to3,
1065 .channels = max1361_channels,
1066 .num_channels = ARRAY_SIZE(max1361_channels),
1067 .info = &max1363_info,
1068 },
1069 [max1363] = {
1070 .bits = 12,
1071 .int_vref_mv = 2048,
1072 .mode_list = max1363_mode_list,
1073 .num_modes = ARRAY_SIZE(max1363_mode_list),
1074 .default_mode = s0to3,
1075 .channels = max1363_channels,
1076 .num_channels = ARRAY_SIZE(max1363_channels),
1077 .info = &max1363_info,
1078 },
1079 [max1364] = {
1080 .bits = 12,
1081 .int_vref_mv = 4096,
1082 .mode_list = max1363_mode_list,
1083 .num_modes = ARRAY_SIZE(max1363_mode_list),
1084 .default_mode = s0to3,
1085 .channels = max1363_channels,
1086 .num_channels = ARRAY_SIZE(max1363_channels),
1087 .info = &max1363_info,
1088 },
1089 [max1036] = {
1090 .bits = 8,
1091 .int_vref_mv = 4096,
1092 .mode_list = max1236_mode_list,
1093 .num_modes = ARRAY_SIZE(max1236_mode_list),
1094 .default_mode = s0to3,
1095 .info = &max1238_info,
1096 .channels = max1036_channels,
1097 .num_channels = ARRAY_SIZE(max1036_channels),
1098 },
1099 [max1037] = {
1100 .bits = 8,
1101 .int_vref_mv = 2048,
1102 .mode_list = max1236_mode_list,
1103 .num_modes = ARRAY_SIZE(max1236_mode_list),
1104 .default_mode = s0to3,
1105 .info = &max1238_info,
1106 .channels = max1036_channels,
1107 .num_channels = ARRAY_SIZE(max1036_channels),
1108 },
1109 [max1038] = {
1110 .bits = 8,
1111 .int_vref_mv = 4096,
1112 .mode_list = max1238_mode_list,
1113 .num_modes = ARRAY_SIZE(max1238_mode_list),
1114 .default_mode = s0to11,
1115 .info = &max1238_info,
1116 .channels = max1038_channels,
1117 .num_channels = ARRAY_SIZE(max1038_channels),
1118 },
1119 [max1039] = {
1120 .bits = 8,
1121 .int_vref_mv = 2048,
1122 .mode_list = max1238_mode_list,
1123 .num_modes = ARRAY_SIZE(max1238_mode_list),
1124 .default_mode = s0to11,
1125 .info = &max1238_info,
1126 .channels = max1038_channels,
1127 .num_channels = ARRAY_SIZE(max1038_channels),
1128 },
1129 [max1136] = {
1130 .bits = 10,
1131 .int_vref_mv = 4096,
1132 .mode_list = max1236_mode_list,
1133 .num_modes = ARRAY_SIZE(max1236_mode_list),
1134 .default_mode = s0to3,
1135 .info = &max1238_info,
1136 .channels = max1136_channels,
1137 .num_channels = ARRAY_SIZE(max1136_channels),
1138 },
1139 [max1137] = {
1140 .bits = 10,
1141 .int_vref_mv = 2048,
1142 .mode_list = max1236_mode_list,
1143 .num_modes = ARRAY_SIZE(max1236_mode_list),
1144 .default_mode = s0to3,
1145 .info = &max1238_info,
1146 .channels = max1136_channels,
1147 .num_channels = ARRAY_SIZE(max1136_channels),
1148 },
1149 [max1138] = {
1150 .bits = 10,
1151 .int_vref_mv = 4096,
1152 .mode_list = max1238_mode_list,
1153 .num_modes = ARRAY_SIZE(max1238_mode_list),
1154 .default_mode = s0to11,
1155 .info = &max1238_info,
1156 .channels = max1138_channels,
1157 .num_channels = ARRAY_SIZE(max1138_channels),
1158 },
1159 [max1139] = {
1160 .bits = 10,
1161 .int_vref_mv = 2048,
1162 .mode_list = max1238_mode_list,
1163 .num_modes = ARRAY_SIZE(max1238_mode_list),
1164 .default_mode = s0to11,
1165 .info = &max1238_info,
1166 .channels = max1138_channels,
1167 .num_channels = ARRAY_SIZE(max1138_channels),
1168 },
1169 [max1236] = {
1170 .bits = 12,
1171 .int_vref_mv = 4096,
1172 .mode_list = max1236_mode_list,
1173 .num_modes = ARRAY_SIZE(max1236_mode_list),
1174 .default_mode = s0to3,
1175 .info = &max1238_info,
1176 .channels = max1236_channels,
1177 .num_channels = ARRAY_SIZE(max1236_channels),
1178 },
1179 [max1237] = {
1180 .bits = 12,
1181 .int_vref_mv = 2048,
1182 .mode_list = max1236_mode_list,
1183 .num_modes = ARRAY_SIZE(max1236_mode_list),
1184 .default_mode = s0to3,
1185 .info = &max1238_info,
1186 .channels = max1236_channels,
1187 .num_channels = ARRAY_SIZE(max1236_channels),
1188 },
1189 [max1238] = {
1190 .bits = 12,
1191 .int_vref_mv = 4096,
1192 .mode_list = max1238_mode_list,
1193 .num_modes = ARRAY_SIZE(max1238_mode_list),
1194 .default_mode = s0to11,
1195 .info = &max1238_info,
1196 .channels = max1238_channels,
1197 .num_channels = ARRAY_SIZE(max1238_channels),
1198 },
1199 [max1239] = {
1200 .bits = 12,
1201 .int_vref_mv = 2048,
1202 .mode_list = max1238_mode_list,
1203 .num_modes = ARRAY_SIZE(max1238_mode_list),
1204 .default_mode = s0to11,
1205 .info = &max1238_info,
1206 .channels = max1238_channels,
1207 .num_channels = ARRAY_SIZE(max1238_channels),
1208 },
1209 [max11600] = {
1210 .bits = 8,
1211 .int_vref_mv = 4096,
1212 .mode_list = max11607_mode_list,
1213 .num_modes = ARRAY_SIZE(max11607_mode_list),
1214 .default_mode = s0to3,
1215 .info = &max1238_info,
1216 .channels = max1036_channels,
1217 .num_channels = ARRAY_SIZE(max1036_channels),
1218 },
1219 [max11601] = {
1220 .bits = 8,
1221 .int_vref_mv = 2048,
1222 .mode_list = max11607_mode_list,
1223 .num_modes = ARRAY_SIZE(max11607_mode_list),
1224 .default_mode = s0to3,
1225 .info = &max1238_info,
1226 .channels = max1036_channels,
1227 .num_channels = ARRAY_SIZE(max1036_channels),
1228 },
1229 [max11602] = {
1230 .bits = 8,
1231 .int_vref_mv = 4096,
1232 .mode_list = max11608_mode_list,
1233 .num_modes = ARRAY_SIZE(max11608_mode_list),
1234 .default_mode = s0to7,
1235 .info = &max1238_info,
1236 .channels = max11602_channels,
1237 .num_channels = ARRAY_SIZE(max11602_channels),
1238 },
1239 [max11603] = {
1240 .bits = 8,
1241 .int_vref_mv = 2048,
1242 .mode_list = max11608_mode_list,
1243 .num_modes = ARRAY_SIZE(max11608_mode_list),
1244 .default_mode = s0to7,
1245 .info = &max1238_info,
1246 .channels = max11602_channels,
1247 .num_channels = ARRAY_SIZE(max11602_channels),
1248 },
1249 [max11604] = {
1250 .bits = 8,
1251 .int_vref_mv = 4096,
1252 .mode_list = max1238_mode_list,
1253 .num_modes = ARRAY_SIZE(max1238_mode_list),
1254 .default_mode = s0to11,
1255 .info = &max1238_info,
1256 .channels = max1038_channels,
1257 .num_channels = ARRAY_SIZE(max1038_channels),
1258 },
1259 [max11605] = {
1260 .bits = 8,
1261 .int_vref_mv = 2048,
1262 .mode_list = max1238_mode_list,
1263 .num_modes = ARRAY_SIZE(max1238_mode_list),
1264 .default_mode = s0to11,
1265 .info = &max1238_info,
1266 .channels = max1038_channels,
1267 .num_channels = ARRAY_SIZE(max1038_channels),
1268 },
1269 [max11606] = {
1270 .bits = 10,
1271 .int_vref_mv = 4096,
1272 .mode_list = max11607_mode_list,
1273 .num_modes = ARRAY_SIZE(max11607_mode_list),
1274 .default_mode = s0to3,
1275 .info = &max1238_info,
1276 .channels = max1136_channels,
1277 .num_channels = ARRAY_SIZE(max1136_channels),
1278 },
1279 [max11607] = {
1280 .bits = 10,
1281 .int_vref_mv = 2048,
1282 .mode_list = max11607_mode_list,
1283 .num_modes = ARRAY_SIZE(max11607_mode_list),
1284 .default_mode = s0to3,
1285 .info = &max1238_info,
1286 .channels = max1136_channels,
1287 .num_channels = ARRAY_SIZE(max1136_channels),
1288 },
1289 [max11608] = {
1290 .bits = 10,
1291 .int_vref_mv = 4096,
1292 .mode_list = max11608_mode_list,
1293 .num_modes = ARRAY_SIZE(max11608_mode_list),
1294 .default_mode = s0to7,
1295 .info = &max1238_info,
1296 .channels = max11608_channels,
1297 .num_channels = ARRAY_SIZE(max11608_channels),
1298 },
1299 [max11609] = {
1300 .bits = 10,
1301 .int_vref_mv = 2048,
1302 .mode_list = max11608_mode_list,
1303 .num_modes = ARRAY_SIZE(max11608_mode_list),
1304 .default_mode = s0to7,
1305 .info = &max1238_info,
1306 .channels = max11608_channels,
1307 .num_channels = ARRAY_SIZE(max11608_channels),
1308 },
1309 [max11610] = {
1310 .bits = 10,
1311 .int_vref_mv = 4096,
1312 .mode_list = max1238_mode_list,
1313 .num_modes = ARRAY_SIZE(max1238_mode_list),
1314 .default_mode = s0to11,
1315 .info = &max1238_info,
1316 .channels = max1138_channels,
1317 .num_channels = ARRAY_SIZE(max1138_channels),
1318 },
1319 [max11611] = {
1320 .bits = 10,
1321 .int_vref_mv = 2048,
1322 .mode_list = max1238_mode_list,
1323 .num_modes = ARRAY_SIZE(max1238_mode_list),
1324 .default_mode = s0to11,
1325 .info = &max1238_info,
1326 .channels = max1138_channels,
1327 .num_channels = ARRAY_SIZE(max1138_channels),
1328 },
1329 [max11612] = {
1330 .bits = 12,
1331 .int_vref_mv = 4096,
1332 .mode_list = max11607_mode_list,
1333 .num_modes = ARRAY_SIZE(max11607_mode_list),
1334 .default_mode = s0to3,
1335 .info = &max1238_info,
1336 .channels = max1363_channels,
1337 .num_channels = ARRAY_SIZE(max1363_channels),
1338 },
1339 [max11613] = {
1340 .bits = 12,
1341 .int_vref_mv = 2048,
1342 .mode_list = max11607_mode_list,
1343 .num_modes = ARRAY_SIZE(max11607_mode_list),
1344 .default_mode = s0to3,
1345 .info = &max1238_info,
1346 .channels = max1363_channels,
1347 .num_channels = ARRAY_SIZE(max1363_channels),
1348 },
1349 [max11614] = {
1350 .bits = 12,
1351 .int_vref_mv = 4096,
1352 .mode_list = max11608_mode_list,
1353 .num_modes = ARRAY_SIZE(max11608_mode_list),
1354 .default_mode = s0to7,
1355 .info = &max1238_info,
1356 .channels = max11614_channels,
1357 .num_channels = ARRAY_SIZE(max11614_channels),
1358 },
1359 [max11615] = {
1360 .bits = 12,
1361 .int_vref_mv = 2048,
1362 .mode_list = max11608_mode_list,
1363 .num_modes = ARRAY_SIZE(max11608_mode_list),
1364 .default_mode = s0to7,
1365 .info = &max1238_info,
1366 .channels = max11614_channels,
1367 .num_channels = ARRAY_SIZE(max11614_channels),
1368 },
1369 [max11616] = {
1370 .bits = 12,
1371 .int_vref_mv = 4096,
1372 .mode_list = max1238_mode_list,
1373 .num_modes = ARRAY_SIZE(max1238_mode_list),
1374 .default_mode = s0to11,
1375 .info = &max1238_info,
1376 .channels = max1238_channels,
1377 .num_channels = ARRAY_SIZE(max1238_channels),
1378 },
1379 [max11617] = {
1380 .bits = 12,
1381 .int_vref_mv = 2048,
1382 .mode_list = max1238_mode_list,
1383 .num_modes = ARRAY_SIZE(max1238_mode_list),
1384 .default_mode = s0to11,
1385 .info = &max1238_info,
1386 .channels = max1238_channels,
1387 .num_channels = ARRAY_SIZE(max1238_channels),
1388 },
1389 [max11644] = {
1390 .bits = 12,
1391 .int_vref_mv = 4096,
1392 .mode_list = max11644_mode_list,
1393 .num_modes = ARRAY_SIZE(max11644_mode_list),
1394 .default_mode = s0to1,
1395 .info = &max1238_info,
1396 .channels = max11644_channels,
1397 .num_channels = ARRAY_SIZE(max11644_channels),
1398 },
1399 [max11645] = {
1400 .bits = 12,
1401 .int_vref_mv = 2048,
1402 .mode_list = max11644_mode_list,
1403 .num_modes = ARRAY_SIZE(max11644_mode_list),
1404 .default_mode = s0to1,
1405 .info = &max1238_info,
1406 .channels = max11644_channels,
1407 .num_channels = ARRAY_SIZE(max11644_channels),
1408 },
1409 [max11646] = {
1410 .bits = 10,
1411 .int_vref_mv = 4096,
1412 .mode_list = max11644_mode_list,
1413 .num_modes = ARRAY_SIZE(max11644_mode_list),
1414 .default_mode = s0to1,
1415 .info = &max1238_info,
1416 .channels = max11646_channels,
1417 .num_channels = ARRAY_SIZE(max11646_channels),
1418 },
1419 [max11647] = {
1420 .bits = 10,
1421 .int_vref_mv = 2048,
1422 .mode_list = max11644_mode_list,
1423 .num_modes = ARRAY_SIZE(max11644_mode_list),
1424 .default_mode = s0to1,
1425 .info = &max1238_info,
1426 .channels = max11646_channels,
1427 .num_channels = ARRAY_SIZE(max11646_channels),
1428 },
1429};
1430
1431static int max1363_initial_setup(struct max1363_state *st)
1432{
1433 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1434 | MAX1363_SETUP_UNIPOLAR
1435 | MAX1363_SETUP_NORESET;
1436
1437 if (st->vref)
1438 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1439 else
1440 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1441 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1442
1443
1444 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1445 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1446 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1447
1448 return max1363_set_scan_mode(st);
1449}
1450
1451static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1452{
1453 struct max1363_state *st = iio_priv(indio_dev);
1454 unsigned long *masks;
1455 int i;
1456
1457 masks = devm_kzalloc(&indio_dev->dev,
1458 BITS_TO_LONGS(MAX1363_MAX_CHANNELS) * sizeof(long) *
1459 (st->chip_info->num_modes + 1), GFP_KERNEL);
1460 if (!masks)
1461 return -ENOMEM;
1462
1463 for (i = 0; i < st->chip_info->num_modes; i++)
1464 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1465 max1363_mode_table[st->chip_info->mode_list[i]]
1466 .modemask, MAX1363_MAX_CHANNELS);
1467
1468 indio_dev->available_scan_masks = masks;
1469
1470 return 0;
1471}
1472
1473static irqreturn_t max1363_trigger_handler(int irq, void *p)
1474{
1475 struct iio_poll_func *pf = p;
1476 struct iio_dev *indio_dev = pf->indio_dev;
1477 struct max1363_state *st = iio_priv(indio_dev);
1478 __u8 *rxbuf;
1479 int b_sent;
1480 size_t d_size;
1481 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1482 MAX1363_MAX_CHANNELS);
1483
1484
1485 if (st->chip_info->bits != 8)
1486 d_size = numvals*2;
1487 else
1488 d_size = numvals;
1489 if (indio_dev->scan_timestamp) {
1490 d_size += sizeof(s64);
1491 if (d_size % sizeof(s64))
1492 d_size += sizeof(s64) - (d_size % sizeof(s64));
1493 }
1494
1495
1496
1497
1498 if (numvals == 0)
1499 goto done;
1500
1501 rxbuf = kmalloc(d_size, GFP_KERNEL);
1502 if (rxbuf == NULL)
1503 goto done;
1504 if (st->chip_info->bits != 8)
1505 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1506 else
1507 b_sent = st->recv(st->client, rxbuf, numvals);
1508 if (b_sent < 0)
1509 goto done_free;
1510
1511 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1512 iio_get_time_ns(indio_dev));
1513
1514done_free:
1515 kfree(rxbuf);
1516done:
1517 iio_trigger_notify_done(indio_dev->trig);
1518
1519 return IRQ_HANDLED;
1520}
1521
1522#ifdef CONFIG_OF
1523
1524#define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1525 .compatible = of_compatible, \
1526 .data = &max1363_chip_info_tbl[cfg], \
1527}
1528
1529static const struct of_device_id max1363_of_match[] = {
1530 MAX1363_COMPATIBLE("maxim,max1361", max1361),
1531 MAX1363_COMPATIBLE("maxim,max1362", max1362),
1532 MAX1363_COMPATIBLE("maxim,max1363", max1363),
1533 MAX1363_COMPATIBLE("maxim,max1364", max1364),
1534 MAX1363_COMPATIBLE("maxim,max1036", max1036),
1535 MAX1363_COMPATIBLE("maxim,max1037", max1037),
1536 MAX1363_COMPATIBLE("maxim,max1038", max1038),
1537 MAX1363_COMPATIBLE("maxim,max1039", max1039),
1538 MAX1363_COMPATIBLE("maxim,max1136", max1136),
1539 MAX1363_COMPATIBLE("maxim,max1137", max1137),
1540 MAX1363_COMPATIBLE("maxim,max1138", max1138),
1541 MAX1363_COMPATIBLE("maxim,max1139", max1139),
1542 MAX1363_COMPATIBLE("maxim,max1236", max1236),
1543 MAX1363_COMPATIBLE("maxim,max1237", max1237),
1544 MAX1363_COMPATIBLE("maxim,max1238", max1238),
1545 MAX1363_COMPATIBLE("maxim,max1239", max1239),
1546 MAX1363_COMPATIBLE("maxim,max11600", max11600),
1547 MAX1363_COMPATIBLE("maxim,max11601", max11601),
1548 MAX1363_COMPATIBLE("maxim,max11602", max11602),
1549 MAX1363_COMPATIBLE("maxim,max11603", max11603),
1550 MAX1363_COMPATIBLE("maxim,max11604", max11604),
1551 MAX1363_COMPATIBLE("maxim,max11605", max11605),
1552 MAX1363_COMPATIBLE("maxim,max11606", max11606),
1553 MAX1363_COMPATIBLE("maxim,max11607", max11607),
1554 MAX1363_COMPATIBLE("maxim,max11608", max11608),
1555 MAX1363_COMPATIBLE("maxim,max11609", max11609),
1556 MAX1363_COMPATIBLE("maxim,max11610", max11610),
1557 MAX1363_COMPATIBLE("maxim,max11611", max11611),
1558 MAX1363_COMPATIBLE("maxim,max11612", max11612),
1559 MAX1363_COMPATIBLE("maxim,max11613", max11613),
1560 MAX1363_COMPATIBLE("maxim,max11614", max11614),
1561 MAX1363_COMPATIBLE("maxim,max11615", max11615),
1562 MAX1363_COMPATIBLE("maxim,max11616", max11616),
1563 MAX1363_COMPATIBLE("maxim,max11617", max11617),
1564 MAX1363_COMPATIBLE("maxim,max11644", max11644),
1565 MAX1363_COMPATIBLE("maxim,max11645", max11645),
1566 MAX1363_COMPATIBLE("maxim,max11646", max11646),
1567 MAX1363_COMPATIBLE("maxim,max11647", max11647),
1568 { }
1569};
1570MODULE_DEVICE_TABLE(of, max1363_of_match);
1571#endif
1572
1573static int max1363_probe(struct i2c_client *client,
1574 const struct i2c_device_id *id)
1575{
1576 int ret;
1577 struct max1363_state *st;
1578 struct iio_dev *indio_dev;
1579 struct regulator *vref;
1580 const struct of_device_id *match;
1581
1582 indio_dev = devm_iio_device_alloc(&client->dev,
1583 sizeof(struct max1363_state));
1584 if (!indio_dev)
1585 return -ENOMEM;
1586
1587 indio_dev->dev.of_node = client->dev.of_node;
1588 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1589 if (ret < 0)
1590 return ret;
1591
1592 st = iio_priv(indio_dev);
1593
1594 st->reg = devm_regulator_get(&client->dev, "vcc");
1595 if (IS_ERR(st->reg)) {
1596 ret = PTR_ERR(st->reg);
1597 goto error_unregister_map;
1598 }
1599
1600 ret = regulator_enable(st->reg);
1601 if (ret)
1602 goto error_unregister_map;
1603
1604
1605 i2c_set_clientdata(client, indio_dev);
1606
1607 match = of_match_device(of_match_ptr(max1363_of_match),
1608 &client->dev);
1609 if (match)
1610 st->chip_info = of_device_get_match_data(&client->dev);
1611 else
1612 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1613 st->client = client;
1614
1615 st->vref_uv = st->chip_info->int_vref_mv * 1000;
1616 vref = devm_regulator_get_optional(&client->dev, "vref");
1617 if (!IS_ERR(vref)) {
1618 int vref_uv;
1619
1620 ret = regulator_enable(vref);
1621 if (ret)
1622 goto error_disable_reg;
1623 st->vref = vref;
1624 vref_uv = regulator_get_voltage(vref);
1625 if (vref_uv <= 0) {
1626 ret = -EINVAL;
1627 goto error_disable_reg;
1628 }
1629 st->vref_uv = vref_uv;
1630 }
1631
1632 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1633 st->send = i2c_master_send;
1634 st->recv = i2c_master_recv;
1635 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1636 && st->chip_info->bits == 8) {
1637 st->send = max1363_smbus_send;
1638 st->recv = max1363_smbus_recv;
1639 } else {
1640 ret = -EOPNOTSUPP;
1641 goto error_disable_reg;
1642 }
1643
1644 ret = max1363_alloc_scan_masks(indio_dev);
1645 if (ret)
1646 goto error_disable_reg;
1647
1648
1649 indio_dev->dev.parent = &client->dev;
1650 indio_dev->dev.of_node = client->dev.of_node;
1651 indio_dev->name = id->name;
1652 indio_dev->channels = st->chip_info->channels;
1653 indio_dev->num_channels = st->chip_info->num_channels;
1654 indio_dev->info = st->chip_info->info;
1655 indio_dev->modes = INDIO_DIRECT_MODE;
1656 ret = max1363_initial_setup(st);
1657 if (ret < 0)
1658 goto error_disable_reg;
1659
1660 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1661 &max1363_trigger_handler, NULL);
1662 if (ret)
1663 goto error_disable_reg;
1664
1665 if (client->irq) {
1666 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1667 NULL,
1668 &max1363_event_handler,
1669 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1670 "max1363_event",
1671 indio_dev);
1672
1673 if (ret)
1674 goto error_uninit_buffer;
1675 }
1676
1677 ret = iio_device_register(indio_dev);
1678 if (ret < 0)
1679 goto error_uninit_buffer;
1680
1681 return 0;
1682
1683error_uninit_buffer:
1684 iio_triggered_buffer_cleanup(indio_dev);
1685error_disable_reg:
1686 if (st->vref)
1687 regulator_disable(st->vref);
1688 regulator_disable(st->reg);
1689error_unregister_map:
1690 iio_map_array_unregister(indio_dev);
1691 return ret;
1692}
1693
1694static int max1363_remove(struct i2c_client *client)
1695{
1696 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1697 struct max1363_state *st = iio_priv(indio_dev);
1698
1699 iio_device_unregister(indio_dev);
1700 iio_triggered_buffer_cleanup(indio_dev);
1701 if (st->vref)
1702 regulator_disable(st->vref);
1703 regulator_disable(st->reg);
1704 iio_map_array_unregister(indio_dev);
1705
1706 return 0;
1707}
1708
1709static const struct i2c_device_id max1363_id[] = {
1710 { "max1361", max1361 },
1711 { "max1362", max1362 },
1712 { "max1363", max1363 },
1713 { "max1364", max1364 },
1714 { "max1036", max1036 },
1715 { "max1037", max1037 },
1716 { "max1038", max1038 },
1717 { "max1039", max1039 },
1718 { "max1136", max1136 },
1719 { "max1137", max1137 },
1720 { "max1138", max1138 },
1721 { "max1139", max1139 },
1722 { "max1236", max1236 },
1723 { "max1237", max1237 },
1724 { "max1238", max1238 },
1725 { "max1239", max1239 },
1726 { "max11600", max11600 },
1727 { "max11601", max11601 },
1728 { "max11602", max11602 },
1729 { "max11603", max11603 },
1730 { "max11604", max11604 },
1731 { "max11605", max11605 },
1732 { "max11606", max11606 },
1733 { "max11607", max11607 },
1734 { "max11608", max11608 },
1735 { "max11609", max11609 },
1736 { "max11610", max11610 },
1737 { "max11611", max11611 },
1738 { "max11612", max11612 },
1739 { "max11613", max11613 },
1740 { "max11614", max11614 },
1741 { "max11615", max11615 },
1742 { "max11616", max11616 },
1743 { "max11617", max11617 },
1744 { "max11644", max11644 },
1745 { "max11645", max11645 },
1746 { "max11646", max11646 },
1747 { "max11647", max11647 },
1748 {}
1749};
1750
1751MODULE_DEVICE_TABLE(i2c, max1363_id);
1752
1753static struct i2c_driver max1363_driver = {
1754 .driver = {
1755 .name = "max1363",
1756 .of_match_table = of_match_ptr(max1363_of_match),
1757 },
1758 .probe = max1363_probe,
1759 .remove = max1363_remove,
1760 .id_table = max1363_id,
1761};
1762module_i2c_driver(max1363_driver);
1763
1764MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1765MODULE_DESCRIPTION("Maxim 1363 ADC");
1766MODULE_LICENSE("GPL v2");
1767
