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16#include <linux/intel-iommu.h>
17#include <linux/mmu_notifier.h>
18#include <linux/sched.h>
19#include <linux/sched/mm.h>
20#include <linux/slab.h>
21#include <linux/intel-svm.h>
22#include <linux/rculist.h>
23#include <linux/pci.h>
24#include <linux/pci-ats.h>
25#include <linux/dmar.h>
26#include <linux/interrupt.h>
27
28static irqreturn_t prq_event_thread(int irq, void *d);
29
30struct pasid_entry {
31 u64 val;
32};
33
34struct pasid_state_entry {
35 u64 val;
36};
37
38int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
39{
40 struct page *pages;
41 int order;
42
43
44 iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
45
46
47
48
49
50
51 if (iommu->pasid_max > 0x20000)
52 iommu->pasid_max = 0x20000;
53
54 order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
55 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
56 if (!pages) {
57 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
58 iommu->name);
59 return -ENOMEM;
60 }
61 iommu->pasid_table = page_address(pages);
62 pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
63
64 if (ecap_dis(iommu->ecap)) {
65
66 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
67 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
68 if (pages)
69 iommu->pasid_state_table = page_address(pages);
70 else
71 pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
72 iommu->name);
73 }
74
75 idr_init(&iommu->pasid_idr);
76
77 return 0;
78}
79
80int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
81{
82 int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
83
84 if (iommu->pasid_table) {
85 free_pages((unsigned long)iommu->pasid_table, order);
86 iommu->pasid_table = NULL;
87 }
88 if (iommu->pasid_state_table) {
89 free_pages((unsigned long)iommu->pasid_state_table, order);
90 iommu->pasid_state_table = NULL;
91 }
92 idr_destroy(&iommu->pasid_idr);
93 return 0;
94}
95
96#define PRQ_ORDER 0
97
98int intel_svm_enable_prq(struct intel_iommu *iommu)
99{
100 struct page *pages;
101 int irq, ret;
102
103 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
104 if (!pages) {
105 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
106 iommu->name);
107 return -ENOMEM;
108 }
109 iommu->prq = page_address(pages);
110
111 irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
112 if (irq <= 0) {
113 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
114 iommu->name);
115 ret = -EINVAL;
116 err:
117 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
118 iommu->prq = NULL;
119 return ret;
120 }
121 iommu->pr_irq = irq;
122
123 snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
124
125 ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
126 iommu->prq_name, iommu);
127 if (ret) {
128 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
129 iommu->name);
130 dmar_free_hwirq(irq);
131 goto err;
132 }
133 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
134 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
135 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
136
137 return 0;
138}
139
140int intel_svm_finish_prq(struct intel_iommu *iommu)
141{
142 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
143 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
144 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
145
146 free_irq(iommu->pr_irq, iommu);
147 dmar_free_hwirq(iommu->pr_irq);
148 iommu->pr_irq = 0;
149
150 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
151 iommu->prq = NULL;
152
153 return 0;
154}
155
156static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
157 unsigned long address, unsigned long pages, int ih, int gl)
158{
159 struct qi_desc desc;
160
161 if (pages == -1) {
162
163
164
165 if (gl)
166 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
167 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
168 else
169 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
170 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
171 desc.high = 0;
172 } else {
173 int mask = ilog2(__roundup_pow_of_two(pages));
174
175 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
176 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
177 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
178 QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
179 }
180 qi_submit_sync(&desc, svm->iommu);
181
182 if (sdev->dev_iotlb) {
183 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
184 QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
185 if (pages == -1) {
186 desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
187 } else if (pages > 1) {
188
189
190
191 unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
192 unsigned long mask = __rounddown_pow_of_two(address ^ last);;
193
194 desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
195 } else {
196 desc.high = QI_DEV_EIOTLB_ADDR(address);
197 }
198 qi_submit_sync(&desc, svm->iommu);
199 }
200}
201
202static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
203 unsigned long pages, int ih, int gl)
204{
205 struct intel_svm_dev *sdev;
206
207
208 if (svm->iommu->pasid_state_table &&
209 !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
210 return;
211
212 rcu_read_lock();
213 list_for_each_entry_rcu(sdev, &svm->devs, list)
214 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
215 rcu_read_unlock();
216}
217
218static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
219 unsigned long address, pte_t pte)
220{
221 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
222
223 intel_flush_svm_range(svm, address, 1, 1, 0);
224}
225
226
227static void intel_invalidate_range(struct mmu_notifier *mn,
228 struct mm_struct *mm,
229 unsigned long start, unsigned long end)
230{
231 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
232
233 intel_flush_svm_range(svm, start,
234 (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
235}
236
237
238static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
239{
240 struct qi_desc desc;
241
242 desc.high = 0;
243 desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
244
245 qi_submit_sync(&desc, svm->iommu);
246}
247
248static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
249{
250 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
251 struct intel_svm_dev *sdev;
252
253
254
255
256
257
258
259
260
261
262
263
264
265 svm->iommu->pasid_table[svm->pasid].val = 0;
266 wmb();
267
268 rcu_read_lock();
269 list_for_each_entry_rcu(sdev, &svm->devs, list) {
270 intel_flush_pasid_dev(svm, sdev, svm->pasid);
271 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
272 }
273 rcu_read_unlock();
274
275}
276
277static const struct mmu_notifier_ops intel_mmuops = {
278 .release = intel_mm_release,
279 .change_pte = intel_change_pte,
280 .invalidate_range = intel_invalidate_range,
281};
282
283static DEFINE_MUTEX(pasid_mutex);
284
285int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
286{
287 struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
288 struct intel_svm_dev *sdev;
289 struct intel_svm *svm = NULL;
290 struct mm_struct *mm = NULL;
291 int pasid_max;
292 int ret;
293
294 if (WARN_ON(!iommu))
295 return -EINVAL;
296
297 if (dev_is_pci(dev)) {
298 pasid_max = pci_max_pasids(to_pci_dev(dev));
299 if (pasid_max < 0)
300 return -EINVAL;
301 } else
302 pasid_max = 1 << 20;
303
304 if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
305 if (!ecap_srs(iommu->ecap))
306 return -EINVAL;
307 } else if (pasid) {
308 mm = get_task_mm(current);
309 BUG_ON(!mm);
310 }
311
312 mutex_lock(&pasid_mutex);
313 if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
314 int i;
315
316 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
317 if (svm->mm != mm ||
318 (svm->flags & SVM_FLAG_PRIVATE_PASID))
319 continue;
320
321 if (svm->pasid >= pasid_max) {
322 dev_warn(dev,
323 "Limited PASID width. Cannot use existing PASID %d\n",
324 svm->pasid);
325 ret = -ENOSPC;
326 goto out;
327 }
328
329 list_for_each_entry(sdev, &svm->devs, list) {
330 if (dev == sdev->dev) {
331 if (sdev->ops != ops) {
332 ret = -EBUSY;
333 goto out;
334 }
335 sdev->users++;
336 goto success;
337 }
338 }
339
340 break;
341 }
342 }
343
344 sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
345 if (!sdev) {
346 ret = -ENOMEM;
347 goto out;
348 }
349 sdev->dev = dev;
350
351 ret = intel_iommu_enable_pasid(iommu, sdev);
352 if (ret || !pasid) {
353
354
355 kfree(sdev);
356 goto out;
357 }
358
359 sdev->users = 1;
360 sdev->ops = ops;
361 init_rcu_head(&sdev->rcu);
362
363 if (!svm) {
364 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
365 if (!svm) {
366 ret = -ENOMEM;
367 kfree(sdev);
368 goto out;
369 }
370 svm->iommu = iommu;
371
372 if (pasid_max > iommu->pasid_max)
373 pasid_max = iommu->pasid_max;
374
375
376 ret = idr_alloc(&iommu->pasid_idr, svm,
377 !!cap_caching_mode(iommu->cap),
378 pasid_max - 1, GFP_KERNEL);
379 if (ret < 0) {
380 kfree(svm);
381 goto out;
382 }
383 svm->pasid = ret;
384 svm->notifier.ops = &intel_mmuops;
385 svm->mm = mm;
386 svm->flags = flags;
387 INIT_LIST_HEAD_RCU(&svm->devs);
388 ret = -ENOMEM;
389 if (mm) {
390 ret = mmu_notifier_register(&svm->notifier, mm);
391 if (ret) {
392 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
393 kfree(svm);
394 kfree(sdev);
395 goto out;
396 }
397 iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
398 } else
399 iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
400 wmb();
401
402
403
404
405
406
407
408
409
410 if (cap_caching_mode(iommu->cap))
411 intel_flush_pasid_dev(svm, sdev, 0);
412 }
413 list_add_rcu(&sdev->list, &svm->devs);
414
415 success:
416 *pasid = svm->pasid;
417 ret = 0;
418 out:
419 mutex_unlock(&pasid_mutex);
420 if (mm)
421 mmput(mm);
422 return ret;
423}
424EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
425
426int intel_svm_unbind_mm(struct device *dev, int pasid)
427{
428 struct intel_svm_dev *sdev;
429 struct intel_iommu *iommu;
430 struct intel_svm *svm;
431 int ret = -EINVAL;
432
433 mutex_lock(&pasid_mutex);
434 iommu = intel_svm_device_to_iommu(dev);
435 if (!iommu || !iommu->pasid_table)
436 goto out;
437
438 svm = idr_find(&iommu->pasid_idr, pasid);
439 if (!svm)
440 goto out;
441
442 list_for_each_entry(sdev, &svm->devs, list) {
443 if (dev == sdev->dev) {
444 ret = 0;
445 sdev->users--;
446 if (!sdev->users) {
447 list_del_rcu(&sdev->list);
448
449
450
451
452
453
454
455 intel_flush_pasid_dev(svm, sdev, svm->pasid);
456 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
457 kfree_rcu(sdev, rcu);
458
459 if (list_empty(&svm->devs)) {
460
461 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
462 if (svm->mm)
463 mmu_notifier_unregister(&svm->notifier, svm->mm);
464
465
466
467
468
469 memset(svm, 0x6b, sizeof(*svm));
470 kfree(svm);
471 }
472 }
473 break;
474 }
475 }
476 out:
477 mutex_unlock(&pasid_mutex);
478
479 return ret;
480}
481EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
482
483int intel_svm_is_pasid_valid(struct device *dev, int pasid)
484{
485 struct intel_iommu *iommu;
486 struct intel_svm *svm;
487 int ret = -EINVAL;
488
489 mutex_lock(&pasid_mutex);
490 iommu = intel_svm_device_to_iommu(dev);
491 if (!iommu || !iommu->pasid_table)
492 goto out;
493
494 svm = idr_find(&iommu->pasid_idr, pasid);
495 if (!svm)
496 goto out;
497
498
499 if (!svm->mm)
500 ret = 1;
501 else if (atomic_read(&svm->mm->mm_users) > 0)
502 ret = 1;
503 else
504 ret = 0;
505
506 out:
507 mutex_unlock(&pasid_mutex);
508
509 return ret;
510}
511EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
512
513
514struct page_req_dsc {
515 u64 srr:1;
516 u64 bof:1;
517 u64 pasid_present:1;
518 u64 lpig:1;
519 u64 pasid:20;
520 u64 bus:8;
521 u64 private:23;
522 u64 prg_index:9;
523 u64 rd_req:1;
524 u64 wr_req:1;
525 u64 exe_req:1;
526 u64 priv_req:1;
527 u64 devfn:8;
528 u64 addr:52;
529};
530
531#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
532
533static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
534{
535 unsigned long requested = 0;
536
537 if (req->exe_req)
538 requested |= VM_EXEC;
539
540 if (req->rd_req)
541 requested |= VM_READ;
542
543 if (req->wr_req)
544 requested |= VM_WRITE;
545
546 return (requested & ~vma->vm_flags) != 0;
547}
548
549static irqreturn_t prq_event_thread(int irq, void *d)
550{
551 struct intel_iommu *iommu = d;
552 struct intel_svm *svm = NULL;
553 int head, tail, handled = 0;
554
555
556
557 writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
558
559 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
560 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
561 while (head != tail) {
562 struct intel_svm_dev *sdev;
563 struct vm_area_struct *vma;
564 struct page_req_dsc *req;
565 struct qi_desc resp;
566 int ret, result;
567 u64 address;
568
569 handled = 1;
570
571 req = &iommu->prq[head / sizeof(*req)];
572
573 result = QI_RESP_FAILURE;
574 address = (u64)req->addr << VTD_PAGE_SHIFT;
575 if (!req->pasid_present) {
576 pr_err("%s: Page request without PASID: %08llx %08llx\n",
577 iommu->name, ((unsigned long long *)req)[0],
578 ((unsigned long long *)req)[1]);
579 goto bad_req;
580 }
581
582 if (!svm || svm->pasid != req->pasid) {
583 rcu_read_lock();
584 svm = idr_find(&iommu->pasid_idr, req->pasid);
585
586
587
588 rcu_read_unlock();
589
590 if (!svm) {
591 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
592 iommu->name, req->pasid, ((unsigned long long *)req)[0],
593 ((unsigned long long *)req)[1]);
594 goto no_pasid;
595 }
596 }
597
598 result = QI_RESP_INVALID;
599
600
601 if (!svm->mm)
602 goto bad_req;
603
604 if (!mmget_not_zero(svm->mm))
605 goto bad_req;
606 down_read(&svm->mm->mmap_sem);
607 vma = find_extend_vma(svm->mm, address);
608 if (!vma || address < vma->vm_start)
609 goto invalid;
610
611 if (access_error(vma, req))
612 goto invalid;
613
614 ret = handle_mm_fault(vma, address,
615 req->wr_req ? FAULT_FLAG_WRITE : 0);
616 if (ret & VM_FAULT_ERROR)
617 goto invalid;
618
619 result = QI_RESP_SUCCESS;
620 invalid:
621 up_read(&svm->mm->mmap_sem);
622 mmput(svm->mm);
623 bad_req:
624
625 rcu_read_lock();
626 list_for_each_entry_rcu(sdev, &svm->devs, list) {
627 if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
628 break;
629 }
630
631
632
633 rcu_read_unlock();
634
635 if (WARN_ON(&sdev->list == &svm->devs))
636 sdev = NULL;
637
638 if (sdev && sdev->ops && sdev->ops->fault_cb) {
639 int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
640 (req->exe_req << 1) | (req->priv_req);
641 sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
642 }
643
644
645 sdev = NULL;
646 svm = NULL;
647 no_pasid:
648 if (req->lpig) {
649
650 resp.low = QI_PGRP_PASID(req->pasid) |
651 QI_PGRP_DID((req->bus << 8) | req->devfn) |
652 QI_PGRP_PASID_P(req->pasid_present) |
653 QI_PGRP_RESP_TYPE;
654 resp.high = QI_PGRP_IDX(req->prg_index) |
655 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
656
657 qi_submit_sync(&resp, iommu);
658 } else if (req->srr) {
659
660 resp.low = QI_PSTRM_IDX(req->prg_index) |
661 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
662 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
663 resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
664 QI_PSTRM_RESP_CODE(result);
665
666 qi_submit_sync(&resp, iommu);
667 }
668
669 head = (head + sizeof(*req)) & PRQ_RING_MASK;
670 }
671
672 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
673
674 return IRQ_RETVAL(handled);
675}
676