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55
56#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
57
58#include <linux/module.h>
59#include <linux/init.h>
60#include <linux/string.h>
61#include <linux/slab.h>
62#include <asm/div64.h>
63
64#include "dvb_frontend.h"
65#include "drx39xxj.h"
66
67#include "drxj.h"
68#include "drxj_map.h"
69
70
71
72
73
74#define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
75
76
77
78
79#ifndef MAX_U32
80#define MAX_U32 ((u32) (0xFFFFFFFFL))
81#endif
82
83
84#ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
85#define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
86#endif
87
88#ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
89#define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
90#endif
91
92#ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
93#define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
94#endif
95
96#ifndef OOB_CRX_DRIVE_STRENGTH
97#define OOB_CRX_DRIVE_STRENGTH 0x02
98#endif
99
100#ifndef OOB_DRX_DRIVE_STRENGTH
101#define OOB_DRX_DRIVE_STRENGTH 0x02
102#endif
103
104
105#define ATV_TOP_CR_AMP_TH_FM 0x0
106#define ATV_TOP_CR_AMP_TH_L 0xA
107#define ATV_TOP_CR_AMP_TH_LP 0xA
108#define ATV_TOP_CR_AMP_TH_BG 0x8
109#define ATV_TOP_CR_AMP_TH_DK 0x8
110#define ATV_TOP_CR_AMP_TH_I 0x8
111#define ATV_TOP_CR_CONT_CR_D_MN 0x18
112#define ATV_TOP_CR_CONT_CR_D_FM 0x0
113#define ATV_TOP_CR_CONT_CR_D_L 0x20
114#define ATV_TOP_CR_CONT_CR_D_LP 0x20
115#define ATV_TOP_CR_CONT_CR_D_BG 0x18
116#define ATV_TOP_CR_CONT_CR_D_DK 0x18
117#define ATV_TOP_CR_CONT_CR_D_I 0x18
118#define ATV_TOP_CR_CONT_CR_I_MN 0x80
119#define ATV_TOP_CR_CONT_CR_I_FM 0x0
120#define ATV_TOP_CR_CONT_CR_I_L 0x80
121#define ATV_TOP_CR_CONT_CR_I_LP 0x80
122#define ATV_TOP_CR_CONT_CR_I_BG 0x80
123#define ATV_TOP_CR_CONT_CR_I_DK 0x80
124#define ATV_TOP_CR_CONT_CR_I_I 0x80
125#define ATV_TOP_CR_CONT_CR_P_MN 0x4
126#define ATV_TOP_CR_CONT_CR_P_FM 0x0
127#define ATV_TOP_CR_CONT_CR_P_L 0x4
128#define ATV_TOP_CR_CONT_CR_P_LP 0x4
129#define ATV_TOP_CR_CONT_CR_P_BG 0x4
130#define ATV_TOP_CR_CONT_CR_P_DK 0x4
131#define ATV_TOP_CR_CONT_CR_P_I 0x4
132#define ATV_TOP_CR_OVM_TH_MN 0xA0
133#define ATV_TOP_CR_OVM_TH_FM 0x0
134#define ATV_TOP_CR_OVM_TH_L 0xA0
135#define ATV_TOP_CR_OVM_TH_LP 0xA0
136#define ATV_TOP_CR_OVM_TH_BG 0xA0
137#define ATV_TOP_CR_OVM_TH_DK 0xA0
138#define ATV_TOP_CR_OVM_TH_I 0xA0
139#define ATV_TOP_EQU0_EQU_C0_FM 0x0
140#define ATV_TOP_EQU0_EQU_C0_L 0x3
141#define ATV_TOP_EQU0_EQU_C0_LP 0x3
142#define ATV_TOP_EQU0_EQU_C0_BG 0x7
143#define ATV_TOP_EQU0_EQU_C0_DK 0x0
144#define ATV_TOP_EQU0_EQU_C0_I 0x3
145#define ATV_TOP_EQU1_EQU_C1_FM 0x0
146#define ATV_TOP_EQU1_EQU_C1_L 0x1F6
147#define ATV_TOP_EQU1_EQU_C1_LP 0x1F6
148#define ATV_TOP_EQU1_EQU_C1_BG 0x197
149#define ATV_TOP_EQU1_EQU_C1_DK 0x198
150#define ATV_TOP_EQU1_EQU_C1_I 0x1F6
151#define ATV_TOP_EQU2_EQU_C2_FM 0x0
152#define ATV_TOP_EQU2_EQU_C2_L 0x28
153#define ATV_TOP_EQU2_EQU_C2_LP 0x28
154#define ATV_TOP_EQU2_EQU_C2_BG 0xC5
155#define ATV_TOP_EQU2_EQU_C2_DK 0xB0
156#define ATV_TOP_EQU2_EQU_C2_I 0x28
157#define ATV_TOP_EQU3_EQU_C3_FM 0x0
158#define ATV_TOP_EQU3_EQU_C3_L 0x192
159#define ATV_TOP_EQU3_EQU_C3_LP 0x192
160#define ATV_TOP_EQU3_EQU_C3_BG 0x12E
161#define ATV_TOP_EQU3_EQU_C3_DK 0x18E
162#define ATV_TOP_EQU3_EQU_C3_I 0x192
163#define ATV_TOP_STD_MODE_MN 0x0
164#define ATV_TOP_STD_MODE_FM 0x1
165#define ATV_TOP_STD_MODE_L 0x0
166#define ATV_TOP_STD_MODE_LP 0x0
167#define ATV_TOP_STD_MODE_BG 0x0
168#define ATV_TOP_STD_MODE_DK 0x0
169#define ATV_TOP_STD_MODE_I 0x0
170#define ATV_TOP_STD_VID_POL_MN 0x0
171#define ATV_TOP_STD_VID_POL_FM 0x0
172#define ATV_TOP_STD_VID_POL_L 0x2
173#define ATV_TOP_STD_VID_POL_LP 0x2
174#define ATV_TOP_STD_VID_POL_BG 0x0
175#define ATV_TOP_STD_VID_POL_DK 0x0
176#define ATV_TOP_STD_VID_POL_I 0x0
177#define ATV_TOP_VID_AMP_MN 0x380
178#define ATV_TOP_VID_AMP_FM 0x0
179#define ATV_TOP_VID_AMP_L 0xF50
180#define ATV_TOP_VID_AMP_LP 0xF50
181#define ATV_TOP_VID_AMP_BG 0x380
182#define ATV_TOP_VID_AMP_DK 0x394
183#define ATV_TOP_VID_AMP_I 0x3D8
184#define IQM_CF_OUT_ENA_OFDM__M 0x4
185#define IQM_FS_ADJ_SEL_B_QAM 0x1
186#define IQM_FS_ADJ_SEL_B_OFF 0x0
187#define IQM_FS_ADJ_SEL_B_VSB 0x2
188#define IQM_RC_ADJ_SEL_B_OFF 0x0
189#define IQM_RC_ADJ_SEL_B_QAM 0x1
190#define IQM_RC_ADJ_SEL_B_VSB 0x2
191
192
193#include "drx_driver_version.h"
194
195
196#ifdef DRX_DEBUG
197#include <stdio.h>
198#endif
199
200
201
202
203
204
205
206
207#ifndef DRXJ_WAKE_UP_KEY
208#define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
209#endif
210
211
212
213
214
215#define DRXJ_DEF_I2C_ADDR (0x52)
216
217
218
219
220
221#define DRXJ_DEF_DEMOD_DEV_ID (1)
222
223
224
225
226
227#define DRXJ_SCAN_TIMEOUT 1000
228
229
230
231
232
233
234
235#define HI_I2C_DELAY 42
236
237
238
239
240
241
242
243#define HI_I2C_BRIDGE_DELAY 750
244
245
246
247
248#define VSB_TOP_MEASUREMENT_PERIOD 64
249#define SYMBOLS_PER_SEGMENT 832
250
251
252
253
254
255#define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
256#define DRXJ_QAM_SL_SIG_POWER_QPSK 32768
257#define DRXJ_QAM_SL_SIG_POWER_QAM8 24576
258#define DRXJ_QAM_SL_SIG_POWER_QAM16 40960
259#define DRXJ_QAM_SL_SIG_POWER_QAM32 20480
260#define DRXJ_QAM_SL_SIG_POWER_QAM64 43008
261#define DRXJ_QAM_SL_SIG_POWER_QAM128 20992
262#define DRXJ_QAM_SL_SIG_POWER_QAM256 43520
263
264
265
266#ifndef DRXJ_QAM_SYMBOLRATE_MIN
267#define DRXJ_QAM_SYMBOLRATE_MIN (520000)
268#endif
269
270
271
272
273#ifndef DRXJ_QAM_SYMBOLRATE_MAX
274#define DRXJ_QAM_SYMBOLRATE_MAX (7233000)
275#endif
276
277
278
279
280
281#ifndef DRXJ_QAM_MAX_WAITTIME
282#define DRXJ_QAM_MAX_WAITTIME 900
283#endif
284
285#ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
286#define DRXJ_QAM_FEC_LOCK_WAITTIME 150
287#endif
288
289#ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
290#define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
291#endif
292
293
294
295
296
297#define DRX_SCU_READY 0
298#define DRXJ_MAX_WAITTIME 100
299#define FEC_RS_MEASUREMENT_PERIOD 12894
300#define FEC_RS_MEASUREMENT_PRESCALE 1
301
302
303
304
305
306#ifndef DRXJ_AUD_MAX_FM_DEVIATION
307#define DRXJ_AUD_MAX_FM_DEVIATION 100
308#endif
309
310
311
312
313#ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
314#define DRXJ_AUD_MAX_NICAM_PRESCALE (9)
315#endif
316
317
318
319
320#ifndef DRXJ_AUD_MAX_WAITTIME
321#define DRXJ_AUD_MAX_WAITTIME 250
322#endif
323
324
325#define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
326#define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
327#define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
328#define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
329#define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
330
331
332#define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
333#define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
334
335
336
337
338
339
340#define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L'))
341
342
343#define DRX_UCODE_CRC_FLAG (0x0001)
344
345
346
347
348
349#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
350
351#if DRX_UCODE_MAX_BUF_SIZE & 1
352#error DRX_UCODE_MAX_BUF_SIZE must be an even number
353#endif
354
355
356
357
358
359#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
360 (mode == DRX_POWER_MODE_10) || \
361 (mode == DRX_POWER_MODE_11) || \
362 (mode == DRX_POWER_MODE_12) || \
363 (mode == DRX_POWER_MODE_13) || \
364 (mode == DRX_POWER_MODE_14) || \
365 (mode == DRX_POWER_MODE_15) || \
366 (mode == DRX_POWER_MODE_16) || \
367 (mode == DRX_POWER_DOWN))
368
369
370#define DRXJ_PIN_SAFE_MODE 0x0000
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391#define AUD_DEM_RAM_MODUS_HI__A 0x10204A3
392#define AUD_DEM_RAM_MODUS_HI__M 0xF000
393
394#define AUD_DEM_RAM_MODUS_LO__A 0x10204A4
395#define AUD_DEM_RAM_MODUS_LO__M 0x0FFF
396
397
398
399
400#define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1
401#define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2
402
403
404
405
406#define AUD_DEM_RAM_DCO_B_HI__A 0x1020461
407#define AUD_DEM_RAM_DCO_B_LO__A 0x1020462
408#define AUD_DEM_RAM_DCO_A_HI__A 0x1020463
409#define AUD_DEM_RAM_DCO_A_LO__A 0x1020464
410
411
412
413
414#define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A
415#define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB
416#define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6
417
418
419
420
421#define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF
422#define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0
423
424
425
426
427#ifdef AUD_DEM_WR_FM_MATRIX__A
428#undef AUD_DEM_WR_FM_MATRIX__A
429#endif
430#define AUD_DEM_WR_FM_MATRIX__A 0x105006F
431
432
433
434
435
436#define AUD_VOLUME_ZERO_DB 115
437#define AUD_VOLUME_DB_MIN -60
438#define AUD_VOLUME_DB_MAX 12
439#define AUD_CARRIER_STRENGTH_QP_0DB 0x4000
440#define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421
441#define AUD_MAX_AVC_REF_LEVEL 15
442#define AUD_I2S_FREQUENCY_MAX 48000UL
443#define AUD_I2S_FREQUENCY_MIN 12000UL
444#define AUD_RDS_ARRAY_SIZE 18
445
446
447
448
449#ifndef DRX_AUD_MAX_FM_DEVIATION
450#define DRX_AUD_MAX_FM_DEVIATION (100)
451#endif
452
453
454
455
456#ifndef DRX_AUD_MAX_NICAM_PRESCALE
457#define DRX_AUD_MAX_NICAM_PRESCALE (9)
458#endif
459
460
461
462#define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004
463#define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008
464#define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004
465#define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000
466
467#define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003
468#define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008
469#define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003
470#define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008
471
472#define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004
473#define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008
474#define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004
475#define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000
476
477
478
479
480
481
482
483
484
485
486
487#define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
488 ((u8)((((u16)x)>>8)&0xFF))
489
490
491
492
493
494#define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
495
496
497
498
499
500
501
502
503
504
505
506
507#define DRXJ_MAX_RETRIES (100)
508
509
510
511
512
513#define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
514 (std == DRX_STANDARD_PAL_SECAM_DK) || \
515 (std == DRX_STANDARD_PAL_SECAM_I) || \
516 (std == DRX_STANDARD_PAL_SECAM_L) || \
517 (std == DRX_STANDARD_PAL_SECAM_LP) || \
518 (std == DRX_STANDARD_NTSC) || \
519 (std == DRX_STANDARD_FM))
520
521#define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
522 (std == DRX_STANDARD_ITU_B) || \
523 (std == DRX_STANDARD_ITU_C) || \
524 (std == DRX_STANDARD_ITU_D))
525
526
527
528
529
530
531
532
533static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
534 u32 addr,
535 u16 datasize,
536 u8 *data, u32 flags);
537
538
539static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
540 u32 waddr,
541 u32 raddr,
542 u16 wdata, u16 *rdata);
543
544static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
545 u32 addr,
546 u16 *data, u32 flags);
547
548static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
549 u32 addr,
550 u32 *data, u32 flags);
551
552static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
553 u32 addr,
554 u16 datasize,
555 u8 *data, u32 flags);
556
557static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
558 u32 addr,
559 u16 data, u32 flags);
560
561static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
562 u32 addr,
563 u32 data, u32 flags);
564
565static struct drxj_data drxj_data_g = {
566 false,
567 false,
568 false,
569 false,
570 false,
571 false,
572 false,
573 false,
574 0,
575
576
577 false,
578
579 DRX_STANDARD_UNKNOWN,
580 DRX_CONSTELLATION_AUTO,
581 0,
582 DRX_BANDWIDTH_UNKNOWN,
583 DRX_MIRROR_NO,
584
585
586
587
588 4000000,
589 5,
590 4,
591 0xFFFF,
592 204 * 8,
593 1,
594 FEC_RS_MEASUREMENT_PERIOD,
595 true,
596 0,
597
598
599 0,
600 0,
601 0,
602 0,
603 0,
604
605 DRX_UIO_MODE_DISABLE,
606 DRX_UIO_MODE_DISABLE,
607 DRX_UIO_MODE_DISABLE,
608 DRX_UIO_MODE_DISABLE,
609
610 0UL,
611 false,
612
613 0UL,
614
615
616
617
618
619
620
621
622
623 0UL,
624
625 {-5,
626 ATV_TOP_EQU0_EQU_C0_FM,
627 ATV_TOP_EQU0_EQU_C0_L,
628 ATV_TOP_EQU0_EQU_C0_LP,
629 ATV_TOP_EQU0_EQU_C0_BG,
630 ATV_TOP_EQU0_EQU_C0_DK,
631 ATV_TOP_EQU0_EQU_C0_I},
632
633 {-50,
634 ATV_TOP_EQU1_EQU_C1_FM,
635 ATV_TOP_EQU1_EQU_C1_L,
636 ATV_TOP_EQU1_EQU_C1_LP,
637 ATV_TOP_EQU1_EQU_C1_BG,
638 ATV_TOP_EQU1_EQU_C1_DK,
639 ATV_TOP_EQU1_EQU_C1_I},
640
641 {210,
642 ATV_TOP_EQU2_EQU_C2_FM,
643 ATV_TOP_EQU2_EQU_C2_L,
644 ATV_TOP_EQU2_EQU_C2_LP,
645 ATV_TOP_EQU2_EQU_C2_BG,
646 ATV_TOP_EQU2_EQU_C2_DK,
647 ATV_TOP_EQU2_EQU_C2_I},
648
649 {-160,
650 ATV_TOP_EQU3_EQU_C3_FM,
651 ATV_TOP_EQU3_EQU_C3_L,
652 ATV_TOP_EQU3_EQU_C3_LP,
653 ATV_TOP_EQU3_EQU_C3_BG,
654 ATV_TOP_EQU3_EQU_C3_DK,
655 ATV_TOP_EQU3_EQU_C3_I},
656 false,
657 ATV_TOP_VID_PEAK__PRE,
658 ATV_TOP_NOISE_TH__PRE,
659 true,
660 false,
661 DRXJ_SIF_ATTENUATION_0DB,
662 {
663 DRX_STANDARD_ITU_B,
664 DRX_AGC_CTRL_AUTO,
665 0,
666 0,
667 0xFFFF,
668 0x0000,
669 0x0000,
670 0x0000
671 },
672 {
673 DRX_STANDARD_ITU_B,
674 DRX_AGC_CTRL_AUTO,
675 0,
676 0,
677 0xFFFF,
678 0x0000,
679 0x0000,
680 0x0000
681 },
682 {
683 DRX_STANDARD_8VSB,
684 DRX_AGC_CTRL_AUTO,
685 0,
686 0,
687 0xFFFF,
688 0x0000,
689 0x0000,
690 0x0000
691 },
692 {
693 DRX_STANDARD_8VSB,
694 DRX_AGC_CTRL_AUTO,
695 0,
696 0,
697 0xFFFF,
698 0x0000,
699 0x0000,
700 0x0000
701 },
702 0,
703 0,
704 {
705 DRX_STANDARD_ITU_B,
706 0,
707 false
708 },
709 {
710 DRX_STANDARD_8VSB,
711 0,
712 false
713 },
714
715
716#ifndef _CH_
717 {
718 "01234567890",
719 "01234567890"
720 },
721 {
722 {
723 DRX_MODULE_UNKNOWN,
724 (char *)(NULL),
725 0,
726 0,
727 0,
728 (char *)(NULL)
729 },
730 {
731 DRX_MODULE_UNKNOWN,
732 (char *)(NULL),
733 0,
734 0,
735 0,
736 (char *)(NULL)
737 }
738 },
739 {
740 {
741 (struct drx_version *) (NULL),
742 (struct drx_version_list *) (NULL)
743 },
744 {
745 (struct drx_version *) (NULL),
746 (struct drx_version_list *) (NULL)
747 }
748 },
749#endif
750 false,
751
752 {
753 12000,
754 9300,
755 6600,
756 5280,
757 3700,
758 3000,
759 2000,
760 0},
761 false,
762 0,
763 false,
764 false,
765 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
766 DRXJ_MPEG_START_WIDTH_1CLKCYC,
767
768
769 {
770 DRX_STANDARD_NTSC,
771 7,
772 true
773 },
774 {
775 DRX_STANDARD_NTSC,
776 DRX_AGC_CTRL_AUTO,
777 0,
778 0,
779 0,
780 3,
781 9500,
782 4000
783 },
784 {
785 DRX_STANDARD_NTSC,
786 DRX_AGC_CTRL_AUTO,
787 0,
788 0,
789 0,
790 3,
791 2400,
792 0
793 },
794 140,
795 0,
796
797 false,
798 SIO_PDR_GPIO_CFG__PRE,
799 SIO_PDR_VSYNC_CFG__PRE,
800 SIO_PDR_SMA_RX_CFG__PRE,
801 SIO_PDR_SMA_TX_CFG__PRE,
802
803 4,
804 DRXJ_OOB_LO_POW_MINUS10DB,
805 {
806 false
807 },
808};
809
810
811
812
813
814static struct i2c_device_addr drxj_default_addr_g = {
815 DRXJ_DEF_I2C_ADDR,
816 DRXJ_DEF_DEMOD_DEV_ID
817};
818
819
820
821
822
823static struct drx_common_attr drxj_default_comm_attr_g = {
824 NULL,
825 true,
826 {0},
827
828 44000,
829 (151875 - 0),
830 0,
831 0,
832 false,
833 {
834
835 true,
836 false,
837 false,
838 false,
839 false,
840 false,
841 false,
842 false,
843 true,
844
845
846 19392658UL,
847
848 DRX_MPEG_STR_WIDTH_1
849 },
850
851
852
853 false,
854
855
856 NULL,
857 0,
858 0,
859 false,
860 0,
861 0,
862 NULL,
863 NULL,
864 0,
865 DRXJ_DEMOD_LOCK,
866 false,
867
868
869 DRX_POWER_UP,
870
871
872 1,
873 0L,
874 0L,
875 false,
876 false,
877 false,
878
879 {
880 0UL
881 },
882 DRX_STANDARD_UNKNOWN,
883 DRX_STANDARD_UNKNOWN,
884 DRX_STANDARD_UNKNOWN,
885 false,
886 0UL,
887 0
888};
889
890
891
892
893
894static struct drx_demod_instance drxj_default_demod_g = {
895 &drxj_default_addr_g,
896 &drxj_default_comm_attr_g,
897 &drxj_data_g
898};
899
900
901
902
903
904
905
906static struct drx_aud_data drxj_default_aud_data_g = {
907 false,
908 DRX_AUD_STANDARD_AUTO,
909
910
911 {
912 false,
913 48000,
914 DRX_I2S_MODE_MASTER,
915 DRX_I2S_WORDLENGTH_32,
916 DRX_I2S_POLARITY_RIGHT,
917 DRX_I2S_FORMAT_WS_WITH_DATA
918 },
919
920 {
921 true,
922 0,
923 DRX_AUD_AVC_OFF,
924 0,
925 DRX_AUD_AVC_MAX_GAIN_12DB,
926 DRX_AUD_AVC_MAX_ATTEN_24DB,
927 0,
928 0
929 },
930 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
931
932 {
933 440,
934 12,
935 700,
936 },
937
938 {
939
940 {
941 42,
942 DRX_NO_CARRIER_NOISE,
943 0,
944 0
945 },
946
947 {
948 42,
949 DRX_NO_CARRIER_MUTE,
950 0,
951 0
952 },
953
954 },
955
956 {
957 DRX_AUD_SRC_STEREO_OR_A,
958 DRX_AUD_I2S_MATRIX_STEREO,
959 DRX_AUD_FM_MATRIX_SOUND_A
960 },
961 DRX_AUD_DEVIATION_NORMAL,
962 DRX_AUD_AVSYNC_OFF,
963
964
965 {
966 DRX_AUD_MAX_FM_DEVIATION,
967 DRX_AUD_MAX_NICAM_PRESCALE
968 },
969 DRX_AUD_FM_DEEMPH_75US,
970 DRX_BTSC_STEREO,
971 0,
972 false
973};
974
975
976
977
978struct drxjeq_stat {
979 u16 eq_mse;
980 u8 eq_mode;
981 u8 eq_ctrl;
982 u8 eq_stat;
983};
984
985
986struct drxj_hi_cmd {
987 u16 cmd;
988 u16 param1;
989 u16 param2;
990 u16 param3;
991 u16 param4;
992 u16 param5;
993 u16 param6;
994};
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009struct drxu_code_block_hdr {
1010 u32 addr;
1011 u16 size;
1012 u16 flags;
1013 u16 CRC;
1014};
1015
1016
1017
1018
1019
1020static int
1021hi_command(struct i2c_device_addr *dev_addr,
1022 const struct drxj_hi_cmd *cmd, u16 *result);
1023
1024static int
1025ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
1026
1027static int
1028ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
1029
1030static int power_down_aud(struct drx_demod_instance *demod);
1031
1032static int
1033ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
1034
1035static int
1036ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067static u32 frac28(u32 N, u32 D)
1068{
1069 int i = 0;
1070 u32 Q1 = 0;
1071 u32 R0 = 0;
1072
1073 R0 = (N % D) << 4;
1074 Q1 = N / D;
1075
1076
1077
1078 for (i = 0; i < 7; i++) {
1079 Q1 = (Q1 << 4) | R0 / D;
1080 R0 = (R0 % D) << 4;
1081 }
1082
1083 if ((R0 >> 3) >= D)
1084 Q1++;
1085
1086 return Q1;
1087}
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105static u32 log1_times100(u32 x)
1106{
1107 static const u8 scale = 15;
1108 static const u8 index_width = 5;
1109
1110
1111
1112
1113
1114 static const u32 log2lut[] = {
1115 0,
1116 290941,
1117 573196,
1118 847269,
1119 1113620,
1120 1372674,
1121 1624818,
1122 1870412,
1123 2109788,
1124 2343253,
1125 2571091,
1126 2793569,
1127 3010931,
1128 3223408,
1129 3431216,
1130 3634553,
1131 3833610,
1132 4028562,
1133 4219576,
1134 4406807,
1135 4590402,
1136 4770499,
1137 4947231,
1138 5120719,
1139 5291081,
1140 5458428,
1141 5622864,
1142 5784489,
1143 5943398,
1144 6099680,
1145 6253421,
1146 6404702,
1147 6553600,
1148 };
1149
1150 u8 i = 0;
1151 u32 y = 0;
1152 u32 d = 0;
1153 u32 k = 0;
1154 u32 r = 0;
1155
1156 if (x == 0)
1157 return 0;
1158
1159
1160
1161 if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
1162 for (k = scale; k > 0; k--) {
1163 if (x & (((u32) 1) << scale))
1164 break;
1165 x <<= 1;
1166 }
1167 } else {
1168 for (k = scale; k < 31; k++) {
1169 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
1170 break;
1171 x >>= 1;
1172 }
1173 }
1174
1175
1176
1177
1178
1179 y = k * ((((u32) 1) << scale) * 200);
1180
1181
1182 x &= ((((u32) 1) << scale) - 1);
1183
1184 i = (u8) (x >> (scale - index_width));
1185
1186 d = x & ((((u32) 1) << (scale - index_width)) - 1);
1187
1188 y += log2lut[i] +
1189 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
1190
1191 y /= 108853;
1192 r = (y >> 1);
1193
1194 if (y & ((u32)1))
1195 r++;
1196
1197 return r;
1198
1199}
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211static u32 frac_times1e6(u32 N, u32 D)
1212{
1213 u32 remainder = 0;
1214 u32 frac = 0;
1215
1216
1217
1218
1219
1220
1221
1222
1223 frac = (((u32) N) * (1000000 >> 4)) / D;
1224 frac <<= 4;
1225 remainder = (((u32) N) * (1000000 >> 4)) % D;
1226 remainder <<= 4;
1227 frac += remainder / D;
1228 remainder = remainder % D;
1229 if ((remainder * 2) > D)
1230 frac++;
1231
1232 return frac;
1233}
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243#if 0
1244
1245static const u16 nicam_presc_table_val[43] = {
1246 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
1247 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
1248 18, 20, 23, 25, 28, 32, 36, 40, 45,
1249 51, 57, 64, 71, 80, 90, 101, 113, 127
1250};
1251#endif
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1280#define DRXJ_DAP_AUDTRIF_TIMEOUT 80
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292static
1293bool is_handled_by_aud_tr_if(u32 addr)
1294{
1295 bool retval = false;
1296
1297 if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
1298 (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
1299 (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
1300 retval = true;
1301 }
1302
1303 return retval;
1304}
1305
1306
1307
1308int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
1309 u16 w_count,
1310 u8 *wData,
1311 struct i2c_device_addr *r_dev_addr,
1312 u16 r_count, u8 *r_data)
1313{
1314 struct drx39xxj_state *state;
1315 struct i2c_msg msg[2];
1316 unsigned int num_msgs;
1317
1318 if (w_dev_addr == NULL) {
1319
1320 state = r_dev_addr->user_data;
1321 msg[0].addr = r_dev_addr->i2c_addr >> 1;
1322 msg[0].flags = I2C_M_RD;
1323 msg[0].buf = r_data;
1324 msg[0].len = r_count;
1325 num_msgs = 1;
1326 } else if (r_dev_addr == NULL) {
1327
1328 state = w_dev_addr->user_data;
1329 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1330 msg[0].flags = 0;
1331 msg[0].buf = wData;
1332 msg[0].len = w_count;
1333 num_msgs = 1;
1334 } else {
1335
1336 state = w_dev_addr->user_data;
1337 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1338 msg[0].flags = 0;
1339 msg[0].buf = wData;
1340 msg[0].len = w_count;
1341 msg[1].addr = r_dev_addr->i2c_addr >> 1;
1342 msg[1].flags = I2C_M_RD;
1343 msg[1].buf = r_data;
1344 msg[1].len = r_count;
1345 num_msgs = 2;
1346 }
1347
1348 if (state->i2c == NULL) {
1349 pr_err("i2c was zero, aborting\n");
1350 return 0;
1351 }
1352 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
1353 pr_warn("drx3933: I2C write/read failed\n");
1354 return -EREMOTEIO;
1355 }
1356
1357#ifdef DJH_DEBUG
1358 if (w_dev_addr == NULL || r_dev_addr == NULL)
1359 return 0;
1360
1361 state = w_dev_addr->user_data;
1362
1363 if (state->i2c == NULL)
1364 return 0;
1365
1366 msg[0].addr = w_dev_addr->i2c_addr;
1367 msg[0].flags = 0;
1368 msg[0].buf = wData;
1369 msg[0].len = w_count;
1370 msg[1].addr = r_dev_addr->i2c_addr;
1371 msg[1].flags = I2C_M_RD;
1372 msg[1].buf = r_data;
1373 msg[1].len = r_count;
1374 num_msgs = 2;
1375
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1377 w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
1378
1379 if (i2c_transfer(state->i2c, msg, 2) != 2) {
1380 pr_warn("drx3933: I2C write/read failed\n");
1381 return -EREMOTEIO;
1382 }
1383#endif
1384 return 0;
1385}
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
1415 u32 addr,
1416 u16 datasize,
1417 u8 *data, u32 flags)
1418{
1419 u8 buf[4];
1420 u16 bufx;
1421 int rc;
1422 u16 overhead_size = 0;
1423
1424
1425 if (dev_addr == NULL)
1426 return -EINVAL;
1427
1428 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1429 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1430
1431 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1432 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1433 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1434 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1435 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
1436 return -EINVAL;
1437 }
1438
1439
1440 flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
1441#if DRXDAP_SINGLE_MASTER
1442 flags |= DRXDAP_FASI_SINGLE_MASTER;
1443#endif
1444
1445
1446 do {
1447 u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
1448 datasize : DRXDAP_MAX_RCHUNKSIZE);
1449
1450 bufx = 0;
1451
1452 addr &= ~DRXDAP_FASI_FLAGS;
1453 addr |= flags;
1454
1455#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1456
1457 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1458#endif
1459#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1460 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1461 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1462 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1463 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1464#endif
1465#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1466 } else {
1467#endif
1468#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
1469 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1470 buf[bufx++] =
1471 (u8) (((addr >> 16) & 0x0F) |
1472 ((addr >> 18) & 0xF0));
1473#endif
1474#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1475 }
1476#endif
1477
1478#if DRXDAP_SINGLE_MASTER
1479
1480
1481
1482
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1484 NULL, 0, NULL);
1485 if (rc == 0)
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1487#else
1488
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1490 data);
1491#endif
1492 data += todo;
1493 addr += (todo >> 1);
1494 datasize -= todo;
1495 } while (datasize && rc == 0);
1496
1497 return rc;
1498}
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
1520 u32 addr,
1521 u16 *data, u32 flags)
1522{
1523 u8 buf[sizeof(*data)];
1524 int rc;
1525
1526 if (!data)
1527 return -EINVAL;
1528
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1530 *data = buf[0] + (((u16) buf[1]) << 8);
1531 return rc;
1532}
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
1553 u32 addr,
1554 u32 *data, u32 flags)
1555{
1556 u8 buf[sizeof(*data)];
1557 int rc;
1558
1559 if (!data)
1560 return -EINVAL;
1561
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1563 *data = (((u32) buf[0]) << 0) +
1564 (((u32) buf[1]) << 8) +
1565 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1566 return rc;
1567}
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
1592 u32 addr,
1593 u16 datasize,
1594 u8 *data, u32 flags)
1595{
1596 u8 buf[DRXDAP_MAX_WCHUNKSIZE];
1597 int st = -EIO;
1598 int first_err = 0;
1599 u16 overhead_size = 0;
1600 u16 block_size = 0;
1601
1602
1603 if (dev_addr == NULL)
1604 return -EINVAL;
1605
1606 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1607 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1608
1609 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1610 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1611 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1612 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1613 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
1614 return -EINVAL;
1615
1616 flags &= DRXDAP_FASI_FLAGS;
1617 flags &= ~DRXDAP_FASI_MODEFLAGS;
1618#if DRXDAP_SINGLE_MASTER
1619 flags |= DRXDAP_FASI_SINGLE_MASTER;
1620#endif
1621
1622
1623 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
1624 do {
1625 u16 todo = 0;
1626 u16 bufx = 0;
1627
1628
1629 addr &= ~DRXDAP_FASI_FLAGS;
1630 addr |= flags;
1631#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1632
1633 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1634#endif
1635#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
1636 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1637 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1638 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1639 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1640#endif
1641#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1642 } else {
1643#endif
1644#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
1645 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1646 buf[bufx++] =
1647 (u8) (((addr >> 16) & 0x0F) |
1648 ((addr >> 18) & 0xF0));
1649#endif
1650#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1651 }
1652#endif
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662 todo = (block_size < datasize ? block_size : datasize);
1663 if (todo == 0) {
1664 u16 overhead_size_i2c_addr = 0;
1665 u16 data_block_size = 0;
1666
1667 overhead_size_i2c_addr =
1668 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
1669 data_block_size =
1670 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
1671
1672
1673 st = drxbsp_i2c_write_read(dev_addr,
1674 (u16) (bufx),
1675 buf,
1676 (struct i2c_device_addr *)(NULL),
1677 0, (u8 *)(NULL));
1678
1679 if ((st != 0) && (first_err == 0)) {
1680
1681 first_err = st;
1682 }
1683 bufx = 0;
1684 todo =
1685 (data_block_size <
1686 datasize ? data_block_size : datasize);
1687 }
1688 memcpy(&buf[bufx], data, todo);
1689
1690 st = drxbsp_i2c_write_read(dev_addr,
1691 (u16) (bufx + todo),
1692 buf,
1693 (struct i2c_device_addr *)(NULL),
1694 0, (u8 *)(NULL));
1695
1696 if ((st != 0) && (first_err == 0)) {
1697
1698 first_err = st;
1699 }
1700 datasize -= todo;
1701 data += todo;
1702 addr += (todo >> 1);
1703 } while (datasize);
1704
1705 return first_err;
1706}
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
1726 u32 addr,
1727 u16 data, u32 flags)
1728{
1729 u8 buf[sizeof(data)];
1730
1731 buf[0] = (u8) ((data >> 0) & 0xFF);
1732 buf[1] = (u8) ((data >> 8) & 0xFF);
1733
1734 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1735}
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1763 u32 waddr,
1764 u32 raddr,
1765 u16 wdata, u16 *rdata)
1766{
1767 int rc = -EIO;
1768
1769#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1770 if (rdata == NULL)
1771 return -EINVAL;
1772
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1774 if (rc == 0)
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1776#endif
1777
1778 return rc;
1779}
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
1799 u32 addr,
1800 u32 data, u32 flags)
1801{
1802 u8 buf[sizeof(data)];
1803
1804 buf[0] = (u8) ((data >> 0) & 0xFF);
1805 buf[1] = (u8) ((data >> 8) & 0xFF);
1806 buf[2] = (u8) ((data >> 16) & 0xFF);
1807 buf[3] = (u8) ((data >> 24) & 0xFF);
1808
1809 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1810}
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
1835static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
1836 u32 waddr,
1837 u32 raddr,
1838 u16 wdata, u16 *rdata)
1839{
1840 int rc;
1841
1842 if (rdata == NULL)
1843 return -EINVAL;
1844
1845
1846 rc = drxdap_fasi_write_reg16(dev_addr,
1847 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1848 SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
1849 0x0000);
1850 if (rc == 0) {
1851
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1853 0x0000);
1854 }
1855 if (rc == 0) {
1856
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1858 0x0000);
1859 }
1860 if (rc == 0) {
1861
1862 rc = drxdap_fasi_write_reg16(dev_addr,
1863 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1864 0, 0x0000);
1865 }
1866
1867 return rc;
1868}
1869#endif
1870
1871
1872
1873static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1874 u32 waddr,
1875 u32 raddr,
1876 u16 wdata, u16 *rdata)
1877{
1878
1879
1880
1881#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1882 return drxdap_fasi_read_modify_write_reg16(dev_addr,
1883 waddr,
1884 raddr, wdata, rdata);
1885#else
1886 return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
1887#endif
1888}
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
1907 u32 addr, u16 *data)
1908{
1909 u32 start_timer = 0;
1910 u32 current_timer = 0;
1911 u32 delta_timer = 0;
1912 u16 tr_status = 0;
1913 int stat = -EIO;
1914
1915
1916 if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
1917 stat = -EINVAL;
1918 } else {
1919 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
1920
1921
1922 addr &= (~write_bit);
1923
1924
1925 start_timer = jiffies_to_msecs(jiffies);
1926 do {
1927
1928 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1929 addr,
1930 SIO_HI_RA_RAM_S0_RMWBUF__A,
1931 0x0000, &tr_status);
1932
1933 if (stat != 0)
1934 break;
1935
1936 current_timer = jiffies_to_msecs(jiffies);
1937 delta_timer = current_timer - start_timer;
1938 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1939 stat = -EIO;
1940 break;
1941 }
1942
1943 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
1944 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1945 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
1946 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1947 }
1948
1949
1950 if (stat == 0) {
1951 start_timer = jiffies_to_msecs(jiffies);
1952
1953 while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
1954 AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
1955 stat = drxj_dap_read_reg16(dev_addr,
1956 AUD_TOP_TR_CTR__A,
1957 &tr_status, 0x0000);
1958 if (stat != 0)
1959 break;
1960
1961 current_timer = jiffies_to_msecs(jiffies);
1962 delta_timer = current_timer - start_timer;
1963 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1964 stat = -EIO;
1965 break;
1966 }
1967 }
1968 }
1969
1970
1971 if (stat == 0)
1972 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1973 AUD_TOP_TR_RD_REG__A,
1974 SIO_HI_RA_RAM_S0_RMWBUF__A,
1975 0x0000, data);
1976 return stat;
1977}
1978
1979
1980
1981static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
1982 u32 addr,
1983 u16 *data, u32 flags)
1984{
1985 int stat = -EIO;
1986
1987
1988 if ((dev_addr == NULL) || (data == NULL))
1989 return -EINVAL;
1990
1991 if (is_handled_by_aud_tr_if(addr))
1992 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1993 else
1994 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
1995
1996 return stat;
1997}
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
2014 u32 addr, u16 data)
2015{
2016 int stat = -EIO;
2017
2018
2019 if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
2020 stat = -EINVAL;
2021 } else {
2022 u32 start_timer = 0;
2023 u32 current_timer = 0;
2024 u32 delta_timer = 0;
2025 u16 tr_status = 0;
2026 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
2027
2028
2029 addr |= write_bit;
2030 start_timer = jiffies_to_msecs(jiffies);
2031 do {
2032
2033 stat = drxj_dap_read_modify_write_reg16(dev_addr,
2034 addr,
2035 SIO_HI_RA_RAM_S0_RMWBUF__A,
2036 data, &tr_status);
2037 if (stat != 0)
2038 break;
2039
2040 current_timer = jiffies_to_msecs(jiffies);
2041 delta_timer = current_timer - start_timer;
2042 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
2043 stat = -EIO;
2044 break;
2045 }
2046
2047 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
2048 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
2049 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
2050 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
2051
2052 }
2053
2054 return stat;
2055}
2056
2057
2058
2059static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
2060 u32 addr,
2061 u16 data, u32 flags)
2062{
2063 int stat = -EIO;
2064
2065
2066 if (dev_addr == NULL)
2067 return -EINVAL;
2068
2069 if (is_handled_by_aud_tr_if(addr))
2070 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2071 else
2072 stat = drxdap_fasi_write_reg16(dev_addr,
2073 addr, data, flags);
2074
2075 return stat;
2076}
2077
2078
2079
2080
2081#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2082#define SIO_HI_RA_RAM_USR_END__A 0x420060
2083
2084#define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2085#define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2086#define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2087#define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101static
2102int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
2103 u32 addr,
2104 u16 datasize,
2105 u8 *data, bool read_flag)
2106{
2107 struct drxj_hi_cmd hi_cmd;
2108 int rc;
2109 u16 word;
2110 u16 dummy = 0;
2111 u16 i = 0;
2112
2113
2114 if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
2115 return -EINVAL;
2116
2117
2118 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
2119 hi_cmd.param1 =
2120 (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
2121 DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
2122 hi_cmd.param2 =
2123 (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
2124 hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2125 if (!read_flag)
2126 hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
2127 else
2128 hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
2129 hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2130 DRXDAP_FASI_ADDR2BANK(addr));
2131 hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2132
2133 if (!read_flag) {
2134
2135 for (i = 0; i < (datasize / 2); i++) {
2136
2137 word = ((u16) data[2 * i]);
2138 word += (((u16) data[(2 * i) + 1]) << 8);
2139 drxj_dap_write_reg16(dev_addr,
2140 (DRXJ_HI_ATOMIC_BUF_START + i),
2141 word, 0);
2142 }
2143 }
2144
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy);
2146 if (rc != 0) {
2147 pr_err("error %d\n", rc);
2148 goto rw_error;
2149 }
2150
2151 if (read_flag) {
2152
2153 for (i = 0; i < (datasize / 2); i++) {
2154 drxj_dap_read_reg16(dev_addr,
2155 (DRXJ_HI_ATOMIC_BUF_START + i),
2156 &word, 0);
2157 data[2 * i] = (u8) (word & 0xFF);
2158 data[(2 * i) + 1] = (u8) (word >> 8);
2159 }
2160 }
2161
2162 return 0;
2163
2164rw_error:
2165 return rc;
2166
2167}
2168
2169
2170
2171
2172
2173
2174
2175static
2176int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
2177 u32 addr,
2178 u32 *data, u32 flags)
2179{
2180 u8 buf[sizeof(*data)] = { 0 };
2181 int rc = -EIO;
2182 u32 word = 0;
2183
2184 if (!data)
2185 return -EINVAL;
2186
2187 rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2188 sizeof(*data), buf, true);
2189
2190 if (rc < 0)
2191 return 0;
2192
2193 word = (u32) buf[3];
2194 word <<= 8;
2195 word |= (u32) buf[2];
2196 word <<= 8;
2197 word |= (u32) buf[1];
2198 word <<= 8;
2199 word |= (u32) buf[0];
2200
2201 *data = word;
2202
2203 return rc;
2204}
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229static int hi_cfg_command(const struct drx_demod_instance *demod)
2230{
2231 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2232 struct drxj_hi_cmd hi_cmd;
2233 u16 result = 0;
2234 int rc;
2235
2236 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2237
2238 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
2239 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
2240 hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2241 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2242 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2243 hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2244 hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2245
2246 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2247 if (rc != 0) {
2248 pr_err("error %d\n", rc);
2249 goto rw_error;
2250 }
2251
2252
2253 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2254
2255 return 0;
2256
2257rw_error:
2258 return rc;
2259}
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272static int
2273hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
2274{
2275 u16 wait_cmd = 0;
2276 u16 nr_retries = 0;
2277 bool powerdown_cmd = false;
2278 int rc;
2279
2280
2281 switch (cmd->cmd) {
2282
2283 case SIO_HI_RA_RAM_CMD_CONFIG:
2284 case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
2285 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2286 if (rc != 0) {
2287 pr_err("error %d\n", rc);
2288 goto rw_error;
2289 }
2290 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2291 if (rc != 0) {
2292 pr_err("error %d\n", rc);
2293 goto rw_error;
2294 }
2295 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2296 if (rc != 0) {
2297 pr_err("error %d\n", rc);
2298 goto rw_error;
2299 }
2300 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2301 if (rc != 0) {
2302 pr_err("error %d\n", rc);
2303 goto rw_error;
2304 }
2305
2306 case SIO_HI_RA_RAM_CMD_BRDCTRL:
2307 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2308 if (rc != 0) {
2309 pr_err("error %d\n", rc);
2310 goto rw_error;
2311 }
2312 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2313 if (rc != 0) {
2314 pr_err("error %d\n", rc);
2315 goto rw_error;
2316 }
2317
2318 case SIO_HI_RA_RAM_CMD_NULL:
2319
2320 break;
2321
2322 default:
2323 return -EINVAL;
2324 break;
2325 }
2326
2327
2328 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2329 if (rc != 0) {
2330 pr_err("error %d\n", rc);
2331 goto rw_error;
2332 }
2333
2334 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
2335 msleep(1);
2336
2337
2338 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
2339 (((cmd->
2340 param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
2341 == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2342 if (!powerdown_cmd) {
2343
2344 do {
2345 nr_retries++;
2346 if (nr_retries > DRXJ_MAX_RETRIES) {
2347 pr_err("timeout\n");
2348 goto rw_error;
2349 }
2350
2351 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2352 if (rc != 0) {
2353 pr_err("error %d\n", rc);
2354 goto rw_error;
2355 }
2356 } while (wait_cmd != 0);
2357
2358
2359 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2360 if (rc != 0) {
2361 pr_err("error %d\n", rc);
2362 goto rw_error;
2363 }
2364
2365 }
2366
2367 return 0;
2368rw_error:
2369 return rc;
2370}
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385static int init_hi(const struct drx_demod_instance *demod)
2386{
2387 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2388 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2389 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2390 int rc;
2391
2392 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2393 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2394 dev_addr = demod->my_i2c_dev_addr;
2395
2396
2397 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2398 if (rc != 0) {
2399 pr_err("error %d\n", rc);
2400 goto rw_error;
2401 }
2402
2403
2404
2405 ext_attr->hi_cfg_timing_div =
2406 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
2407
2408 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2409 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2410
2411
2412
2413 ext_attr->hi_cfg_bridge_delay =
2414 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
2415 1000;
2416
2417 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2418 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2419
2420 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2421 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
2422
2423
2424
2425 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2426
2427 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2428
2429 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2430
2431 rc = hi_cfg_command(demod);
2432 if (rc != 0) {
2433 pr_err("error %d\n", rc);
2434 goto rw_error;
2435 }
2436
2437 return 0;
2438
2439rw_error:
2440 return rc;
2441}
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469static int get_device_capabilities(struct drx_demod_instance *demod)
2470{
2471 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2472 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
2473 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2474 u16 sio_pdr_ohw_cfg = 0;
2475 u32 sio_top_jtagid_lo = 0;
2476 u16 bid = 0;
2477 int rc;
2478
2479 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2480 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2481 dev_addr = demod->my_i2c_dev_addr;
2482
2483 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2484 if (rc != 0) {
2485 pr_err("error %d\n", rc);
2486 goto rw_error;
2487 }
2488 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2489 if (rc != 0) {
2490 pr_err("error %d\n", rc);
2491 goto rw_error;
2492 }
2493 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2494 if (rc != 0) {
2495 pr_err("error %d\n", rc);
2496 goto rw_error;
2497 }
2498
2499 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
2500 case 0:
2501
2502 break;
2503 case 1:
2504
2505 common_attr->osc_clock_freq = 27000;
2506 break;
2507 case 2:
2508
2509 common_attr->osc_clock_freq = 20250;
2510 break;
2511 case 3:
2512
2513 common_attr->osc_clock_freq = 4000;
2514 break;
2515 default:
2516 return -EIO;
2517 }
2518
2519
2520
2521
2522
2523 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2524 if (rc != 0) {
2525 pr_err("error %d\n", rc);
2526 goto rw_error;
2527 }
2528 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2529
2530 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
2531 case 0x31:
2532 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2533 if (rc != 0) {
2534 pr_err("error %d\n", rc);
2535 goto rw_error;
2536 }
2537 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2538 if (rc != 0) {
2539 pr_err("error %d\n", rc);
2540 goto rw_error;
2541 }
2542 bid = (bid >> 10) & 0xf;
2543 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2544 if (rc != 0) {
2545 pr_err("error %d\n", rc);
2546 goto rw_error;
2547 }
2548
2549 ext_attr->has_lna = true;
2550 ext_attr->has_ntsc = false;
2551 ext_attr->has_btsc = false;
2552 ext_attr->has_oob = false;
2553 ext_attr->has_smatx = true;
2554 ext_attr->has_smarx = false;
2555 ext_attr->has_gpio = false;
2556 ext_attr->has_irqn = false;
2557 break;
2558 case 0x33:
2559 ext_attr->has_lna = false;
2560 ext_attr->has_ntsc = false;
2561 ext_attr->has_btsc = false;
2562 ext_attr->has_oob = false;
2563 ext_attr->has_smatx = true;
2564 ext_attr->has_smarx = false;
2565 ext_attr->has_gpio = false;
2566 ext_attr->has_irqn = false;
2567 break;
2568 case 0x45:
2569 ext_attr->has_lna = true;
2570 ext_attr->has_ntsc = true;
2571 ext_attr->has_btsc = false;
2572 ext_attr->has_oob = false;
2573 ext_attr->has_smatx = true;
2574 ext_attr->has_smarx = true;
2575 ext_attr->has_gpio = true;
2576 ext_attr->has_irqn = false;
2577 break;
2578 case 0x46:
2579 ext_attr->has_lna = false;
2580 ext_attr->has_ntsc = true;
2581 ext_attr->has_btsc = false;
2582 ext_attr->has_oob = false;
2583 ext_attr->has_smatx = true;
2584 ext_attr->has_smarx = true;
2585 ext_attr->has_gpio = true;
2586 ext_attr->has_irqn = false;
2587 break;
2588 case 0x41:
2589 ext_attr->has_lna = true;
2590 ext_attr->has_ntsc = true;
2591 ext_attr->has_btsc = true;
2592 ext_attr->has_oob = false;
2593 ext_attr->has_smatx = true;
2594 ext_attr->has_smarx = true;
2595 ext_attr->has_gpio = true;
2596 ext_attr->has_irqn = false;
2597 break;
2598 case 0x43:
2599 ext_attr->has_lna = false;
2600 ext_attr->has_ntsc = true;
2601 ext_attr->has_btsc = true;
2602 ext_attr->has_oob = false;
2603 ext_attr->has_smatx = true;
2604 ext_attr->has_smarx = true;
2605 ext_attr->has_gpio = true;
2606 ext_attr->has_irqn = false;
2607 break;
2608 case 0x32:
2609 ext_attr->has_lna = true;
2610 ext_attr->has_ntsc = false;
2611 ext_attr->has_btsc = false;
2612 ext_attr->has_oob = true;
2613 ext_attr->has_smatx = true;
2614 ext_attr->has_smarx = true;
2615 ext_attr->has_gpio = true;
2616 ext_attr->has_irqn = true;
2617 break;
2618 case 0x34:
2619 ext_attr->has_lna = false;
2620 ext_attr->has_ntsc = true;
2621 ext_attr->has_btsc = true;
2622 ext_attr->has_oob = true;
2623 ext_attr->has_smatx = true;
2624 ext_attr->has_smarx = true;
2625 ext_attr->has_gpio = true;
2626 ext_attr->has_irqn = true;
2627 break;
2628 case 0x42:
2629 ext_attr->has_lna = true;
2630 ext_attr->has_ntsc = true;
2631 ext_attr->has_btsc = true;
2632 ext_attr->has_oob = true;
2633 ext_attr->has_smatx = true;
2634 ext_attr->has_smarx = true;
2635 ext_attr->has_gpio = true;
2636 ext_attr->has_irqn = true;
2637 break;
2638 case 0x44:
2639 ext_attr->has_lna = false;
2640 ext_attr->has_ntsc = true;
2641 ext_attr->has_btsc = true;
2642 ext_attr->has_oob = true;
2643 ext_attr->has_smatx = true;
2644 ext_attr->has_smarx = true;
2645 ext_attr->has_gpio = true;
2646 ext_attr->has_irqn = true;
2647 break;
2648 default:
2649
2650 return -EIO;
2651 break;
2652 }
2653
2654 return 0;
2655rw_error:
2656 return rc;
2657}
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669#ifndef DRXJ_MAX_RETRIES_POWERUP
2670#define DRXJ_MAX_RETRIES_POWERUP 10
2671#endif
2672
2673static int power_up_device(struct drx_demod_instance *demod)
2674{
2675 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2676 u8 data = 0;
2677 u16 retry_count = 0;
2678 struct i2c_device_addr wake_up_addr;
2679
2680 dev_addr = demod->my_i2c_dev_addr;
2681 wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
2682 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
2683 wake_up_addr.user_data = dev_addr->user_data;
2684
2685
2686
2687
2688
2689 do {
2690 data = 0;
2691 drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
2692 (struct i2c_device_addr *)(NULL), 0,
2693 (u8 *)(NULL));
2694 msleep(10);
2695 retry_count++;
2696 } while ((drxbsp_i2c_write_read
2697 ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
2698 &data)
2699 != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
2700
2701
2702 msleep(10);
2703
2704 if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
2705 return -EIO;
2706
2707 return 0;
2708}
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723static int
2724ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
2725{
2726 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2727 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2728 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2729 int rc;
2730 u16 fec_oc_reg_mode = 0;
2731 u16 fec_oc_reg_ipr_mode = 0;
2732 u16 fec_oc_reg_ipr_invert = 0;
2733 u32 max_bit_rate = 0;
2734 u32 rcn_rate = 0;
2735 u32 nr_bits = 0;
2736 u16 sio_pdr_md_cfg = 0;
2737
2738 u16 invert_data_mask =
2739 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2740 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2741 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2742 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2743
2744
2745 if ((demod == NULL) || (cfg_data == NULL))
2746 return -EINVAL;
2747
2748 dev_addr = demod->my_i2c_dev_addr;
2749 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2750 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2751
2752 if (cfg_data->enable_mpeg_output == true) {
2753
2754
2755 switch (ext_attr->standard) {
2756 case DRX_STANDARD_8VSB:
2757 case DRX_STANDARD_ITU_A:
2758 case DRX_STANDARD_ITU_B:
2759 case DRX_STANDARD_ITU_C:
2760 break;
2761 default:
2762 return 0;
2763 }
2764
2765 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2766 if (rc != 0) {
2767 pr_err("error %d\n", rc);
2768 goto rw_error;
2769 }
2770 switch (ext_attr->standard) {
2771 case DRX_STANDARD_8VSB:
2772 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2773 if (rc != 0) {
2774 pr_err("error %d\n", rc);
2775 goto rw_error;
2776 }
2777 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2778 if (rc != 0) {
2779 pr_err("error %d\n", rc);
2780 goto rw_error;
2781 }
2782 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2783 if (rc != 0) {
2784 pr_err("error %d\n", rc);
2785 goto rw_error;
2786 }
2787 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2788 if (rc != 0) {
2789 pr_err("error %d\n", rc);
2790 goto rw_error;
2791 }
2792 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2793 if (rc != 0) {
2794 pr_err("error %d\n", rc);
2795 goto rw_error;
2796 }
2797 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2798 if (rc != 0) {
2799 pr_err("error %d\n", rc);
2800 goto rw_error;
2801 }
2802
2803 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2804 if (rc != 0) {
2805 pr_err("error %d\n", rc);
2806 goto rw_error;
2807 }
2808
2809 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2810 if (rc != 0) {
2811 pr_err("error %d\n", rc);
2812 goto rw_error;
2813 }
2814 break;
2815 case DRX_STANDARD_ITU_A:
2816 case DRX_STANDARD_ITU_C:
2817 switch (ext_attr->constellation) {
2818 case DRX_CONSTELLATION_QAM256:
2819 nr_bits = 8;
2820 break;
2821 case DRX_CONSTELLATION_QAM128:
2822 nr_bits = 7;
2823 break;
2824 case DRX_CONSTELLATION_QAM64:
2825 nr_bits = 6;
2826 break;
2827 case DRX_CONSTELLATION_QAM32:
2828 nr_bits = 5;
2829 break;
2830 case DRX_CONSTELLATION_QAM16:
2831 nr_bits = 4;
2832 break;
2833 default:
2834 return -EIO;
2835 }
2836
2837
2838 max_bit_rate =
2839 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2840
2841
2842 case DRX_STANDARD_ITU_B:
2843 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2844 if (rc != 0) {
2845 pr_err("error %d\n", rc);
2846 goto rw_error;
2847 }
2848 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2849 if (rc != 0) {
2850 pr_err("error %d\n", rc);
2851 goto rw_error;
2852 }
2853 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2854 if (rc != 0) {
2855 pr_err("error %d\n", rc);
2856 goto rw_error;
2857 }
2858 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2859 if (rc != 0) {
2860 pr_err("error %d\n", rc);
2861 goto rw_error;
2862 }
2863 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2864 if (rc != 0) {
2865 pr_err("error %d\n", rc);
2866 goto rw_error;
2867 }
2868 if (cfg_data->static_clk == true) {
2869 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2870 if (rc != 0) {
2871 pr_err("error %d\n", rc);
2872 goto rw_error;
2873 }
2874 } else {
2875 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2876 if (rc != 0) {
2877 pr_err("error %d\n", rc);
2878 goto rw_error;
2879 }
2880 }
2881 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2882 if (rc != 0) {
2883 pr_err("error %d\n", rc);
2884 goto rw_error;
2885 }
2886 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2887 if (rc != 0) {
2888 pr_err("error %d\n", rc);
2889 goto rw_error;
2890 }
2891 break;
2892 default:
2893 break;
2894 }
2895
2896
2897 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2898 if (rc != 0) {
2899 pr_err("error %d\n", rc);
2900 goto rw_error;
2901 }
2902 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2903 if (rc != 0) {
2904 pr_err("error %d\n", rc);
2905 goto rw_error;
2906 }
2907 if (cfg_data->insert_rs_byte == true) {
2908
2909 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2910
2911 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2912 switch (ext_attr->standard) {
2913 case DRX_STANDARD_8VSB:
2914 rcn_rate = 0x004854D3;
2915 break;
2916 case DRX_STANDARD_ITU_B:
2917 fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
2918 switch (ext_attr->constellation) {
2919 case DRX_CONSTELLATION_QAM256:
2920 rcn_rate = 0x008945E7;
2921 break;
2922 case DRX_CONSTELLATION_QAM64:
2923 rcn_rate = 0x005F64D4;
2924 break;
2925 default:
2926 return -EIO;
2927 }
2928 break;
2929 case DRX_STANDARD_ITU_A:
2930 case DRX_STANDARD_ITU_C:
2931
2932 rcn_rate =
2933 (frac28
2934 (max_bit_rate,
2935 (u32) (common_attr->sys_clock_freq / 8))) /
2936 188;
2937 break;
2938 default:
2939 return -EIO;
2940 }
2941 } else {
2942
2943
2944 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2945
2946 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2947 switch (ext_attr->standard) {
2948 case DRX_STANDARD_8VSB:
2949 rcn_rate = 0x0041605C;
2950 break;
2951 case DRX_STANDARD_ITU_B:
2952 fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
2953 switch (ext_attr->constellation) {
2954 case DRX_CONSTELLATION_QAM256:
2955 rcn_rate = 0x0082D6A0;
2956 break;
2957 case DRX_CONSTELLATION_QAM64:
2958 rcn_rate = 0x005AEC1A;
2959 break;
2960 default:
2961 return -EIO;
2962 }
2963 break;
2964 case DRX_STANDARD_ITU_A:
2965 case DRX_STANDARD_ITU_C:
2966
2967 rcn_rate =
2968 (frac28
2969 (max_bit_rate,
2970 (u32) (common_attr->sys_clock_freq / 8))) /
2971 204;
2972 break;
2973 default:
2974 return -EIO;
2975 }
2976 }
2977
2978 if (cfg_data->enable_parallel == true) {
2979 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2980 } else {
2981 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2982 }
2983
2984
2985 if (cfg_data->invert_data == true)
2986 fec_oc_reg_ipr_invert |= invert_data_mask;
2987 else
2988 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2989
2990 if (cfg_data->invert_err == true)
2991 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2992 else
2993 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2994
2995 if (cfg_data->invert_str == true)
2996 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2997 else
2998 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2999
3000 if (cfg_data->invert_val == true)
3001 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
3002 else
3003 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
3004
3005 if (cfg_data->invert_clk == true)
3006 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
3007 else
3008 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
3009
3010
3011 if (cfg_data->static_clk == true) {
3012 u32 dto_rate = 0;
3013 u32 bit_rate = 0;
3014 u16 fec_oc_dto_burst_len = 0;
3015 u16 fec_oc_dto_period = 0;
3016
3017 fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
3018
3019 switch (ext_attr->standard) {
3020 case DRX_STANDARD_8VSB:
3021 fec_oc_dto_period = 4;
3022 if (cfg_data->insert_rs_byte == true)
3023 fec_oc_dto_burst_len = 208;
3024 break;
3025 case DRX_STANDARD_ITU_A:
3026 {
3027 u32 symbol_rate_th = 6400000;
3028 if (cfg_data->insert_rs_byte == true) {
3029 fec_oc_dto_burst_len = 204;
3030 symbol_rate_th = 5900000;
3031 }
3032 if (ext_attr->curr_symbol_rate >=
3033 symbol_rate_th) {
3034 fec_oc_dto_period = 0;
3035 } else {
3036 fec_oc_dto_period = 1;
3037 }
3038 }
3039 break;
3040 case DRX_STANDARD_ITU_B:
3041 fec_oc_dto_period = 1;
3042 if (cfg_data->insert_rs_byte == true)
3043 fec_oc_dto_burst_len = 128;
3044 break;
3045 case DRX_STANDARD_ITU_C:
3046 fec_oc_dto_period = 1;
3047 if (cfg_data->insert_rs_byte == true)
3048 fec_oc_dto_burst_len = 204;
3049 break;
3050 default:
3051 return -EIO;
3052 }
3053 bit_rate =
3054 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
3055 2);
3056 dto_rate =
3057 frac28(bit_rate, common_attr->sys_clock_freq * 1000);
3058 dto_rate >>= 3;
3059 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3060 if (rc != 0) {
3061 pr_err("error %d\n", rc);
3062 goto rw_error;
3063 }
3064 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3065 if (rc != 0) {
3066 pr_err("error %d\n", rc);
3067 goto rw_error;
3068 }
3069 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3070 if (rc != 0) {
3071 pr_err("error %d\n", rc);
3072 goto rw_error;
3073 }
3074 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3075 if (rc != 0) {
3076 pr_err("error %d\n", rc);
3077 goto rw_error;
3078 }
3079 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3080 if (rc != 0) {
3081 pr_err("error %d\n", rc);
3082 goto rw_error;
3083 }
3084 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3085 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3086 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3087 if (rc != 0) {
3088 pr_err("error %d\n", rc);
3089 goto rw_error;
3090 }
3091 } else {
3092
3093 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3094 if (rc != 0) {
3095 pr_err("error %d\n", rc);
3096 goto rw_error;
3097 }
3098 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3099 if (rc != 0) {
3100 pr_err("error %d\n", rc);
3101 goto rw_error;
3102 }
3103 }
3104
3105 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3106 if (rc != 0) {
3107 pr_err("error %d\n", rc);
3108 goto rw_error;
3109 }
3110
3111
3112 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3113 if (rc != 0) {
3114 pr_err("error %d\n", rc);
3115 goto rw_error;
3116 }
3117 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3118 if (rc != 0) {
3119 pr_err("error %d\n", rc);
3120 goto rw_error;
3121 }
3122 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3123 if (rc != 0) {
3124 pr_err("error %d\n", rc);
3125 goto rw_error;
3126 }
3127
3128
3129
3130 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3131 if (rc != 0) {
3132 pr_err("error %d\n", rc);
3133 goto rw_error;
3134 }
3135
3136 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3137 if (rc != 0) {
3138 pr_err("error %d\n", rc);
3139 goto rw_error;
3140 }
3141 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3142 if (rc != 0) {
3143 pr_err("error %d\n", rc);
3144 goto rw_error;
3145 }
3146 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3147 if (rc != 0) {
3148 pr_err("error %d\n", rc);
3149 goto rw_error;
3150 }
3151 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3152 if (rc != 0) {
3153 pr_err("error %d\n", rc);
3154 goto rw_error;
3155 }
3156 sio_pdr_md_cfg =
3157 MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
3158 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
3159 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3160 if (rc != 0) {
3161 pr_err("error %d\n", rc);
3162 goto rw_error;
3163 }
3164 if (cfg_data->enable_parallel == true) {
3165 sio_pdr_md_cfg =
3166 MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
3167 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
3168 SIO_PDR_MD0_CFG_MODE__B;
3169 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3170 if (rc != 0) {
3171 pr_err("error %d\n", rc);
3172 goto rw_error;
3173 }
3174 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3175 if (rc != 0) {
3176 pr_err("error %d\n", rc);
3177 goto rw_error;
3178 }
3179 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3180 if (rc != 0) {
3181 pr_err("error %d\n", rc);
3182 goto rw_error;
3183 }
3184 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3185 if (rc != 0) {
3186 pr_err("error %d\n", rc);
3187 goto rw_error;
3188 }
3189 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3190 if (rc != 0) {
3191 pr_err("error %d\n", rc);
3192 goto rw_error;
3193 }
3194 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3195 if (rc != 0) {
3196 pr_err("error %d\n", rc);
3197 goto rw_error;
3198 }
3199 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3200 if (rc != 0) {
3201 pr_err("error %d\n", rc);
3202 goto rw_error;
3203 }
3204 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3205 if (rc != 0) {
3206 pr_err("error %d\n", rc);
3207 goto rw_error;
3208 }
3209 } else {
3210 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3211 if (rc != 0) {
3212 pr_err("error %d\n", rc);
3213 goto rw_error;
3214 }
3215 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3216 if (rc != 0) {
3217 pr_err("error %d\n", rc);
3218 goto rw_error;
3219 }
3220 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3221 if (rc != 0) {
3222 pr_err("error %d\n", rc);
3223 goto rw_error;
3224 }
3225 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3226 if (rc != 0) {
3227 pr_err("error %d\n", rc);
3228 goto rw_error;
3229 }
3230 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3231 if (rc != 0) {
3232 pr_err("error %d\n", rc);
3233 goto rw_error;
3234 }
3235 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3236 if (rc != 0) {
3237 pr_err("error %d\n", rc);
3238 goto rw_error;
3239 }
3240 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3241 if (rc != 0) {
3242 pr_err("error %d\n", rc);
3243 goto rw_error;
3244 }
3245 }
3246
3247 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3248 if (rc != 0) {
3249 pr_err("error %d\n", rc);
3250 goto rw_error;
3251 }
3252
3253 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3254 if (rc != 0) {
3255 pr_err("error %d\n", rc);
3256 goto rw_error;
3257 }
3258 } else {
3259
3260 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3261 if (rc != 0) {
3262 pr_err("error %d\n", rc);
3263 goto rw_error;
3264 }
3265
3266 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3267 if (rc != 0) {
3268 pr_err("error %d\n", rc);
3269 goto rw_error;
3270 }
3271 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3272 if (rc != 0) {
3273 pr_err("error %d\n", rc);
3274 goto rw_error;
3275 }
3276 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3277 if (rc != 0) {
3278 pr_err("error %d\n", rc);
3279 goto rw_error;
3280 }
3281 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3282 if (rc != 0) {
3283 pr_err("error %d\n", rc);
3284 goto rw_error;
3285 }
3286 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3287 if (rc != 0) {
3288 pr_err("error %d\n", rc);
3289 goto rw_error;
3290 }
3291 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3292 if (rc != 0) {
3293 pr_err("error %d\n", rc);
3294 goto rw_error;
3295 }
3296 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3297 if (rc != 0) {
3298 pr_err("error %d\n", rc);
3299 goto rw_error;
3300 }
3301 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3302 if (rc != 0) {
3303 pr_err("error %d\n", rc);
3304 goto rw_error;
3305 }
3306 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3307 if (rc != 0) {
3308 pr_err("error %d\n", rc);
3309 goto rw_error;
3310 }
3311 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3312 if (rc != 0) {
3313 pr_err("error %d\n", rc);
3314 goto rw_error;
3315 }
3316 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3317 if (rc != 0) {
3318 pr_err("error %d\n", rc);
3319 goto rw_error;
3320 }
3321 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3322 if (rc != 0) {
3323 pr_err("error %d\n", rc);
3324 goto rw_error;
3325 }
3326
3327 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3328 if (rc != 0) {
3329 pr_err("error %d\n", rc);
3330 goto rw_error;
3331 }
3332
3333 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3334 if (rc != 0) {
3335 pr_err("error %d\n", rc);
3336 goto rw_error;
3337 }
3338 }
3339
3340
3341 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
3342
3343 return 0;
3344rw_error:
3345 return rc;
3346}
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368static int set_mpegtei_handling(struct drx_demod_instance *demod)
3369{
3370 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3371 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3372 int rc;
3373 u16 fec_oc_dpr_mode = 0;
3374 u16 fec_oc_snc_mode = 0;
3375 u16 fec_oc_ems_mode = 0;
3376
3377 dev_addr = demod->my_i2c_dev_addr;
3378 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3379
3380 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3381 if (rc != 0) {
3382 pr_err("error %d\n", rc);
3383 goto rw_error;
3384 }
3385 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3386 if (rc != 0) {
3387 pr_err("error %d\n", rc);
3388 goto rw_error;
3389 }
3390 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3391 if (rc != 0) {
3392 pr_err("error %d\n", rc);
3393 goto rw_error;
3394 }
3395
3396
3397 fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
3398 fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
3399 FEC_OC_SNC_MODE_CORR_DISABLE__M));
3400 fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
3401
3402 if (ext_attr->disable_te_ihandling) {
3403
3404 fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
3405 fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
3406 ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
3407 fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
3408 }
3409
3410 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3411 if (rc != 0) {
3412 pr_err("error %d\n", rc);
3413 goto rw_error;
3414 }
3415 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3416 if (rc != 0) {
3417 pr_err("error %d\n", rc);
3418 goto rw_error;
3419 }
3420 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3421 if (rc != 0) {
3422 pr_err("error %d\n", rc);
3423 goto rw_error;
3424 }
3425
3426 return 0;
3427rw_error:
3428 return rc;
3429}
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
3442{
3443 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3444 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3445 int rc;
3446 u16 fec_oc_ipr_mode = 0;
3447
3448 dev_addr = demod->my_i2c_dev_addr;
3449 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3450
3451 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3452 if (rc != 0) {
3453 pr_err("error %d\n", rc);
3454 goto rw_error;
3455 }
3456
3457
3458 fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
3459
3460 if (ext_attr->bit_reverse_mpeg_outout)
3461 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
3462
3463 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3464 if (rc != 0) {
3465 pr_err("error %d\n", rc);
3466 goto rw_error;
3467 }
3468
3469 return 0;
3470rw_error:
3471 return rc;
3472}
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484static int set_mpeg_start_width(struct drx_demod_instance *demod)
3485{
3486 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3487 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3488 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
3489 int rc;
3490 u16 fec_oc_comm_mb = 0;
3491
3492 dev_addr = demod->my_i2c_dev_addr;
3493 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3494 common_attr = demod->my_common_attr;
3495
3496 if ((common_attr->mpeg_cfg.static_clk == true)
3497 && (common_attr->mpeg_cfg.enable_parallel == false)) {
3498 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3499 if (rc != 0) {
3500 pr_err("error %d\n", rc);
3501 goto rw_error;
3502 }
3503 fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
3504 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3505 fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
3506 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3507 if (rc != 0) {
3508 pr_err("error %d\n", rc);
3509 goto rw_error;
3510 }
3511 }
3512
3513 return 0;
3514rw_error:
3515 return rc;
3516}
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
3533{
3534 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3535 int rc;
3536
3537 if ((uio_cfg == NULL) || (demod == NULL))
3538 return -EINVAL;
3539
3540 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3541
3542
3543 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3544 if (rc != 0) {
3545 pr_err("error %d\n", rc);
3546 goto rw_error;
3547 }
3548 switch (uio_cfg->uio) {
3549
3550 case DRX_UIO1:
3551
3552 if (!ext_attr->has_smatx)
3553 return -EIO;
3554 switch (uio_cfg->mode) {
3555 case DRX_UIO_MODE_FIRMWARE_SMA:
3556 case DRX_UIO_MODE_FIRMWARE_SAW:
3557 case DRX_UIO_MODE_READWRITE:
3558 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3559 break;
3560 case DRX_UIO_MODE_DISABLE:
3561 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3562
3563 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3564 if (rc != 0) {
3565 pr_err("error %d\n", rc);
3566 goto rw_error;
3567 }
3568 break;
3569 default:
3570 return -EINVAL;
3571 }
3572 break;
3573
3574 case DRX_UIO2:
3575
3576 if (!ext_attr->has_smarx)
3577 return -EIO;
3578 switch (uio_cfg->mode) {
3579 case DRX_UIO_MODE_FIRMWARE0:
3580 case DRX_UIO_MODE_READWRITE:
3581 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3582 break;
3583 case DRX_UIO_MODE_DISABLE:
3584 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3585
3586 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3587 if (rc != 0) {
3588 pr_err("error %d\n", rc);
3589 goto rw_error;
3590 }
3591 break;
3592 default:
3593 return -EINVAL;
3594 break;
3595 }
3596 break;
3597
3598 case DRX_UIO3:
3599
3600 if (!ext_attr->has_gpio)
3601 return -EIO;
3602 switch (uio_cfg->mode) {
3603 case DRX_UIO_MODE_FIRMWARE0:
3604 case DRX_UIO_MODE_READWRITE:
3605 ext_attr->uio_gpio_mode = uio_cfg->mode;
3606 break;
3607 case DRX_UIO_MODE_DISABLE:
3608 ext_attr->uio_gpio_mode = uio_cfg->mode;
3609
3610 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3611 if (rc != 0) {
3612 pr_err("error %d\n", rc);
3613 goto rw_error;
3614 }
3615 break;
3616 default:
3617 return -EINVAL;
3618 break;
3619 }
3620 break;
3621
3622 case DRX_UIO4:
3623
3624 if (!ext_attr->has_irqn)
3625 return -EIO;
3626 switch (uio_cfg->mode) {
3627 case DRX_UIO_MODE_READWRITE:
3628 ext_attr->uio_irqn_mode = uio_cfg->mode;
3629 break;
3630 case DRX_UIO_MODE_DISABLE:
3631
3632 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3633 if (rc != 0) {
3634 pr_err("error %d\n", rc);
3635 goto rw_error;
3636 }
3637 ext_attr->uio_irqn_mode = uio_cfg->mode;
3638 break;
3639 case DRX_UIO_MODE_FIRMWARE0:
3640 default:
3641 return -EINVAL;
3642 break;
3643 }
3644 break;
3645
3646 default:
3647 return -EINVAL;
3648 }
3649
3650
3651 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3652 if (rc != 0) {
3653 pr_err("error %d\n", rc);
3654 goto rw_error;
3655 }
3656
3657 return 0;
3658rw_error:
3659 return rc;
3660}
3661
3662
3663
3664
3665
3666
3667
3668
3669static int
3670ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
3671{
3672 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3673 int rc;
3674 u16 pin_cfg_value = 0;
3675 u16 value = 0;
3676
3677 if ((uio_data == NULL) || (demod == NULL))
3678 return -EINVAL;
3679
3680 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3681
3682
3683 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3684 if (rc != 0) {
3685 pr_err("error %d\n", rc);
3686 goto rw_error;
3687 }
3688 switch (uio_data->uio) {
3689
3690 case DRX_UIO1:
3691
3692 if (!ext_attr->has_smatx)
3693 return -EIO;
3694 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3695 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3696 return -EIO;
3697 }
3698 pin_cfg_value = 0;
3699
3700 pin_cfg_value |= 0x0113;
3701
3702
3703
3704
3705 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3706 if (rc != 0) {
3707 pr_err("error %d\n", rc);
3708 goto rw_error;
3709 }
3710
3711
3712 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3713 if (rc != 0) {
3714 pr_err("error %d\n", rc);
3715 goto rw_error;
3716 }
3717 if (!uio_data->value)
3718 value &= 0x7FFF;
3719 else
3720 value |= 0x8000;
3721
3722
3723 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3724 if (rc != 0) {
3725 pr_err("error %d\n", rc);
3726 goto rw_error;
3727 }
3728 break;
3729
3730 case DRX_UIO2:
3731
3732 if (!ext_attr->has_smarx)
3733 return -EIO;
3734 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3735 return -EIO;
3736
3737 pin_cfg_value = 0;
3738
3739 pin_cfg_value |= 0x0113;
3740
3741
3742
3743
3744 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3745 if (rc != 0) {
3746 pr_err("error %d\n", rc);
3747 goto rw_error;
3748 }
3749
3750
3751 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3752 if (rc != 0) {
3753 pr_err("error %d\n", rc);
3754 goto rw_error;
3755 }
3756 if (!uio_data->value)
3757 value &= 0xBFFF;
3758 else
3759 value |= 0x4000;
3760
3761
3762 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3763 if (rc != 0) {
3764 pr_err("error %d\n", rc);
3765 goto rw_error;
3766 }
3767 break;
3768
3769 case DRX_UIO3:
3770
3771 if (!ext_attr->has_gpio)
3772 return -EIO;
3773 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3774 return -EIO;
3775
3776 pin_cfg_value = 0;
3777
3778 pin_cfg_value |= 0x0113;
3779
3780
3781
3782
3783 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3784 if (rc != 0) {
3785 pr_err("error %d\n", rc);
3786 goto rw_error;
3787 }
3788
3789
3790 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3791 if (rc != 0) {
3792 pr_err("error %d\n", rc);
3793 goto rw_error;
3794 }
3795 if (!uio_data->value)
3796 value &= 0xFFFB;
3797 else
3798 value |= 0x0004;
3799
3800
3801 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3802 if (rc != 0) {
3803 pr_err("error %d\n", rc);
3804 goto rw_error;
3805 }
3806 break;
3807
3808 case DRX_UIO4:
3809
3810 if (!ext_attr->has_irqn)
3811 return -EIO;
3812
3813 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3814 return -EIO;
3815
3816 pin_cfg_value = 0;
3817
3818 pin_cfg_value |= 0x0113;
3819
3820
3821
3822
3823 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3824 if (rc != 0) {
3825 pr_err("error %d\n", rc);
3826 goto rw_error;
3827 }
3828
3829
3830 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3831 if (rc != 0) {
3832 pr_err("error %d\n", rc);
3833 goto rw_error;
3834 }
3835 if (uio_data->value == false)
3836 value &= 0xEFFF;
3837 else
3838 value |= 0x1000;
3839
3840
3841 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3842 if (rc != 0) {
3843 pr_err("error %d\n", rc);
3844 goto rw_error;
3845 }
3846 break;
3847
3848 default:
3849 return -EINVAL;
3850 }
3851
3852
3853 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3854 if (rc != 0) {
3855 pr_err("error %d\n", rc);
3856 goto rw_error;
3857 }
3858
3859 return 0;
3860rw_error:
3861 return rc;
3862}
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879static int
3880ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
3881{
3882 struct drxj_hi_cmd hi_cmd;
3883 u16 result = 0;
3884
3885
3886 if (bridge_closed == NULL)
3887 return -EINVAL;
3888
3889 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
3890 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
3891 if (*bridge_closed)
3892 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
3893 else
3894 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
3895
3896 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3897}
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913static int smart_ant_init(struct drx_demod_instance *demod)
3914{
3915 struct drxj_data *ext_attr = NULL;
3916 struct i2c_device_addr *dev_addr = NULL;
3917 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
3918 int rc;
3919 u16 data = 0;
3920
3921 dev_addr = demod->my_i2c_dev_addr;
3922 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3923
3924
3925 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3926 if (rc != 0) {
3927 pr_err("error %d\n", rc);
3928 goto rw_error;
3929 }
3930
3931 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3932 if (rc != 0) {
3933 pr_err("error %d\n", rc);
3934 goto rw_error;
3935 }
3936 if (ext_attr->smart_ant_inverted) {
3937 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3938 if (rc != 0) {
3939 pr_err("error %d\n", rc);
3940 goto rw_error;
3941 }
3942 } else {
3943 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3944 if (rc != 0) {
3945 pr_err("error %d\n", rc);
3946 goto rw_error;
3947 }
3948 }
3949
3950
3951 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3952 if (rc != 0) {
3953 pr_err("error %d\n", rc);
3954 goto rw_error;
3955 }
3956 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3957 if (rc != 0) {
3958 pr_err("error %d\n", rc);
3959 goto rw_error;
3960 }
3961 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3962 if (rc != 0) {
3963 pr_err("error %d\n", rc);
3964 goto rw_error;
3965 }
3966
3967
3968 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3969 if (rc != 0) {
3970 pr_err("error %d\n", rc);
3971 goto rw_error;
3972 }
3973
3974 return 0;
3975rw_error:
3976 return rc;
3977}
3978
3979static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
3980{
3981 int rc;
3982 u16 cur_cmd = 0;
3983 unsigned long timeout;
3984
3985
3986 if (cmd == NULL)
3987 return -EINVAL;
3988
3989
3990 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3991 if (rc != 0) {
3992 pr_err("error %d\n", rc);
3993 goto rw_error;
3994 }
3995 if (cur_cmd != DRX_SCU_READY)
3996 return -EIO;
3997
3998 switch (cmd->parameter_len) {
3999 case 5:
4000 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
4001 if (rc != 0) {
4002 pr_err("error %d\n", rc);
4003 goto rw_error;
4004 }
4005 case 4:
4006 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4007 if (rc != 0) {
4008 pr_err("error %d\n", rc);
4009 goto rw_error;
4010 }
4011 case 3:
4012 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4013 if (rc != 0) {
4014 pr_err("error %d\n", rc);
4015 goto rw_error;
4016 }
4017 case 2:
4018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4019 if (rc != 0) {
4020 pr_err("error %d\n", rc);
4021 goto rw_error;
4022 }
4023 case 1:
4024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4025 if (rc != 0) {
4026 pr_err("error %d\n", rc);
4027 goto rw_error;
4028 }
4029 case 0:
4030
4031 break;
4032 default:
4033
4034 return -EIO;
4035 }
4036 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4037 if (rc != 0) {
4038 pr_err("error %d\n", rc);
4039 goto rw_error;
4040 }
4041
4042
4043 timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
4044 while (time_is_after_jiffies(timeout)) {
4045 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4046 if (rc != 0) {
4047 pr_err("error %d\n", rc);
4048 goto rw_error;
4049 }
4050 if (cur_cmd == DRX_SCU_READY)
4051 break;
4052 usleep_range(1000, 2000);
4053 }
4054
4055 if (cur_cmd != DRX_SCU_READY)
4056 return -EIO;
4057
4058
4059 if ((cmd->result_len > 0) && (cmd->result != NULL)) {
4060 s16 err;
4061
4062 switch (cmd->result_len) {
4063 case 4:
4064 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4065 if (rc != 0) {
4066 pr_err("error %d\n", rc);
4067 goto rw_error;
4068 }
4069 case 3:
4070 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4071 if (rc != 0) {
4072 pr_err("error %d\n", rc);
4073 goto rw_error;
4074 }
4075 case 2:
4076 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4077 if (rc != 0) {
4078 pr_err("error %d\n", rc);
4079 goto rw_error;
4080 }
4081 case 1:
4082 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4083 if (rc != 0) {
4084 pr_err("error %d\n", rc);
4085 goto rw_error;
4086 }
4087 case 0:
4088
4089 break;
4090 default:
4091
4092 return -EIO;
4093 }
4094
4095
4096 err = cmd->result[0];
4097
4098
4099 if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
4100 || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
4101 || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
4102 || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
4103 ) {
4104 return -EINVAL;
4105 }
4106
4107 else if (err < 0)
4108 return -EIO;
4109 else
4110 return 0;
4111 }
4112
4113 return 0;
4114
4115rw_error:
4116 return rc;
4117}
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131#define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4132static
4133int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize,
4134 u8 *data, bool read_flag)
4135{
4136 struct drxjscu_cmd scu_cmd;
4137 int rc;
4138 u16 set_param_parameters[18];
4139 u16 cmd_result[15];
4140
4141
4142 if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
4143 return -EINVAL;
4144
4145 set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
4146 if (read_flag) {
4147 set_param_parameters[0] = ((~(0x0080)) & datasize);
4148 scu_cmd.parameter_len = 2;
4149 scu_cmd.result_len = datasize / 2 + 2;
4150 } else {
4151 int i = 0;
4152
4153 set_param_parameters[0] = 0x0080 | datasize;
4154 for (i = 0; i < (datasize / 2); i++) {
4155 set_param_parameters[i + 2] =
4156 (data[2 * i] | (data[(2 * i) + 1] << 8));
4157 }
4158 scu_cmd.parameter_len = datasize / 2 + 2;
4159 scu_cmd.result_len = 1;
4160 }
4161
4162 scu_cmd.command =
4163 SCU_RAM_COMMAND_STANDARD_TOP |
4164 SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
4165 scu_cmd.result = cmd_result;
4166 scu_cmd.parameter = set_param_parameters;
4167 rc = scu_command(dev_addr, &scu_cmd);
4168 if (rc != 0) {
4169 pr_err("error %d\n", rc);
4170 goto rw_error;
4171 }
4172
4173 if (read_flag) {
4174 int i = 0;
4175
4176 for (i = 0; i < (datasize / 2); i++) {
4177 data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
4178 data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
4179 }
4180 }
4181
4182 return 0;
4183
4184rw_error:
4185 return rc;
4186
4187}
4188
4189
4190
4191
4192
4193
4194
4195static
4196int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
4197 u32 addr,
4198 u16 *data, u32 flags)
4199{
4200 u8 buf[2] = { 0 };
4201 int rc = -EIO;
4202 u16 word = 0;
4203
4204 if (!data)
4205 return -EINVAL;
4206
4207 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4208 if (rc < 0)
4209 return rc;
4210
4211 word = (u16) (buf[0] + (buf[1] << 8));
4212
4213 *data = word;
4214
4215 return rc;
4216}
4217
4218
4219
4220
4221
4222
4223static
4224int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
4225 u32 addr,
4226 u16 data, u32 flags)
4227{
4228 u8 buf[2];
4229 int rc = -EIO;
4230
4231 buf[0] = (u8) (data & 0xff);
4232 buf[1] = (u8) ((data >> 8) & 0xff);
4233
4234 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4235
4236 return rc;
4237}
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
4250{
4251 struct i2c_device_addr *dev_addr = NULL;
4252 int rc;
4253 u16 data = 0;
4254
4255 dev_addr = demod->my_i2c_dev_addr;
4256
4257
4258 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4259 if (rc != 0) {
4260 pr_err("error %d\n", rc);
4261 goto rw_error;
4262 }
4263 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4264 if (rc != 0) {
4265 pr_err("error %d\n", rc);
4266 goto rw_error;
4267 }
4268
4269
4270 msleep(1);
4271
4272 *count = 0;
4273 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4274 if (rc != 0) {
4275 pr_err("error %d\n", rc);
4276 goto rw_error;
4277 }
4278 if (data == 127)
4279 *count = *count + 1;
4280 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4281 if (rc != 0) {
4282 pr_err("error %d\n", rc);
4283 goto rw_error;
4284 }
4285 if (data == 127)
4286 *count = *count + 1;
4287 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4288 if (rc != 0) {
4289 pr_err("error %d\n", rc);
4290 goto rw_error;
4291 }
4292 if (data == 127)
4293 *count = *count + 1;
4294
4295 return 0;
4296rw_error:
4297 return rc;
4298}
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312static int adc_synchronization(struct drx_demod_instance *demod)
4313{
4314 struct i2c_device_addr *dev_addr = NULL;
4315 int rc;
4316 u16 count = 0;
4317
4318 dev_addr = demod->my_i2c_dev_addr;
4319
4320 rc = adc_sync_measurement(demod, &count);
4321 if (rc != 0) {
4322 pr_err("error %d\n", rc);
4323 goto rw_error;
4324 }
4325
4326 if (count == 1) {
4327
4328 u16 clk_neg = 0;
4329
4330 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4331 if (rc != 0) {
4332 pr_err("error %d\n", rc);
4333 goto rw_error;
4334 }
4335
4336 clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
4337 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4338 if (rc != 0) {
4339 pr_err("error %d\n", rc);
4340 goto rw_error;
4341 }
4342
4343 rc = adc_sync_measurement(demod, &count);
4344 if (rc != 0) {
4345 pr_err("error %d\n", rc);
4346 goto rw_error;
4347 }
4348 }
4349
4350
4351 if (count < 2)
4352 return -EIO;
4353
4354 return 0;
4355rw_error:
4356 return rc;
4357}
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375static int init_agc(struct drx_demod_instance *demod)
4376{
4377 struct i2c_device_addr *dev_addr = NULL;
4378 struct drx_common_attr *common_attr = NULL;
4379 struct drxj_data *ext_attr = NULL;
4380 struct drxj_cfg_agc *p_agc_rf_settings = NULL;
4381 struct drxj_cfg_agc *p_agc_if_settings = NULL;
4382 int rc;
4383 u16 ingain_tgt_max = 0;
4384 u16 clp_dir_to = 0;
4385 u16 sns_sum_max = 0;
4386 u16 clp_sum_max = 0;
4387 u16 sns_dir_to = 0;
4388 u16 ki_innergain_min = 0;
4389 u16 agc_ki = 0;
4390 u16 ki_max = 0;
4391 u16 if_iaccu_hi_tgt_min = 0;
4392 u16 data = 0;
4393 u16 agc_ki_dgain = 0;
4394 u16 ki_min = 0;
4395 u16 clp_ctrl_mode = 0;
4396 u16 agc_rf = 0;
4397 u16 agc_if = 0;
4398
4399 dev_addr = demod->my_i2c_dev_addr;
4400 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4401 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4402
4403 switch (ext_attr->standard) {
4404 case DRX_STANDARD_8VSB:
4405 clp_sum_max = 1023;
4406 clp_dir_to = (u16) (-9);
4407 sns_sum_max = 1023;
4408 sns_dir_to = (u16) (-9);
4409 ki_innergain_min = (u16) (-32768);
4410 ki_max = 0x032C;
4411 agc_ki_dgain = 0xC;
4412 if_iaccu_hi_tgt_min = 2047;
4413 ki_min = 0x0117;
4414 ingain_tgt_max = 16383;
4415 clp_ctrl_mode = 0;
4416 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4417 if (rc != 0) {
4418 pr_err("error %d\n", rc);
4419 goto rw_error;
4420 }
4421 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4422 if (rc != 0) {
4423 pr_err("error %d\n", rc);
4424 goto rw_error;
4425 }
4426 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4427 if (rc != 0) {
4428 pr_err("error %d\n", rc);
4429 goto rw_error;
4430 }
4431 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4432 if (rc != 0) {
4433 pr_err("error %d\n", rc);
4434 goto rw_error;
4435 }
4436 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4437 if (rc != 0) {
4438 pr_err("error %d\n", rc);
4439 goto rw_error;
4440 }
4441 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4442 if (rc != 0) {
4443 pr_err("error %d\n", rc);
4444 goto rw_error;
4445 }
4446 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4447 if (rc != 0) {
4448 pr_err("error %d\n", rc);
4449 goto rw_error;
4450 }
4451 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4452 if (rc != 0) {
4453 pr_err("error %d\n", rc);
4454 goto rw_error;
4455 }
4456 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4457 if (rc != 0) {
4458 pr_err("error %d\n", rc);
4459 goto rw_error;
4460 }
4461 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4462 if (rc != 0) {
4463 pr_err("error %d\n", rc);
4464 goto rw_error;
4465 }
4466 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4467 if (rc != 0) {
4468 pr_err("error %d\n", rc);
4469 goto rw_error;
4470 }
4471 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4472 if (rc != 0) {
4473 pr_err("error %d\n", rc);
4474 goto rw_error;
4475 }
4476 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4477 if (rc != 0) {
4478 pr_err("error %d\n", rc);
4479 goto rw_error;
4480 }
4481 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4482 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4483 break;
4484#ifndef DRXJ_VSB_ONLY
4485 case DRX_STANDARD_ITU_A:
4486 case DRX_STANDARD_ITU_C:
4487 case DRX_STANDARD_ITU_B:
4488 ingain_tgt_max = 5119;
4489 clp_sum_max = 1023;
4490 clp_dir_to = (u16) (-5);
4491 sns_sum_max = 127;
4492 sns_dir_to = (u16) (-3);
4493 ki_innergain_min = 0;
4494 ki_max = 0x0657;
4495 if_iaccu_hi_tgt_min = 2047;
4496 agc_ki_dgain = 0x7;
4497 ki_min = 0x0117;
4498 clp_ctrl_mode = 0;
4499 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4500 if (rc != 0) {
4501 pr_err("error %d\n", rc);
4502 goto rw_error;
4503 }
4504 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4505 if (rc != 0) {
4506 pr_err("error %d\n", rc);
4507 goto rw_error;
4508 }
4509 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4510 if (rc != 0) {
4511 pr_err("error %d\n", rc);
4512 goto rw_error;
4513 }
4514 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4515 if (rc != 0) {
4516 pr_err("error %d\n", rc);
4517 goto rw_error;
4518 }
4519 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4520 if (rc != 0) {
4521 pr_err("error %d\n", rc);
4522 goto rw_error;
4523 }
4524 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4525 if (rc != 0) {
4526 pr_err("error %d\n", rc);
4527 goto rw_error;
4528 }
4529 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4530 if (rc != 0) {
4531 pr_err("error %d\n", rc);
4532 goto rw_error;
4533 }
4534 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4535 if (rc != 0) {
4536 pr_err("error %d\n", rc);
4537 goto rw_error;
4538 }
4539 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4540 if (rc != 0) {
4541 pr_err("error %d\n", rc);
4542 goto rw_error;
4543 }
4544 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4545 if (rc != 0) {
4546 pr_err("error %d\n", rc);
4547 goto rw_error;
4548 }
4549 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4550 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4552 if (rc != 0) {
4553 pr_err("error %d\n", rc);
4554 goto rw_error;
4555 }
4556
4557 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4558 if (rc != 0) {
4559 pr_err("error %d\n", rc);
4560 goto rw_error;
4561 }
4562 agc_ki &= 0xf000;
4563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4564 if (rc != 0) {
4565 pr_err("error %d\n", rc);
4566 goto rw_error;
4567 }
4568 break;
4569#endif
4570 default:
4571 return -EINVAL;
4572 }
4573
4574
4575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4576 if (rc != 0) {
4577 pr_err("error %d\n", rc);
4578 goto rw_error;
4579 }
4580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4581 if (rc != 0) {
4582 pr_err("error %d\n", rc);
4583 goto rw_error;
4584 }
4585 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4586 if (rc != 0) {
4587 pr_err("error %d\n", rc);
4588 goto rw_error;
4589 }
4590 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4591 if (rc != 0) {
4592 pr_err("error %d\n", rc);
4593 goto rw_error;
4594 }
4595 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4596 if (rc != 0) {
4597 pr_err("error %d\n", rc);
4598 goto rw_error;
4599 }
4600 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4601 if (rc != 0) {
4602 pr_err("error %d\n", rc);
4603 goto rw_error;
4604 }
4605 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4606 if (rc != 0) {
4607 pr_err("error %d\n", rc);
4608 goto rw_error;
4609 }
4610 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4611 if (rc != 0) {
4612 pr_err("error %d\n", rc);
4613 goto rw_error;
4614 }
4615 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4616 if (rc != 0) {
4617 pr_err("error %d\n", rc);
4618 goto rw_error;
4619 }
4620 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4621 if (rc != 0) {
4622 pr_err("error %d\n", rc);
4623 goto rw_error;
4624 }
4625 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4626 if (rc != 0) {
4627 pr_err("error %d\n", rc);
4628 goto rw_error;
4629 }
4630 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4631 if (rc != 0) {
4632 pr_err("error %d\n", rc);
4633 goto rw_error;
4634 }
4635 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4636 if (rc != 0) {
4637 pr_err("error %d\n", rc);
4638 goto rw_error;
4639 }
4640 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4641 if (rc != 0) {
4642 pr_err("error %d\n", rc);
4643 goto rw_error;
4644 }
4645 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4646 if (rc != 0) {
4647 pr_err("error %d\n", rc);
4648 goto rw_error;
4649 }
4650 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4651 if (rc != 0) {
4652 pr_err("error %d\n", rc);
4653 goto rw_error;
4654 }
4655 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4656 if (rc != 0) {
4657 pr_err("error %d\n", rc);
4658 goto rw_error;
4659 }
4660 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4661 if (rc != 0) {
4662 pr_err("error %d\n", rc);
4663 goto rw_error;
4664 }
4665 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4666 if (rc != 0) {
4667 pr_err("error %d\n", rc);
4668 goto rw_error;
4669 }
4670 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4671 if (rc != 0) {
4672 pr_err("error %d\n", rc);
4673 goto rw_error;
4674 }
4675 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4676 if (rc != 0) {
4677 pr_err("error %d\n", rc);
4678 goto rw_error;
4679 }
4680 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4681 if (rc != 0) {
4682 pr_err("error %d\n", rc);
4683 goto rw_error;
4684 }
4685 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4686 if (rc != 0) {
4687 pr_err("error %d\n", rc);
4688 goto rw_error;
4689 }
4690 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4691 if (rc != 0) {
4692 pr_err("error %d\n", rc);
4693 goto rw_error;
4694 }
4695 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4696 if (rc != 0) {
4697 pr_err("error %d\n", rc);
4698 goto rw_error;
4699 }
4700 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4701 if (rc != 0) {
4702 pr_err("error %d\n", rc);
4703 goto rw_error;
4704 }
4705
4706 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
4707 if (common_attr->tuner_rf_agc_pol == true)
4708 agc_rf = 0x87ff - agc_rf;
4709
4710 agc_if = 0x800;
4711 if (common_attr->tuner_if_agc_pol == true)
4712 agc_rf = 0x87ff - agc_rf;
4713
4714 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4715 if (rc != 0) {
4716 pr_err("error %d\n", rc);
4717 goto rw_error;
4718 }
4719 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4720 if (rc != 0) {
4721 pr_err("error %d\n", rc);
4722 goto rw_error;
4723 }
4724
4725
4726 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4727 if (rc != 0) {
4728 pr_err("error %d\n", rc);
4729 goto rw_error;
4730 }
4731 data &= ~SCU_RAM_AGC_KI_DGAIN__M;
4732 data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
4733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4734 if (rc != 0) {
4735 pr_err("error %d\n", rc);
4736 goto rw_error;
4737 }
4738
4739 return 0;
4740rw_error:
4741 return rc;
4742}
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752static int
4753set_frequency(struct drx_demod_instance *demod,
4754 struct drx_channel *channel, s32 tuner_freq_offset)
4755{
4756 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
4757 struct drxj_data *ext_attr = demod->my_ext_attr;
4758 int rc;
4759 s32 sampling_frequency = 0;
4760 s32 frequency_shift = 0;
4761 s32 if_freq_actual = 0;
4762 s32 rf_freq_residual = -1 * tuner_freq_offset;
4763 s32 adc_freq = 0;
4764 s32 intermediate_freq = 0;
4765 u32 iqm_fs_rate_ofs = 0;
4766 bool adc_flip = true;
4767 bool select_pos_image = false;
4768 bool rf_mirror;
4769 bool tuner_mirror;
4770 bool image_to_select = true;
4771 s32 fm_frequency_shift = 0;
4772
4773 rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
4774 tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
4775
4776
4777
4778
4779 switch (ext_attr->standard) {
4780 case DRX_STANDARD_ITU_A:
4781 case DRX_STANDARD_ITU_C:
4782 case DRX_STANDARD_PAL_SECAM_LP:
4783 case DRX_STANDARD_8VSB:
4784 select_pos_image = true;
4785 break;
4786 case DRX_STANDARD_FM:
4787
4788
4789
4790 fm_frequency_shift = 1000;
4791
4792 case DRX_STANDARD_ITU_B:
4793 case DRX_STANDARD_NTSC:
4794 case DRX_STANDARD_PAL_SECAM_BG:
4795 case DRX_STANDARD_PAL_SECAM_DK:
4796 case DRX_STANDARD_PAL_SECAM_I:
4797 case DRX_STANDARD_PAL_SECAM_L:
4798 select_pos_image = false;
4799 break;
4800 default:
4801 return -EINVAL;
4802 }
4803 intermediate_freq = demod->my_common_attr->intermediate_freq;
4804 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
4805 if (tuner_mirror)
4806 if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
4807 else
4808 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
4809 if (if_freq_actual > sampling_frequency / 2) {
4810
4811 adc_freq = sampling_frequency - if_freq_actual;
4812 adc_flip = true;
4813 } else {
4814
4815 adc_freq = if_freq_actual;
4816 adc_flip = false;
4817 }
4818
4819 frequency_shift = adc_freq;
4820 image_to_select =
4821 (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
4822 iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
4823
4824 if (image_to_select)
4825 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
4826
4827
4828
4829 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4830 if (rc != 0) {
4831 pr_err("error %d\n", rc);
4832 goto rw_error;
4833 }
4834 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4835 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4836
4837 return 0;
4838rw_error:
4839 return rc;
4840}
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852#ifdef DRXJ_SIGNAL_ACCUM_ERR
4853static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
4854{
4855 int rc;
4856 static u16 pkt_err;
4857 static u16 last_pkt_err;
4858 u16 data = 0;
4859 struct drxj_data *ext_attr = NULL;
4860 struct i2c_device_addr *dev_addr = NULL;
4861
4862 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4863 dev_addr = demod->my_i2c_dev_addr;
4864
4865 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4866 if (rc != 0) {
4867 pr_err("error %d\n", rc);
4868 goto rw_error;
4869 }
4870 if (ext_attr->reset_pkt_err_acc) {
4871 last_pkt_err = data;
4872 pkt_err = 0;
4873 ext_attr->reset_pkt_err_acc = false;
4874 }
4875
4876 if (data < last_pkt_err) {
4877 pkt_err += 0xffff - last_pkt_err;
4878 pkt_err += data;
4879 } else {
4880 pkt_err += (data - last_pkt_err);
4881 }
4882 *packet_err = pkt_err;
4883 last_pkt_err = data;
4884
4885 return 0;
4886rw_error:
4887 return rc;
4888}
4889#endif
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901static int
4902set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
4903{
4904 struct i2c_device_addr *dev_addr = NULL;
4905 struct drxj_data *ext_attr = NULL;
4906 struct drxj_cfg_agc *p_agc_settings = NULL;
4907 struct drx_common_attr *common_attr = NULL;
4908 int rc;
4909 drx_write_reg16func_t scu_wr16 = NULL;
4910 drx_read_reg16func_t scu_rr16 = NULL;
4911
4912 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4913 dev_addr = demod->my_i2c_dev_addr;
4914 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4915
4916 if (atomic) {
4917 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
4918 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
4919 } else {
4920 scu_rr16 = drxj_dap_read_reg16;
4921 scu_wr16 = drxj_dap_write_reg16;
4922 }
4923
4924
4925 if ((ext_attr->standard == agc_settings->standard) ||
4926 (DRXJ_ISQAMSTD(ext_attr->standard) &&
4927 DRXJ_ISQAMSTD(agc_settings->standard)) ||
4928 (DRXJ_ISATVSTD(ext_attr->standard) &&
4929 DRXJ_ISATVSTD(agc_settings->standard))) {
4930 u16 data = 0;
4931
4932 switch (agc_settings->ctrl_mode) {
4933 case DRX_AGC_CTRL_AUTO:
4934
4935
4936 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4937 if (rc != 0) {
4938 pr_err("error %d\n", rc);
4939 goto rw_error;
4940 }
4941 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
4942 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4943 if (rc != 0) {
4944 pr_err("error %d\n", rc);
4945 goto rw_error;
4946 }
4947
4948
4949 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4950 if (rc != 0) {
4951 pr_err("error %d\n", rc);
4952 goto rw_error;
4953 }
4954 data &= ~SCU_RAM_AGC_KI_RF__M;
4955 if (ext_attr->standard == DRX_STANDARD_8VSB)
4956 data |= (2 << SCU_RAM_AGC_KI_RF__B);
4957 else if (DRXJ_ISQAMSTD(ext_attr->standard))
4958 data |= (5 << SCU_RAM_AGC_KI_RF__B);
4959 else
4960 data |= (4 << SCU_RAM_AGC_KI_RF__B);
4961
4962 if (common_attr->tuner_rf_agc_pol)
4963 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
4964 else
4965 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
4966 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4967 if (rc != 0) {
4968 pr_err("error %d\n", rc);
4969 goto rw_error;
4970 }
4971
4972
4973 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4974 if (rc != 0) {
4975 pr_err("error %d\n", rc);
4976 goto rw_error;
4977 }
4978 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
4979 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4980 if (rc != 0) {
4981 pr_err("error %d\n", rc);
4982 goto rw_error;
4983 }
4984
4985 if (agc_settings->standard == DRX_STANDARD_8VSB)
4986 p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4987 else if (DRXJ_ISQAMSTD(agc_settings->standard))
4988 p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4989 else if (DRXJ_ISATVSTD(agc_settings->standard))
4990 p_agc_settings = &(ext_attr->atv_if_agc_cfg);
4991 else
4992 return -EINVAL;
4993
4994
4995 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
4996 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
4997 if (rc != 0) {
4998 pr_err("error %d\n", rc);
4999 goto rw_error;
5000 }
5001 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5002 if (rc != 0) {
5003 pr_err("error %d\n", rc);
5004 goto rw_error;
5005 }
5006 }
5007
5008
5009 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5010 if (rc != 0) {
5011 pr_err("error %d\n", rc);
5012 goto rw_error;
5013 }
5014 break;
5015 case DRX_AGC_CTRL_USER:
5016
5017
5018 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5019 if (rc != 0) {
5020 pr_err("error %d\n", rc);
5021 goto rw_error;
5022 }
5023 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
5024 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5025 if (rc != 0) {
5026 pr_err("error %d\n", rc);
5027 goto rw_error;
5028 }
5029
5030
5031 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5032 if (rc != 0) {
5033 pr_err("error %d\n", rc);
5034 goto rw_error;
5035 }
5036 data &= ~SCU_RAM_AGC_KI_RF__M;
5037 if (common_attr->tuner_rf_agc_pol)
5038 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
5039 else
5040 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
5041 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5042 if (rc != 0) {
5043 pr_err("error %d\n", rc);
5044 goto rw_error;
5045 }
5046
5047
5048 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5049 if (rc != 0) {
5050 pr_err("error %d\n", rc);
5051 goto rw_error;
5052 }
5053 break;
5054 case DRX_AGC_CTRL_OFF:
5055
5056
5057 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5058 if (rc != 0) {
5059 pr_err("error %d\n", rc);
5060 goto rw_error;
5061 }
5062 data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5063 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5064 if (rc != 0) {
5065 pr_err("error %d\n", rc);
5066 goto rw_error;
5067 }
5068
5069
5070 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5071 if (rc != 0) {
5072 pr_err("error %d\n", rc);
5073 goto rw_error;
5074 }
5075 data &= ~SCU_RAM_AGC_KI_RF__M;
5076 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5077 if (rc != 0) {
5078 pr_err("error %d\n", rc);
5079 goto rw_error;
5080 }
5081 break;
5082 default:
5083 return -EINVAL;
5084 }
5085 }
5086
5087
5088 switch (agc_settings->standard) {
5089 case DRX_STANDARD_8VSB:
5090 ext_attr->vsb_rf_agc_cfg = *agc_settings;
5091 break;
5092#ifndef DRXJ_VSB_ONLY
5093 case DRX_STANDARD_ITU_A:
5094 case DRX_STANDARD_ITU_B:
5095 case DRX_STANDARD_ITU_C:
5096 ext_attr->qam_rf_agc_cfg = *agc_settings;
5097 break;
5098#endif
5099 default:
5100 return -EIO;
5101 }
5102
5103 return 0;
5104rw_error:
5105 return rc;
5106}
5107
5108
5109
5110
5111
5112
5113
5114
5115static int
5116set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
5117{
5118 struct i2c_device_addr *dev_addr = NULL;
5119 struct drxj_data *ext_attr = NULL;
5120 struct drxj_cfg_agc *p_agc_settings = NULL;
5121 struct drx_common_attr *common_attr = NULL;
5122 drx_write_reg16func_t scu_wr16 = NULL;
5123 drx_read_reg16func_t scu_rr16 = NULL;
5124 int rc;
5125
5126 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5127 dev_addr = demod->my_i2c_dev_addr;
5128 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5129
5130 if (atomic) {
5131 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
5132 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
5133 } else {
5134 scu_rr16 = drxj_dap_read_reg16;
5135 scu_wr16 = drxj_dap_write_reg16;
5136 }
5137
5138
5139 if ((ext_attr->standard == agc_settings->standard) ||
5140 (DRXJ_ISQAMSTD(ext_attr->standard) &&
5141 DRXJ_ISQAMSTD(agc_settings->standard)) ||
5142 (DRXJ_ISATVSTD(ext_attr->standard) &&
5143 DRXJ_ISATVSTD(agc_settings->standard))) {
5144 u16 data = 0;
5145
5146 switch (agc_settings->ctrl_mode) {
5147 case DRX_AGC_CTRL_AUTO:
5148
5149 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5150 if (rc != 0) {
5151 pr_err("error %d\n", rc);
5152 goto rw_error;
5153 }
5154 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5155 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5156 if (rc != 0) {
5157 pr_err("error %d\n", rc);
5158 goto rw_error;
5159 }
5160
5161
5162 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5163 if (rc != 0) {
5164 pr_err("error %d\n", rc);
5165 goto rw_error;
5166 }
5167 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5168 data &= ~SCU_RAM_AGC_KI_IF__M;
5169 if (ext_attr->standard == DRX_STANDARD_8VSB)
5170 data |= (3 << SCU_RAM_AGC_KI_IF__B);
5171 else if (DRXJ_ISQAMSTD(ext_attr->standard))
5172 data |= (6 << SCU_RAM_AGC_KI_IF__B);
5173 else
5174 data |= (5 << SCU_RAM_AGC_KI_IF__B);
5175
5176 if (common_attr->tuner_if_agc_pol)
5177 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5178 else
5179 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5180 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5181 if (rc != 0) {
5182 pr_err("error %d\n", rc);
5183 goto rw_error;
5184 }
5185
5186
5187 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5188 if (rc != 0) {
5189 pr_err("error %d\n", rc);
5190 goto rw_error;
5191 }
5192 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
5193 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5194 if (rc != 0) {
5195 pr_err("error %d\n", rc);
5196 goto rw_error;
5197 }
5198
5199 if (agc_settings->standard == DRX_STANDARD_8VSB)
5200 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5201 else if (DRXJ_ISQAMSTD(agc_settings->standard))
5202 p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5203 else if (DRXJ_ISATVSTD(agc_settings->standard))
5204 p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5205 else
5206 return -EINVAL;
5207
5208
5209 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5210 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5211 if (rc != 0) {
5212 pr_err("error %d\n", rc);
5213 goto rw_error;
5214 }
5215 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5216 if (rc != 0) {
5217 pr_err("error %d\n", rc);
5218 goto rw_error;
5219 }
5220 } else {
5221 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5222 if (rc != 0) {
5223 pr_err("error %d\n", rc);
5224 goto rw_error;
5225 }
5226 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5227 if (rc != 0) {
5228 pr_err("error %d\n", rc);
5229 goto rw_error;
5230 }
5231 }
5232 break;
5233
5234 case DRX_AGC_CTRL_USER:
5235
5236
5237 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5238 if (rc != 0) {
5239 pr_err("error %d\n", rc);
5240 goto rw_error;
5241 }
5242 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5243 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5244 if (rc != 0) {
5245 pr_err("error %d\n", rc);
5246 goto rw_error;
5247 }
5248
5249
5250 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5251 if (rc != 0) {
5252 pr_err("error %d\n", rc);
5253 goto rw_error;
5254 }
5255 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5256 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5257 if (common_attr->tuner_if_agc_pol)
5258 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5259 else
5260 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5261 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5262 if (rc != 0) {
5263 pr_err("error %d\n", rc);
5264 goto rw_error;
5265 }
5266
5267
5268 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5269 if (rc != 0) {
5270 pr_err("error %d\n", rc);
5271 goto rw_error;
5272 }
5273 break;
5274
5275 case DRX_AGC_CTRL_OFF:
5276
5277
5278 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5279 if (rc != 0) {
5280 pr_err("error %d\n", rc);
5281 goto rw_error;
5282 }
5283 data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
5284 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5285 if (rc != 0) {
5286 pr_err("error %d\n", rc);
5287 goto rw_error;
5288 }
5289
5290
5291 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5292 if (rc != 0) {
5293 pr_err("error %d\n", rc);
5294 goto rw_error;
5295 }
5296 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5297 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5298 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5299 if (rc != 0) {
5300 pr_err("error %d\n", rc);
5301 goto rw_error;
5302 }
5303 break;
5304 default:
5305 return -EINVAL;
5306 }
5307
5308
5309 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5310 if (rc != 0) {
5311 pr_err("error %d\n", rc);
5312 goto rw_error;
5313 }
5314 }
5315
5316
5317 switch (agc_settings->standard) {
5318 case DRX_STANDARD_8VSB:
5319 ext_attr->vsb_if_agc_cfg = *agc_settings;
5320 break;
5321#ifndef DRXJ_VSB_ONLY
5322 case DRX_STANDARD_ITU_A:
5323 case DRX_STANDARD_ITU_B:
5324 case DRX_STANDARD_ITU_C:
5325 ext_attr->qam_if_agc_cfg = *agc_settings;
5326 break;
5327#endif
5328 default:
5329 return -EIO;
5330 }
5331
5332 return 0;
5333rw_error:
5334 return rc;
5335}
5336
5337
5338
5339
5340
5341
5342
5343
5344static int set_iqm_af(struct drx_demod_instance *demod, bool active)
5345{
5346 u16 data = 0;
5347 struct i2c_device_addr *dev_addr = NULL;
5348 int rc;
5349
5350 dev_addr = demod->my_i2c_dev_addr;
5351
5352
5353 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5354 if (rc != 0) {
5355 pr_err("error %d\n", rc);
5356 goto rw_error;
5357 }
5358 if (!active)
5359 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
5360 else
5361 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5362 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5363 if (rc != 0) {
5364 pr_err("error %d\n", rc);
5365 goto rw_error;
5366 }
5367
5368 return 0;
5369rw_error:
5370 return rc;
5371}
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
5391{
5392 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
5393 struct drxjscu_cmd cmd_scu = { 0,
5394 0,
5395 0,
5396 NULL,
5397 NULL
5398 };
5399 struct drx_cfg_mpeg_output cfg_mpeg_output;
5400 int rc;
5401 u16 cmd_result = 0;
5402
5403
5404
5405
5406
5407 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
5408 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
5409 cmd_scu.parameter_len = 0;
5410 cmd_scu.result_len = 1;
5411 cmd_scu.parameter = NULL;
5412 cmd_scu.result = &cmd_result;
5413 rc = scu_command(dev_addr, &cmd_scu);
5414 if (rc != 0) {
5415 pr_err("error %d\n", rc);
5416 goto rw_error;
5417 }
5418
5419
5420 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5421 if (rc != 0) {
5422 pr_err("error %d\n", rc);
5423 goto rw_error;
5424 }
5425 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5426 if (rc != 0) {
5427 pr_err("error %d\n", rc);
5428 goto rw_error;
5429 }
5430 if (primary) {
5431 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5432 if (rc != 0) {
5433 pr_err("error %d\n", rc);
5434 goto rw_error;
5435 }
5436 rc = set_iqm_af(demod, false);
5437 if (rc != 0) {
5438 pr_err("error %d\n", rc);
5439 goto rw_error;
5440 }
5441 } else {
5442 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5443 if (rc != 0) {
5444 pr_err("error %d\n", rc);
5445 goto rw_error;
5446 }
5447 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5448 if (rc != 0) {
5449 pr_err("error %d\n", rc);
5450 goto rw_error;
5451 }
5452 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5453 if (rc != 0) {
5454 pr_err("error %d\n", rc);
5455 goto rw_error;
5456 }
5457 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5458 if (rc != 0) {
5459 pr_err("error %d\n", rc);
5460 goto rw_error;
5461 }
5462 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5463 if (rc != 0) {
5464 pr_err("error %d\n", rc);
5465 goto rw_error;
5466 }
5467 }
5468
5469 cfg_mpeg_output.enable_mpeg_output = false;
5470 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5471 if (rc != 0) {
5472 pr_err("error %d\n", rc);
5473 goto rw_error;
5474 }
5475
5476 return 0;
5477rw_error:
5478 return rc;
5479}
5480
5481
5482
5483
5484
5485
5486
5487static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
5488{
5489 struct i2c_device_addr *dev_addr = NULL;
5490 int rc;
5491
5492 const u8 vsb_ffe_leak_gain_ram0[] = {
5493 DRXJ_16TO8(0x8),
5494 DRXJ_16TO8(0x8),
5495 DRXJ_16TO8(0x8),
5496 DRXJ_16TO8(0xf),
5497 DRXJ_16TO8(0xf),
5498 DRXJ_16TO8(0xf),
5499 DRXJ_16TO8(0xf),
5500 DRXJ_16TO8(0xf),
5501 DRXJ_16TO8(0xf),
5502 DRXJ_16TO8(0x8),
5503 DRXJ_16TO8(0x8),
5504 DRXJ_16TO8(0x8),
5505 DRXJ_16TO8(0x10),
5506 DRXJ_16TO8(0x10),
5507 DRXJ_16TO8(0x10),
5508 DRXJ_16TO8(0x20),
5509 DRXJ_16TO8(0x20),
5510 DRXJ_16TO8(0x20),
5511 DRXJ_16TO8(0x20),
5512 DRXJ_16TO8(0x20),
5513 DRXJ_16TO8(0x20),
5514 DRXJ_16TO8(0x10),
5515 DRXJ_16TO8(0x10),
5516 DRXJ_16TO8(0x10),
5517 DRXJ_16TO8(0x10),
5518 DRXJ_16TO8(0x10),
5519 DRXJ_16TO8(0x10),
5520 DRXJ_16TO8(0x20),
5521 DRXJ_16TO8(0x20),
5522 DRXJ_16TO8(0x20),
5523 DRXJ_16TO8(0x20),
5524 DRXJ_16TO8(0x20),
5525 DRXJ_16TO8(0x20),
5526 DRXJ_16TO8(0x10),
5527 DRXJ_16TO8(0x10),
5528 DRXJ_16TO8(0x10),
5529 DRXJ_16TO8(0x10),
5530 DRXJ_16TO8(0x10),
5531 DRXJ_16TO8(0x10),
5532 DRXJ_16TO8(0x20),
5533 DRXJ_16TO8(0x20),
5534 DRXJ_16TO8(0x20),
5535 DRXJ_16TO8(0x20),
5536 DRXJ_16TO8(0x20),
5537 DRXJ_16TO8(0x20),
5538 DRXJ_16TO8(0x10),
5539 DRXJ_16TO8(0x10),
5540 DRXJ_16TO8(0x10),
5541 DRXJ_16TO8(0x10),
5542 DRXJ_16TO8(0x10),
5543 DRXJ_16TO8(0x10),
5544 DRXJ_16TO8(0x20),
5545 DRXJ_16TO8(0x20),
5546 DRXJ_16TO8(0x20),
5547 DRXJ_16TO8(0x20),
5548 DRXJ_16TO8(0x20),
5549 DRXJ_16TO8(0x20),
5550 DRXJ_16TO8(0x10),
5551 DRXJ_16TO8(0x10),
5552 DRXJ_16TO8(0x10),
5553 DRXJ_16TO8(0x07),
5554 DRXJ_16TO8(0x07),
5555 DRXJ_16TO8(0x07),
5556 DRXJ_16TO8(0x0e),
5557 DRXJ_16TO8(0x0e),
5558 DRXJ_16TO8(0x0e),
5559 DRXJ_16TO8(0x0e),
5560 DRXJ_16TO8(0x0e),
5561 DRXJ_16TO8(0x0e),
5562 DRXJ_16TO8(0x07),
5563 DRXJ_16TO8(0x07),
5564 DRXJ_16TO8(0x07),
5565 DRXJ_16TO8(0x07),
5566 DRXJ_16TO8(0x07),
5567 DRXJ_16TO8(0x07),
5568 DRXJ_16TO8(0x0e),
5569 DRXJ_16TO8(0x0e),
5570 DRXJ_16TO8(0x0e),
5571 DRXJ_16TO8(0x0e),
5572 DRXJ_16TO8(0x0e),
5573 DRXJ_16TO8(0x0e),
5574 DRXJ_16TO8(0x07),
5575 DRXJ_16TO8(0x07),
5576 DRXJ_16TO8(0x07),
5577 DRXJ_16TO8(0x06),
5578 DRXJ_16TO8(0x06),
5579 DRXJ_16TO8(0x06),
5580 DRXJ_16TO8(0x0c),
5581 DRXJ_16TO8(0x0c),
5582 DRXJ_16TO8(0x0c),
5583 DRXJ_16TO8(0x0c),
5584 DRXJ_16TO8(0x0c),
5585 DRXJ_16TO8(0x0c),
5586 DRXJ_16TO8(0x06),
5587 DRXJ_16TO8(0x06),
5588 DRXJ_16TO8(0x06),
5589 DRXJ_16TO8(0x06),
5590 DRXJ_16TO8(0x06),
5591 DRXJ_16TO8(0x06),
5592 DRXJ_16TO8(0x0c),
5593 DRXJ_16TO8(0x0c),
5594 DRXJ_16TO8(0x0c),
5595 DRXJ_16TO8(0x0c),
5596 DRXJ_16TO8(0x0c),
5597 DRXJ_16TO8(0x0c),
5598 DRXJ_16TO8(0x06),
5599 DRXJ_16TO8(0x06),
5600 DRXJ_16TO8(0x06),
5601 DRXJ_16TO8(0x2020),
5602 DRXJ_16TO8(0x2020),
5603 DRXJ_16TO8(0x2020),
5604 DRXJ_16TO8(0x4040),
5605 DRXJ_16TO8(0x4040),
5606 DRXJ_16TO8(0x4040),
5607 DRXJ_16TO8(0x4040),
5608 DRXJ_16TO8(0x4040),
5609 DRXJ_16TO8(0x4040),
5610 DRXJ_16TO8(0x2020),
5611 DRXJ_16TO8(0x2020),
5612 DRXJ_16TO8(0x2020),
5613 DRXJ_16TO8(0x0808),
5614 DRXJ_16TO8(0x0808),
5615 DRXJ_16TO8(0x0808),
5616 DRXJ_16TO8(0x1010),
5617 DRXJ_16TO8(0x1010),
5618 DRXJ_16TO8(0x1010),
5619 DRXJ_16TO8(0x1010),
5620 DRXJ_16TO8(0x1010)
5621 };
5622
5623 const u8 vsb_ffe_leak_gain_ram1[] = {
5624 DRXJ_16TO8(0x1010),
5625 DRXJ_16TO8(0x0808),
5626 DRXJ_16TO8(0x0808),
5627 DRXJ_16TO8(0x0808),
5628 DRXJ_16TO8(0x0808),
5629 DRXJ_16TO8(0x0808),
5630 DRXJ_16TO8(0x0808),
5631 DRXJ_16TO8(0x1010),
5632 DRXJ_16TO8(0x1010),
5633 DRXJ_16TO8(0x1010),
5634 DRXJ_16TO8(0x1010),
5635 DRXJ_16TO8(0x1010),
5636 DRXJ_16TO8(0x1010),
5637 DRXJ_16TO8(0x0808),
5638 DRXJ_16TO8(0x0808),
5639 DRXJ_16TO8(0x0808),
5640 DRXJ_16TO8(0x0303),
5641 DRXJ_16TO8(0x0303),
5642 DRXJ_16TO8(0x0303),
5643 DRXJ_16TO8(0x0606),
5644 DRXJ_16TO8(0x0606),
5645 DRXJ_16TO8(0x0606),
5646 DRXJ_16TO8(0x0606),
5647 DRXJ_16TO8(0x0606),
5648 DRXJ_16TO8(0x0606),
5649 DRXJ_16TO8(0x0303),
5650 DRXJ_16TO8(0x0303),
5651 DRXJ_16TO8(0x0303),
5652 DRXJ_16TO8(0x0303),
5653 DRXJ_16TO8(0x0303),
5654 DRXJ_16TO8(0x0303),
5655 DRXJ_16TO8(0x0505),
5656 DRXJ_16TO8(0x0505),
5657 DRXJ_16TO8(0x0505),
5658 DRXJ_16TO8(0x0505),
5659 DRXJ_16TO8(0x0505),
5660 DRXJ_16TO8(0x0505),
5661 DRXJ_16TO8(0x0303),
5662 DRXJ_16TO8(0x0303),
5663 DRXJ_16TO8(0x0303),
5664 DRXJ_16TO8(0x001f),
5665 DRXJ_16TO8(0x01ff),
5666 DRXJ_16TO8(0x01ff),
5667 DRXJ_16TO8(0x004f),
5668 DRXJ_16TO8(0x004f),
5669 DRXJ_16TO8(0x01ff),
5670 DRXJ_16TO8(0x01ff),
5671 DRXJ_16TO8(0x0352),
5672 DRXJ_16TO8(0x0352),
5673 DRXJ_16TO8(0x0000),
5674 DRXJ_16TO8(0x2020),
5675 DRXJ_16TO8(0x1010),
5676 DRXJ_16TO8(0x1818),
5677 DRXJ_16TO8(0x1212)
5678 };
5679
5680 dev_addr = demod->my_i2c_dev_addr;
5681 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5682 if (rc != 0) {
5683 pr_err("error %d\n", rc);
5684 goto rw_error;
5685 }
5686 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5687 if (rc != 0) {
5688 pr_err("error %d\n", rc);
5689 goto rw_error;
5690 }
5691
5692 return 0;
5693rw_error:
5694 return rc;
5695}
5696
5697
5698
5699
5700
5701
5702
5703
5704static int set_vsb(struct drx_demod_instance *demod)
5705{
5706 struct i2c_device_addr *dev_addr = NULL;
5707 int rc;
5708 struct drx_common_attr *common_attr = NULL;
5709 struct drxjscu_cmd cmd_scu;
5710 struct drxj_data *ext_attr = NULL;
5711 u16 cmd_result = 0;
5712 u16 cmd_param = 0;
5713 const u8 vsb_taps_re[] = {
5714 DRXJ_16TO8(-2),
5715 DRXJ_16TO8(4),
5716 DRXJ_16TO8(1),
5717 DRXJ_16TO8(-4),
5718 DRXJ_16TO8(1),
5719 DRXJ_16TO8(4),
5720 DRXJ_16TO8(-3),
5721 DRXJ_16TO8(-3),
5722 DRXJ_16TO8(6),
5723 DRXJ_16TO8(1),
5724 DRXJ_16TO8(-9),
5725 DRXJ_16TO8(3),
5726 DRXJ_16TO8(12),
5727 DRXJ_16TO8(-9),
5728 DRXJ_16TO8(-15),
5729 DRXJ_16TO8(17),
5730 DRXJ_16TO8(19),
5731 DRXJ_16TO8(-29),
5732 DRXJ_16TO8(-22),
5733 DRXJ_16TO8(45),
5734 DRXJ_16TO8(25),
5735 DRXJ_16TO8(-70),
5736 DRXJ_16TO8(-28),
5737 DRXJ_16TO8(111),
5738 DRXJ_16TO8(30),
5739 DRXJ_16TO8(-201),
5740 DRXJ_16TO8(-31),
5741 DRXJ_16TO8(629)
5742 };
5743
5744 dev_addr = demod->my_i2c_dev_addr;
5745 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5746 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5747
5748
5749 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5750 if (rc != 0) {
5751 pr_err("error %d\n", rc);
5752 goto rw_error;
5753 }
5754 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5755 if (rc != 0) {
5756 pr_err("error %d\n", rc);
5757 goto rw_error;
5758 }
5759 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5760 if (rc != 0) {
5761 pr_err("error %d\n", rc);
5762 goto rw_error;
5763 }
5764 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5765 if (rc != 0) {
5766 pr_err("error %d\n", rc);
5767 goto rw_error;
5768 }
5769 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5770 if (rc != 0) {
5771 pr_err("error %d\n", rc);
5772 goto rw_error;
5773 }
5774 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5775 if (rc != 0) {
5776 pr_err("error %d\n", rc);
5777 goto rw_error;
5778 }
5779 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5780 if (rc != 0) {
5781 pr_err("error %d\n", rc);
5782 goto rw_error;
5783 }
5784
5785
5786 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
5787 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
5788 cmd_scu.parameter_len = 0;
5789 cmd_scu.result_len = 1;
5790 cmd_scu.parameter = NULL;
5791 cmd_scu.result = &cmd_result;
5792 rc = scu_command(dev_addr, &cmd_scu);
5793 if (rc != 0) {
5794 pr_err("error %d\n", rc);
5795 goto rw_error;
5796 }
5797
5798 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5799 if (rc != 0) {
5800 pr_err("error %d\n", rc);
5801 goto rw_error;
5802 }
5803 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5804 if (rc != 0) {
5805 pr_err("error %d\n", rc);
5806 goto rw_error;
5807 }
5808 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5809 if (rc != 0) {
5810 pr_err("error %d\n", rc);
5811 goto rw_error;
5812 }
5813 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5814 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5815 if (rc != 0) {
5816 pr_err("error %d\n", rc);
5817 goto rw_error;
5818 }
5819 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5820 if (rc != 0) {
5821 pr_err("error %d\n", rc);
5822 goto rw_error;
5823 }
5824 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5825 if (rc != 0) {
5826 pr_err("error %d\n", rc);
5827 goto rw_error;
5828 }
5829
5830 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5831 if (rc != 0) {
5832 pr_err("error %d\n", rc);
5833 goto rw_error;
5834 }
5835 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5836 if (rc != 0) {
5837 pr_err("error %d\n", rc);
5838 goto rw_error;
5839 }
5840 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5841 if (rc != 0) {
5842 pr_err("error %d\n", rc);
5843 goto rw_error;
5844 }
5845 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5846 if (rc != 0) {
5847 pr_err("error %d\n", rc);
5848 goto rw_error;
5849 }
5850 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5851 if (rc != 0) {
5852 pr_err("error %d\n", rc);
5853 goto rw_error;
5854 }
5855 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5856 if (rc != 0) {
5857 pr_err("error %d\n", rc);
5858 goto rw_error;
5859 }
5860 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5861 if (rc != 0) {
5862 pr_err("error %d\n", rc);
5863 goto rw_error;
5864 }
5865 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5866 if (rc != 0) {
5867 pr_err("error %d\n", rc);
5868 goto rw_error;
5869 }
5870 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5871 if (rc != 0) {
5872 pr_err("error %d\n", rc);
5873 goto rw_error;
5874 }
5875
5876 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5877 if (rc != 0) {
5878 pr_err("error %d\n", rc);
5879 goto rw_error;
5880 }
5881 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5882 if (rc != 0) {
5883 pr_err("error %d\n", rc);
5884 goto rw_error;
5885 }
5886
5887 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5888 if (rc != 0) {
5889 pr_err("error %d\n", rc);
5890 goto rw_error;
5891 }
5892 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5893 if (rc != 0) {
5894 pr_err("error %d\n", rc);
5895 goto rw_error;
5896 }
5897 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5898 if (rc != 0) {
5899 pr_err("error %d\n", rc);
5900 goto rw_error;
5901 }
5902 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5903 if (rc != 0) {
5904 pr_err("error %d\n", rc);
5905 goto rw_error;
5906 }
5907 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5908 if (rc != 0) {
5909 pr_err("error %d\n", rc);
5910 goto rw_error;
5911 }
5912 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5913 if (rc != 0) {
5914 pr_err("error %d\n", rc);
5915 goto rw_error;
5916 }
5917
5918
5919 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5920 if (rc != 0) {
5921 pr_err("error %d\n", rc);
5922 goto rw_error;
5923 }
5924 {
5925 u16 fec_oc_snc_mode = 0;
5926 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5927 if (rc != 0) {
5928 pr_err("error %d\n", rc);
5929 goto rw_error;
5930 }
5931
5932 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5933 if (rc != 0) {
5934 pr_err("error %d\n", rc);
5935 goto rw_error;
5936 }
5937 }
5938
5939
5940 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5941 if (rc != 0) {
5942 pr_err("error %d\n", rc);
5943 goto rw_error;
5944 }
5945 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5946 if (rc != 0) {
5947 pr_err("error %d\n", rc);
5948 goto rw_error;
5949 }
5950 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5951 if (rc != 0) {
5952 pr_err("error %d\n", rc);
5953 goto rw_error;
5954 }
5955 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5956 if (rc != 0) {
5957 pr_err("error %d\n", rc);
5958 goto rw_error;
5959 }
5960
5961 {
5962 u16 fec_oc_reg_mode = 0;
5963 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5964 if (rc != 0) {
5965 pr_err("error %d\n", rc);
5966 goto rw_error;
5967 }
5968 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5969 if (rc != 0) {
5970 pr_err("error %d\n", rc);
5971 goto rw_error;
5972 }
5973 }
5974
5975 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5976 if (rc != 0) {
5977 pr_err("error %d\n", rc);
5978 goto rw_error;
5979 }
5980 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5981 if (rc != 0) {
5982 pr_err("error %d\n", rc);
5983 goto rw_error;
5984 }
5985 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5986 if (rc != 0) {
5987 pr_err("error %d\n", rc);
5988 goto rw_error;
5989 }
5990
5991 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
5992 if (rc != 0) {
5993 pr_err("error %d\n", rc);
5994 goto rw_error;
5995 }
5996 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
5997 if (rc != 0) {
5998 pr_err("error %d\n", rc);
5999 goto rw_error;
6000 }
6001
6002
6003 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
6004 if (rc != 0) {
6005 pr_err("error %d\n", rc);
6006 goto rw_error;
6007 }
6008 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6009 if (rc != 0) {
6010 pr_err("error %d\n", rc);
6011 goto rw_error;
6012 }
6013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6014 if (rc != 0) {
6015 pr_err("error %d\n", rc);
6016 goto rw_error;
6017 }
6018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6019 if (rc != 0) {
6020 pr_err("error %d\n", rc);
6021 goto rw_error;
6022 }
6023
6024 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6025 if (rc != 0) {
6026 pr_err("error %d\n", rc);
6027 goto rw_error;
6028 }
6029
6030 if (!ext_attr->has_lna) {
6031 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6032 if (rc != 0) {
6033 pr_err("error %d\n", rc);
6034 goto rw_error;
6035 }
6036 }
6037
6038
6039 rc = set_iqm_af(demod, true);
6040 if (rc != 0) {
6041 pr_err("error %d\n", rc);
6042 goto rw_error;
6043 }
6044 rc = adc_synchronization(demod);
6045 if (rc != 0) {
6046 pr_err("error %d\n", rc);
6047 goto rw_error;
6048 }
6049
6050 rc = init_agc(demod);
6051 if (rc != 0) {
6052 pr_err("error %d\n", rc);
6053 goto rw_error;
6054 }
6055 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6056 if (rc != 0) {
6057 pr_err("error %d\n", rc);
6058 goto rw_error;
6059 }
6060 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6061 if (rc != 0) {
6062 pr_err("error %d\n", rc);
6063 goto rw_error;
6064 }
6065 {
6066
6067
6068 struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
6069
6070 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6071 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6072 if (rc != 0) {
6073 pr_err("error %d\n", rc);
6074 goto rw_error;
6075 }
6076 }
6077 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6078 if (rc != 0) {
6079 pr_err("error %d\n", rc);
6080 goto rw_error;
6081 }
6082
6083
6084 rc = set_mpegtei_handling(demod);
6085 if (rc != 0) {
6086 pr_err("error %d\n", rc);
6087 goto rw_error;
6088 }
6089 rc = bit_reverse_mpeg_output(demod);
6090 if (rc != 0) {
6091 pr_err("error %d\n", rc);
6092 goto rw_error;
6093 }
6094 rc = set_mpeg_start_width(demod);
6095 if (rc != 0) {
6096 pr_err("error %d\n", rc);
6097 goto rw_error;
6098 }
6099 {
6100
6101
6102 struct drx_cfg_mpeg_output cfg_mpeg_output;
6103
6104 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6105 cfg_mpeg_output.enable_mpeg_output = true;
6106
6107 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6108 if (rc != 0) {
6109 pr_err("error %d\n", rc);
6110 goto rw_error;
6111 }
6112 }
6113
6114
6115 cmd_param = 0x00;
6116 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6117 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
6118 cmd_scu.parameter_len = 1;
6119 cmd_scu.result_len = 1;
6120 cmd_scu.parameter = &cmd_param;
6121 cmd_scu.result = &cmd_result;
6122 rc = scu_command(dev_addr, &cmd_scu);
6123 if (rc != 0) {
6124 pr_err("error %d\n", rc);
6125 goto rw_error;
6126 }
6127
6128 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6129 if (rc != 0) {
6130 pr_err("error %d\n", rc);
6131 goto rw_error;
6132 }
6133 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6134 if (rc != 0) {
6135 pr_err("error %d\n", rc);
6136 goto rw_error;
6137 }
6138 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6139 if (rc != 0) {
6140 pr_err("error %d\n", rc);
6141 goto rw_error;
6142 }
6143 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6144 if (rc != 0) {
6145 pr_err("error %d\n", rc);
6146 goto rw_error;
6147 }
6148 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6149 if (rc != 0) {
6150 pr_err("error %d\n", rc);
6151 goto rw_error;
6152 }
6153 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6154 if (rc != 0) {
6155 pr_err("error %d\n", rc);
6156 goto rw_error;
6157 }
6158 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6159 if (rc != 0) {
6160 pr_err("error %d\n", rc);
6161 goto rw_error;
6162 }
6163 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6164 if (rc != 0) {
6165 pr_err("error %d\n", rc);
6166 goto rw_error;
6167 }
6168
6169
6170 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6171 | SCU_RAM_COMMAND_CMD_DEMOD_START;
6172 cmd_scu.parameter_len = 0;
6173 cmd_scu.result_len = 1;
6174 cmd_scu.parameter = NULL;
6175 cmd_scu.result = &cmd_result;
6176 rc = scu_command(dev_addr, &cmd_scu);
6177 if (rc != 0) {
6178 pr_err("error %d\n", rc);
6179 goto rw_error;
6180 }
6181
6182 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6183 if (rc != 0) {
6184 pr_err("error %d\n", rc);
6185 goto rw_error;
6186 }
6187 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6188 if (rc != 0) {
6189 pr_err("error %d\n", rc);
6190 goto rw_error;
6191 }
6192 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6193 if (rc != 0) {
6194 pr_err("error %d\n", rc);
6195 goto rw_error;
6196 }
6197
6198 return 0;
6199rw_error:
6200 return rc;
6201}
6202
6203
6204
6205
6206
6207
6208static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
6209 u32 *pck_errs, u32 *pck_count)
6210{
6211 int rc;
6212 u16 data = 0;
6213 u16 period = 0;
6214 u16 prescale = 0;
6215 u16 packet_errors_mant = 0;
6216 u16 packet_errors_exp = 0;
6217
6218 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6219 if (rc != 0) {
6220 pr_err("error %d\n", rc);
6221 goto rw_error;
6222 }
6223 packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
6224 packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
6225 >> FEC_RS_NR_FAILURES_EXP__B;
6226 period = FEC_RS_MEASUREMENT_PERIOD;
6227 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6228
6229
6230 if (period * prescale == 0) {
6231 pr_err("error: period and/or prescale is zero!\n");
6232 return -EIO;
6233 }
6234 *pck_errs = packet_errors_mant * (1 << packet_errors_exp);
6235 *pck_count = period * prescale * 77;
6236
6237 return 0;
6238rw_error:
6239 return rc;
6240}
6241
6242
6243
6244
6245
6246
6247static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
6248 u32 *ber, u32 *cnt)
6249{
6250 int rc;
6251 u16 data = 0;
6252 u16 period = 0;
6253 u16 prescale = 0;
6254 u16 bit_errors_mant = 0;
6255 u16 bit_errors_exp = 0;
6256
6257 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6258 if (rc != 0) {
6259 pr_err("error %d\n", rc);
6260 goto rw_error;
6261 }
6262 period = FEC_RS_MEASUREMENT_PERIOD;
6263 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6264
6265 bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
6266 bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
6267 >> FEC_RS_NR_BIT_ERRORS_EXP__B;
6268
6269 *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
6270
6271 if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
6272 *ber = (*cnt) * 26570;
6273 else {
6274 if (period * prescale == 0) {
6275 pr_err("error: period and/or prescale is zero!\n");
6276 return -EIO;
6277 }
6278 *ber = bit_errors_mant << ((bit_errors_exp > 2) ?
6279 (bit_errors_exp - 3) : bit_errors_exp);
6280 }
6281
6282 return 0;
6283rw_error:
6284 return rc;
6285}
6286
6287
6288
6289
6290
6291
6292static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
6293 u32 *ber, u32 *cnt)
6294{
6295 u16 data = 0;
6296 int rc;
6297
6298 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6299 if (rc != 0) {
6300 pr_err("error %d\n", rc);
6301 return -EIO;
6302 }
6303 *ber = data;
6304 *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
6305
6306 return 0;
6307}
6308
6309
6310
6311
6312
6313
6314static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6315{
6316 int rc;
6317 u16 data_hi = 0;
6318
6319 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6320 if (rc != 0) {
6321 pr_err("error %d\n", rc);
6322 goto rw_error;
6323 }
6324 *mer =
6325 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
6326
6327 return 0;
6328rw_error:
6329 return rc;
6330}
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350static int power_down_qam(struct drx_demod_instance *demod, bool primary)
6351{
6352 struct drxjscu_cmd cmd_scu = { 0,
6353 0,
6354 0,
6355 NULL,
6356 NULL
6357 };
6358 int rc;
6359 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6360 struct drx_cfg_mpeg_output cfg_mpeg_output;
6361 struct drx_common_attr *common_attr = demod->my_common_attr;
6362 u16 cmd_result = 0;
6363
6364
6365
6366
6367
6368
6369 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6370 if (rc != 0) {
6371 pr_err("error %d\n", rc);
6372 goto rw_error;
6373 }
6374 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6375 if (rc != 0) {
6376 pr_err("error %d\n", rc);
6377 goto rw_error;
6378 }
6379
6380 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
6381 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
6382 cmd_scu.parameter_len = 0;
6383 cmd_scu.result_len = 1;
6384 cmd_scu.parameter = NULL;
6385 cmd_scu.result = &cmd_result;
6386 rc = scu_command(dev_addr, &cmd_scu);
6387 if (rc != 0) {
6388 pr_err("error %d\n", rc);
6389 goto rw_error;
6390 }
6391
6392 if (primary) {
6393 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6394 if (rc != 0) {
6395 pr_err("error %d\n", rc);
6396 goto rw_error;
6397 }
6398 rc = set_iqm_af(demod, false);
6399 if (rc != 0) {
6400 pr_err("error %d\n", rc);
6401 goto rw_error;
6402 }
6403 } else {
6404 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6405 if (rc != 0) {
6406 pr_err("error %d\n", rc);
6407 goto rw_error;
6408 }
6409 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6410 if (rc != 0) {
6411 pr_err("error %d\n", rc);
6412 goto rw_error;
6413 }
6414 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6415 if (rc != 0) {
6416 pr_err("error %d\n", rc);
6417 goto rw_error;
6418 }
6419 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6420 if (rc != 0) {
6421 pr_err("error %d\n", rc);
6422 goto rw_error;
6423 }
6424 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6425 if (rc != 0) {
6426 pr_err("error %d\n", rc);
6427 goto rw_error;
6428 }
6429 }
6430
6431 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6432 cfg_mpeg_output.enable_mpeg_output = false;
6433
6434 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6435 if (rc != 0) {
6436 pr_err("error %d\n", rc);
6437 goto rw_error;
6438 }
6439
6440 return 0;
6441rw_error:
6442 return rc;
6443}
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463#ifndef DRXJ_VSB_ONLY
6464static int
6465set_qam_measurement(struct drx_demod_instance *demod,
6466 enum drx_modulation constellation, u32 symbol_rate)
6467{
6468 struct i2c_device_addr *dev_addr = NULL;
6469 struct drxj_data *ext_attr = NULL;
6470 int rc;
6471 u32 fec_bits_desired = 0;
6472 u16 fec_rs_plen = 0;
6473 u16 fec_rs_prescale = 0;
6474 u32 fec_rs_period = 0;
6475 u32 fec_rs_bit_cnt = 0;
6476 u32 fec_oc_snc_fail_period = 0;
6477 u32 qam_vd_period = 0;
6478 u32 qam_vd_bit_cnt = 0;
6479 u16 fec_vd_plen = 0;
6480 u16 qam_vd_prescale = 0;
6481
6482 dev_addr = demod->my_i2c_dev_addr;
6483 ext_attr = (struct drxj_data *) demod->my_ext_attr;
6484
6485 fec_bits_desired = ext_attr->fec_bits_desired;
6486 fec_rs_prescale = ext_attr->fec_rs_prescale;
6487
6488 switch (constellation) {
6489 case DRX_CONSTELLATION_QAM16:
6490 fec_bits_desired = 4 * symbol_rate;
6491 break;
6492 case DRX_CONSTELLATION_QAM32:
6493 fec_bits_desired = 5 * symbol_rate;
6494 break;
6495 case DRX_CONSTELLATION_QAM64:
6496 fec_bits_desired = 6 * symbol_rate;
6497 break;
6498 case DRX_CONSTELLATION_QAM128:
6499 fec_bits_desired = 7 * symbol_rate;
6500 break;
6501 case DRX_CONSTELLATION_QAM256:
6502 fec_bits_desired = 8 * symbol_rate;
6503 break;
6504 default:
6505 return -EINVAL;
6506 }
6507
6508
6509
6510
6511
6512
6513
6514
6515 switch (ext_attr->standard) {
6516 case DRX_STANDARD_ITU_A:
6517 case DRX_STANDARD_ITU_C:
6518 fec_rs_plen = 204 * 8;
6519 break;
6520 case DRX_STANDARD_ITU_B:
6521 fec_rs_plen = 128 * 7;
6522 break;
6523 default:
6524 return -EINVAL;
6525 }
6526
6527 ext_attr->fec_rs_plen = fec_rs_plen;
6528 fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen;
6529 if (fec_rs_bit_cnt == 0) {
6530 pr_err("error: fec_rs_bit_cnt is zero!\n");
6531 return -EIO;
6532 }
6533 fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1;
6534 if (ext_attr->standard != DRX_STANDARD_ITU_B)
6535 fec_oc_snc_fail_period = fec_rs_period;
6536
6537
6538 if (fec_rs_period > 0xFFFF)
6539 fec_rs_period = 0xFFFF;
6540
6541
6542 switch (ext_attr->standard) {
6543 case DRX_STANDARD_ITU_A:
6544 case DRX_STANDARD_ITU_C:
6545 break;
6546 case DRX_STANDARD_ITU_B:
6547 switch (constellation) {
6548 case DRX_CONSTELLATION_QAM64:
6549 fec_rs_period = 31581;
6550 fec_oc_snc_fail_period = 17932;
6551 break;
6552 case DRX_CONSTELLATION_QAM256:
6553 fec_rs_period = 45446;
6554 fec_oc_snc_fail_period = 25805;
6555 break;
6556 default:
6557 return -EINVAL;
6558 }
6559 break;
6560 default:
6561 return -EINVAL;
6562 }
6563
6564 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6565 if (rc != 0) {
6566 pr_err("error %d\n", rc);
6567 goto rw_error;
6568 }
6569 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6570 if (rc != 0) {
6571 pr_err("error %d\n", rc);
6572 goto rw_error;
6573 }
6574 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6575 if (rc != 0) {
6576 pr_err("error %d\n", rc);
6577 goto rw_error;
6578 }
6579 ext_attr->fec_rs_period = (u16) fec_rs_period;
6580 ext_attr->fec_rs_prescale = fec_rs_prescale;
6581 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6582 if (rc != 0) {
6583 pr_err("error %d\n", rc);
6584 goto rw_error;
6585 }
6586 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6587 if (rc != 0) {
6588 pr_err("error %d\n", rc);
6589 goto rw_error;
6590 }
6591 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6592 if (rc != 0) {
6593 pr_err("error %d\n", rc);
6594 goto rw_error;
6595 }
6596
6597 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6598
6599
6600
6601
6602
6603
6604
6605
6606 fec_vd_plen = ext_attr->fec_vd_plen;
6607 qam_vd_prescale = ext_attr->qam_vd_prescale;
6608 qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen;
6609
6610 switch (constellation) {
6611 case DRX_CONSTELLATION_QAM64:
6612
6613 qam_vd_period =
6614 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
6615 * (QAM_TOP_CONSTELLATION_QAM64 + 1);
6616 break;
6617 case DRX_CONSTELLATION_QAM256:
6618
6619 qam_vd_period =
6620 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
6621 * (QAM_TOP_CONSTELLATION_QAM256 + 1);
6622 break;
6623 default:
6624 return -EINVAL;
6625 }
6626 if (qam_vd_period == 0) {
6627 pr_err("error: qam_vd_period is zero!\n");
6628 return -EIO;
6629 }
6630 qam_vd_period = fec_bits_desired / qam_vd_period;
6631
6632 if (qam_vd_period > 0xFFFF)
6633 qam_vd_period = 0xFFFF;
6634
6635
6636 qam_vd_bit_cnt *= qam_vd_period;
6637
6638 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6639 if (rc != 0) {
6640 pr_err("error %d\n", rc);
6641 goto rw_error;
6642 }
6643 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6644 if (rc != 0) {
6645 pr_err("error %d\n", rc);
6646 goto rw_error;
6647 }
6648 ext_attr->qam_vd_period = (u16) qam_vd_period;
6649 ext_attr->qam_vd_prescale = qam_vd_prescale;
6650 }
6651
6652 return 0;
6653rw_error:
6654 return rc;
6655}
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665static int set_qam16(struct drx_demod_instance *demod)
6666{
6667 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6668 int rc;
6669 const u8 qam_dq_qual_fun[] = {
6670 DRXJ_16TO8(2),
6671 DRXJ_16TO8(2),
6672 DRXJ_16TO8(2),
6673 DRXJ_16TO8(2),
6674 DRXJ_16TO8(3),
6675 DRXJ_16TO8(3),
6676 };
6677 const u8 qam_eq_cma_rad[] = {
6678 DRXJ_16TO8(13517),
6679 DRXJ_16TO8(13517),
6680 DRXJ_16TO8(13517),
6681 DRXJ_16TO8(13517),
6682 DRXJ_16TO8(13517),
6683 DRXJ_16TO8(13517),
6684 };
6685
6686 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6687 if (rc != 0) {
6688 pr_err("error %d\n", rc);
6689 goto rw_error;
6690 }
6691 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6692 if (rc != 0) {
6693 pr_err("error %d\n", rc);
6694 goto rw_error;
6695 }
6696
6697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6698 if (rc != 0) {
6699 pr_err("error %d\n", rc);
6700 goto rw_error;
6701 }
6702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6703 if (rc != 0) {
6704 pr_err("error %d\n", rc);
6705 goto rw_error;
6706 }
6707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6708 if (rc != 0) {
6709 pr_err("error %d\n", rc);
6710 goto rw_error;
6711 }
6712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6713 if (rc != 0) {
6714 pr_err("error %d\n", rc);
6715 goto rw_error;
6716 }
6717 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6718 if (rc != 0) {
6719 pr_err("error %d\n", rc);
6720 goto rw_error;
6721 }
6722 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6723 if (rc != 0) {
6724 pr_err("error %d\n", rc);
6725 goto rw_error;
6726 }
6727
6728 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6729 if (rc != 0) {
6730 pr_err("error %d\n", rc);
6731 goto rw_error;
6732 }
6733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6734 if (rc != 0) {
6735 pr_err("error %d\n", rc);
6736 goto rw_error;
6737 }
6738 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6739 if (rc != 0) {
6740 pr_err("error %d\n", rc);
6741 goto rw_error;
6742 }
6743
6744 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6745 if (rc != 0) {
6746 pr_err("error %d\n", rc);
6747 goto rw_error;
6748 }
6749 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6750 if (rc != 0) {
6751 pr_err("error %d\n", rc);
6752 goto rw_error;
6753 }
6754 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6755 if (rc != 0) {
6756 pr_err("error %d\n", rc);
6757 goto rw_error;
6758 }
6759 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6760 if (rc != 0) {
6761 pr_err("error %d\n", rc);
6762 goto rw_error;
6763 }
6764 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6765 if (rc != 0) {
6766 pr_err("error %d\n", rc);
6767 goto rw_error;
6768 }
6769 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6770 if (rc != 0) {
6771 pr_err("error %d\n", rc);
6772 goto rw_error;
6773 }
6774 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6775 if (rc != 0) {
6776 pr_err("error %d\n", rc);
6777 goto rw_error;
6778 }
6779
6780 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6781 if (rc != 0) {
6782 pr_err("error %d\n", rc);
6783 goto rw_error;
6784 }
6785 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6786 if (rc != 0) {
6787 pr_err("error %d\n", rc);
6788 goto rw_error;
6789 }
6790 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6791 if (rc != 0) {
6792 pr_err("error %d\n", rc);
6793 goto rw_error;
6794 }
6795 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6796 if (rc != 0) {
6797 pr_err("error %d\n", rc);
6798 goto rw_error;
6799 }
6800 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6801 if (rc != 0) {
6802 pr_err("error %d\n", rc);
6803 goto rw_error;
6804 }
6805 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6806 if (rc != 0) {
6807 pr_err("error %d\n", rc);
6808 goto rw_error;
6809 }
6810 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6811 if (rc != 0) {
6812 pr_err("error %d\n", rc);
6813 goto rw_error;
6814 }
6815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6816 if (rc != 0) {
6817 pr_err("error %d\n", rc);
6818 goto rw_error;
6819 }
6820 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6821 if (rc != 0) {
6822 pr_err("error %d\n", rc);
6823 goto rw_error;
6824 }
6825 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6826 if (rc != 0) {
6827 pr_err("error %d\n", rc);
6828 goto rw_error;
6829 }
6830 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6831 if (rc != 0) {
6832 pr_err("error %d\n", rc);
6833 goto rw_error;
6834 }
6835 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6836 if (rc != 0) {
6837 pr_err("error %d\n", rc);
6838 goto rw_error;
6839 }
6840 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6841 if (rc != 0) {
6842 pr_err("error %d\n", rc);
6843 goto rw_error;
6844 }
6845 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6846 if (rc != 0) {
6847 pr_err("error %d\n", rc);
6848 goto rw_error;
6849 }
6850 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6851 if (rc != 0) {
6852 pr_err("error %d\n", rc);
6853 goto rw_error;
6854 }
6855 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6856 if (rc != 0) {
6857 pr_err("error %d\n", rc);
6858 goto rw_error;
6859 }
6860 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6861 if (rc != 0) {
6862 pr_err("error %d\n", rc);
6863 goto rw_error;
6864 }
6865 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6866 if (rc != 0) {
6867 pr_err("error %d\n", rc);
6868 goto rw_error;
6869 }
6870 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6871 if (rc != 0) {
6872 pr_err("error %d\n", rc);
6873 goto rw_error;
6874 }
6875 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6876 if (rc != 0) {
6877 pr_err("error %d\n", rc);
6878 goto rw_error;
6879 }
6880
6881 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6882 if (rc != 0) {
6883 pr_err("error %d\n", rc);
6884 goto rw_error;
6885 }
6886
6887 return 0;
6888rw_error:
6889 return rc;
6890}
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900static int set_qam32(struct drx_demod_instance *demod)
6901{
6902 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6903 int rc;
6904 const u8 qam_dq_qual_fun[] = {
6905 DRXJ_16TO8(3),
6906 DRXJ_16TO8(3),
6907 DRXJ_16TO8(3),
6908 DRXJ_16TO8(3),
6909 DRXJ_16TO8(4),
6910 DRXJ_16TO8(4),
6911 };
6912 const u8 qam_eq_cma_rad[] = {
6913 DRXJ_16TO8(6707),
6914 DRXJ_16TO8(6707),
6915 DRXJ_16TO8(6707),
6916 DRXJ_16TO8(6707),
6917 DRXJ_16TO8(6707),
6918 DRXJ_16TO8(6707),
6919 };
6920
6921 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6922 if (rc != 0) {
6923 pr_err("error %d\n", rc);
6924 goto rw_error;
6925 }
6926 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6927 if (rc != 0) {
6928 pr_err("error %d\n", rc);
6929 goto rw_error;
6930 }
6931
6932 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6933 if (rc != 0) {
6934 pr_err("error %d\n", rc);
6935 goto rw_error;
6936 }
6937 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6938 if (rc != 0) {
6939 pr_err("error %d\n", rc);
6940 goto rw_error;
6941 }
6942 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6943 if (rc != 0) {
6944 pr_err("error %d\n", rc);
6945 goto rw_error;
6946 }
6947 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6948 if (rc != 0) {
6949 pr_err("error %d\n", rc);
6950 goto rw_error;
6951 }
6952 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6953 if (rc != 0) {
6954 pr_err("error %d\n", rc);
6955 goto rw_error;
6956 }
6957 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6958 if (rc != 0) {
6959 pr_err("error %d\n", rc);
6960 goto rw_error;
6961 }
6962
6963 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6964 if (rc != 0) {
6965 pr_err("error %d\n", rc);
6966 goto rw_error;
6967 }
6968 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6969 if (rc != 0) {
6970 pr_err("error %d\n", rc);
6971 goto rw_error;
6972 }
6973 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6974 if (rc != 0) {
6975 pr_err("error %d\n", rc);
6976 goto rw_error;
6977 }
6978
6979 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6980 if (rc != 0) {
6981 pr_err("error %d\n", rc);
6982 goto rw_error;
6983 }
6984 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6985 if (rc != 0) {
6986 pr_err("error %d\n", rc);
6987 goto rw_error;
6988 }
6989 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6990 if (rc != 0) {
6991 pr_err("error %d\n", rc);
6992 goto rw_error;
6993 }
6994 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
6995 if (rc != 0) {
6996 pr_err("error %d\n", rc);
6997 goto rw_error;
6998 }
6999 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
7000 if (rc != 0) {
7001 pr_err("error %d\n", rc);
7002 goto rw_error;
7003 }
7004 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7005 if (rc != 0) {
7006 pr_err("error %d\n", rc);
7007 goto rw_error;
7008 }
7009 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7010 if (rc != 0) {
7011 pr_err("error %d\n", rc);
7012 goto rw_error;
7013 }
7014
7015 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7016 if (rc != 0) {
7017 pr_err("error %d\n", rc);
7018 goto rw_error;
7019 }
7020 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7021 if (rc != 0) {
7022 pr_err("error %d\n", rc);
7023 goto rw_error;
7024 }
7025 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7026 if (rc != 0) {
7027 pr_err("error %d\n", rc);
7028 goto rw_error;
7029 }
7030 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7031 if (rc != 0) {
7032 pr_err("error %d\n", rc);
7033 goto rw_error;
7034 }
7035 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7036 if (rc != 0) {
7037 pr_err("error %d\n", rc);
7038 goto rw_error;
7039 }
7040 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7041 if (rc != 0) {
7042 pr_err("error %d\n", rc);
7043 goto rw_error;
7044 }
7045 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7046 if (rc != 0) {
7047 pr_err("error %d\n", rc);
7048 goto rw_error;
7049 }
7050 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7051 if (rc != 0) {
7052 pr_err("error %d\n", rc);
7053 goto rw_error;
7054 }
7055 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7056 if (rc != 0) {
7057 pr_err("error %d\n", rc);
7058 goto rw_error;
7059 }
7060 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7061 if (rc != 0) {
7062 pr_err("error %d\n", rc);
7063 goto rw_error;
7064 }
7065 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7066 if (rc != 0) {
7067 pr_err("error %d\n", rc);
7068 goto rw_error;
7069 }
7070 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7071 if (rc != 0) {
7072 pr_err("error %d\n", rc);
7073 goto rw_error;
7074 }
7075 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7076 if (rc != 0) {
7077 pr_err("error %d\n", rc);
7078 goto rw_error;
7079 }
7080 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7081 if (rc != 0) {
7082 pr_err("error %d\n", rc);
7083 goto rw_error;
7084 }
7085 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7086 if (rc != 0) {
7087 pr_err("error %d\n", rc);
7088 goto rw_error;
7089 }
7090 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7091 if (rc != 0) {
7092 pr_err("error %d\n", rc);
7093 goto rw_error;
7094 }
7095 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7096 if (rc != 0) {
7097 pr_err("error %d\n", rc);
7098 goto rw_error;
7099 }
7100 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7101 if (rc != 0) {
7102 pr_err("error %d\n", rc);
7103 goto rw_error;
7104 }
7105 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7106 if (rc != 0) {
7107 pr_err("error %d\n", rc);
7108 goto rw_error;
7109 }
7110 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7111 if (rc != 0) {
7112 pr_err("error %d\n", rc);
7113 goto rw_error;
7114 }
7115
7116 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7117 if (rc != 0) {
7118 pr_err("error %d\n", rc);
7119 goto rw_error;
7120 }
7121
7122 return 0;
7123rw_error:
7124 return rc;
7125}
7126
7127
7128
7129
7130
7131
7132
7133
7134
7135static int set_qam64(struct drx_demod_instance *demod)
7136{
7137 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7138 int rc;
7139 const u8 qam_dq_qual_fun[] = {
7140 DRXJ_16TO8(4),
7141 DRXJ_16TO8(4),
7142 DRXJ_16TO8(4),
7143 DRXJ_16TO8(4),
7144 DRXJ_16TO8(6),
7145 DRXJ_16TO8(6),
7146 };
7147 const u8 qam_eq_cma_rad[] = {
7148 DRXJ_16TO8(13336),
7149 DRXJ_16TO8(12618),
7150 DRXJ_16TO8(11988),
7151 DRXJ_16TO8(13809),
7152 DRXJ_16TO8(13809),
7153 DRXJ_16TO8(15609),
7154 };
7155
7156 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7157 if (rc != 0) {
7158 pr_err("error %d\n", rc);
7159 goto rw_error;
7160 }
7161 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7162 if (rc != 0) {
7163 pr_err("error %d\n", rc);
7164 goto rw_error;
7165 }
7166
7167 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7168 if (rc != 0) {
7169 pr_err("error %d\n", rc);
7170 goto rw_error;
7171 }
7172 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7173 if (rc != 0) {
7174 pr_err("error %d\n", rc);
7175 goto rw_error;
7176 }
7177 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7178 if (rc != 0) {
7179 pr_err("error %d\n", rc);
7180 goto rw_error;
7181 }
7182 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7183 if (rc != 0) {
7184 pr_err("error %d\n", rc);
7185 goto rw_error;
7186 }
7187 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7188 if (rc != 0) {
7189 pr_err("error %d\n", rc);
7190 goto rw_error;
7191 }
7192 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7193 if (rc != 0) {
7194 pr_err("error %d\n", rc);
7195 goto rw_error;
7196 }
7197
7198 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7199 if (rc != 0) {
7200 pr_err("error %d\n", rc);
7201 goto rw_error;
7202 }
7203 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7204 if (rc != 0) {
7205 pr_err("error %d\n", rc);
7206 goto rw_error;
7207 }
7208 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7209 if (rc != 0) {
7210 pr_err("error %d\n", rc);
7211 goto rw_error;
7212 }
7213
7214 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7215 if (rc != 0) {
7216 pr_err("error %d\n", rc);
7217 goto rw_error;
7218 }
7219 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7220 if (rc != 0) {
7221 pr_err("error %d\n", rc);
7222 goto rw_error;
7223 }
7224 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7225 if (rc != 0) {
7226 pr_err("error %d\n", rc);
7227 goto rw_error;
7228 }
7229 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7230 if (rc != 0) {
7231 pr_err("error %d\n", rc);
7232 goto rw_error;
7233 }
7234 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7235 if (rc != 0) {
7236 pr_err("error %d\n", rc);
7237 goto rw_error;
7238 }
7239 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7240 if (rc != 0) {
7241 pr_err("error %d\n", rc);
7242 goto rw_error;
7243 }
7244 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7245 if (rc != 0) {
7246 pr_err("error %d\n", rc);
7247 goto rw_error;
7248 }
7249
7250 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7251 if (rc != 0) {
7252 pr_err("error %d\n", rc);
7253 goto rw_error;
7254 }
7255 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7256 if (rc != 0) {
7257 pr_err("error %d\n", rc);
7258 goto rw_error;
7259 }
7260 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7261 if (rc != 0) {
7262 pr_err("error %d\n", rc);
7263 goto rw_error;
7264 }
7265 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7266 if (rc != 0) {
7267 pr_err("error %d\n", rc);
7268 goto rw_error;
7269 }
7270 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7271 if (rc != 0) {
7272 pr_err("error %d\n", rc);
7273 goto rw_error;
7274 }
7275 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7276 if (rc != 0) {
7277 pr_err("error %d\n", rc);
7278 goto rw_error;
7279 }
7280 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7281 if (rc != 0) {
7282 pr_err("error %d\n", rc);
7283 goto rw_error;
7284 }
7285 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7286 if (rc != 0) {
7287 pr_err("error %d\n", rc);
7288 goto rw_error;
7289 }
7290 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7291 if (rc != 0) {
7292 pr_err("error %d\n", rc);
7293 goto rw_error;
7294 }
7295 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7296 if (rc != 0) {
7297 pr_err("error %d\n", rc);
7298 goto rw_error;
7299 }
7300 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7301 if (rc != 0) {
7302 pr_err("error %d\n", rc);
7303 goto rw_error;
7304 }
7305 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7306 if (rc != 0) {
7307 pr_err("error %d\n", rc);
7308 goto rw_error;
7309 }
7310 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7311 if (rc != 0) {
7312 pr_err("error %d\n", rc);
7313 goto rw_error;
7314 }
7315 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7316 if (rc != 0) {
7317 pr_err("error %d\n", rc);
7318 goto rw_error;
7319 }
7320 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7321 if (rc != 0) {
7322 pr_err("error %d\n", rc);
7323 goto rw_error;
7324 }
7325 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7326 if (rc != 0) {
7327 pr_err("error %d\n", rc);
7328 goto rw_error;
7329 }
7330 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7331 if (rc != 0) {
7332 pr_err("error %d\n", rc);
7333 goto rw_error;
7334 }
7335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7336 if (rc != 0) {
7337 pr_err("error %d\n", rc);
7338 goto rw_error;
7339 }
7340 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7341 if (rc != 0) {
7342 pr_err("error %d\n", rc);
7343 goto rw_error;
7344 }
7345 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7346 if (rc != 0) {
7347 pr_err("error %d\n", rc);
7348 goto rw_error;
7349 }
7350
7351 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7352 if (rc != 0) {
7353 pr_err("error %d\n", rc);
7354 goto rw_error;
7355 }
7356
7357 return 0;
7358rw_error:
7359 return rc;
7360}
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370static int set_qam128(struct drx_demod_instance *demod)
7371{
7372 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7373 int rc;
7374 const u8 qam_dq_qual_fun[] = {
7375 DRXJ_16TO8(6),
7376 DRXJ_16TO8(6),
7377 DRXJ_16TO8(6),
7378 DRXJ_16TO8(6),
7379 DRXJ_16TO8(9),
7380 DRXJ_16TO8(9),
7381 };
7382 const u8 qam_eq_cma_rad[] = {
7383 DRXJ_16TO8(6164),
7384 DRXJ_16TO8(6598),
7385 DRXJ_16TO8(6394),
7386 DRXJ_16TO8(6409),
7387 DRXJ_16TO8(6656),
7388 DRXJ_16TO8(7238),
7389 };
7390
7391 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7392 if (rc != 0) {
7393 pr_err("error %d\n", rc);
7394 goto rw_error;
7395 }
7396 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7397 if (rc != 0) {
7398 pr_err("error %d\n", rc);
7399 goto rw_error;
7400 }
7401
7402 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7403 if (rc != 0) {
7404 pr_err("error %d\n", rc);
7405 goto rw_error;
7406 }
7407 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7408 if (rc != 0) {
7409 pr_err("error %d\n", rc);
7410 goto rw_error;
7411 }
7412 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7413 if (rc != 0) {
7414 pr_err("error %d\n", rc);
7415 goto rw_error;
7416 }
7417 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7418 if (rc != 0) {
7419 pr_err("error %d\n", rc);
7420 goto rw_error;
7421 }
7422 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7423 if (rc != 0) {
7424 pr_err("error %d\n", rc);
7425 goto rw_error;
7426 }
7427 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7428 if (rc != 0) {
7429 pr_err("error %d\n", rc);
7430 goto rw_error;
7431 }
7432
7433 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7434 if (rc != 0) {
7435 pr_err("error %d\n", rc);
7436 goto rw_error;
7437 }
7438 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7439 if (rc != 0) {
7440 pr_err("error %d\n", rc);
7441 goto rw_error;
7442 }
7443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7444 if (rc != 0) {
7445 pr_err("error %d\n", rc);
7446 goto rw_error;
7447 }
7448
7449 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7450 if (rc != 0) {
7451 pr_err("error %d\n", rc);
7452 goto rw_error;
7453 }
7454 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7455 if (rc != 0) {
7456 pr_err("error %d\n", rc);
7457 goto rw_error;
7458 }
7459 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7460 if (rc != 0) {
7461 pr_err("error %d\n", rc);
7462 goto rw_error;
7463 }
7464 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7465 if (rc != 0) {
7466 pr_err("error %d\n", rc);
7467 goto rw_error;
7468 }
7469 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7470 if (rc != 0) {
7471 pr_err("error %d\n", rc);
7472 goto rw_error;
7473 }
7474 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7475 if (rc != 0) {
7476 pr_err("error %d\n", rc);
7477 goto rw_error;
7478 }
7479 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7480 if (rc != 0) {
7481 pr_err("error %d\n", rc);
7482 goto rw_error;
7483 }
7484
7485 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7486 if (rc != 0) {
7487 pr_err("error %d\n", rc);
7488 goto rw_error;
7489 }
7490 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7491 if (rc != 0) {
7492 pr_err("error %d\n", rc);
7493 goto rw_error;
7494 }
7495 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7496 if (rc != 0) {
7497 pr_err("error %d\n", rc);
7498 goto rw_error;
7499 }
7500 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7501 if (rc != 0) {
7502 pr_err("error %d\n", rc);
7503 goto rw_error;
7504 }
7505 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7506 if (rc != 0) {
7507 pr_err("error %d\n", rc);
7508 goto rw_error;
7509 }
7510 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7511 if (rc != 0) {
7512 pr_err("error %d\n", rc);
7513 goto rw_error;
7514 }
7515 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7516 if (rc != 0) {
7517 pr_err("error %d\n", rc);
7518 goto rw_error;
7519 }
7520 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7521 if (rc != 0) {
7522 pr_err("error %d\n", rc);
7523 goto rw_error;
7524 }
7525 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7526 if (rc != 0) {
7527 pr_err("error %d\n", rc);
7528 goto rw_error;
7529 }
7530 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7531 if (rc != 0) {
7532 pr_err("error %d\n", rc);
7533 goto rw_error;
7534 }
7535 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7536 if (rc != 0) {
7537 pr_err("error %d\n", rc);
7538 goto rw_error;
7539 }
7540 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7541 if (rc != 0) {
7542 pr_err("error %d\n", rc);
7543 goto rw_error;
7544 }
7545 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7546 if (rc != 0) {
7547 pr_err("error %d\n", rc);
7548 goto rw_error;
7549 }
7550 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7551 if (rc != 0) {
7552 pr_err("error %d\n", rc);
7553 goto rw_error;
7554 }
7555 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7556 if (rc != 0) {
7557 pr_err("error %d\n", rc);
7558 goto rw_error;
7559 }
7560 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7561 if (rc != 0) {
7562 pr_err("error %d\n", rc);
7563 goto rw_error;
7564 }
7565 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7566 if (rc != 0) {
7567 pr_err("error %d\n", rc);
7568 goto rw_error;
7569 }
7570 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7571 if (rc != 0) {
7572 pr_err("error %d\n", rc);
7573 goto rw_error;
7574 }
7575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7576 if (rc != 0) {
7577 pr_err("error %d\n", rc);
7578 goto rw_error;
7579 }
7580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7581 if (rc != 0) {
7582 pr_err("error %d\n", rc);
7583 goto rw_error;
7584 }
7585
7586 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7587 if (rc != 0) {
7588 pr_err("error %d\n", rc);
7589 goto rw_error;
7590 }
7591
7592 return 0;
7593rw_error:
7594 return rc;
7595}
7596
7597
7598
7599
7600
7601
7602
7603
7604
7605static int set_qam256(struct drx_demod_instance *demod)
7606{
7607 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7608 int rc;
7609 const u8 qam_dq_qual_fun[] = {
7610 DRXJ_16TO8(8),
7611 DRXJ_16TO8(8),
7612 DRXJ_16TO8(8),
7613 DRXJ_16TO8(8),
7614 DRXJ_16TO8(12),
7615 DRXJ_16TO8(12),
7616 };
7617 const u8 qam_eq_cma_rad[] = {
7618 DRXJ_16TO8(12345),
7619 DRXJ_16TO8(12345),
7620 DRXJ_16TO8(13626),
7621 DRXJ_16TO8(12931),
7622 DRXJ_16TO8(14719),
7623 DRXJ_16TO8(15356),
7624 };
7625
7626 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7627 if (rc != 0) {
7628 pr_err("error %d\n", rc);
7629 goto rw_error;
7630 }
7631 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7632 if (rc != 0) {
7633 pr_err("error %d\n", rc);
7634 goto rw_error;
7635 }
7636
7637 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7638 if (rc != 0) {
7639 pr_err("error %d\n", rc);
7640 goto rw_error;
7641 }
7642 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7643 if (rc != 0) {
7644 pr_err("error %d\n", rc);
7645 goto rw_error;
7646 }
7647 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7648 if (rc != 0) {
7649 pr_err("error %d\n", rc);
7650 goto rw_error;
7651 }
7652 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7653 if (rc != 0) {
7654 pr_err("error %d\n", rc);
7655 goto rw_error;
7656 }
7657 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7658 if (rc != 0) {
7659 pr_err("error %d\n", rc);
7660 goto rw_error;
7661 }
7662 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7663 if (rc != 0) {
7664 pr_err("error %d\n", rc);
7665 goto rw_error;
7666 }
7667
7668 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7669 if (rc != 0) {
7670 pr_err("error %d\n", rc);
7671 goto rw_error;
7672 }
7673 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7674 if (rc != 0) {
7675 pr_err("error %d\n", rc);
7676 goto rw_error;
7677 }
7678 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7679 if (rc != 0) {
7680 pr_err("error %d\n", rc);
7681 goto rw_error;
7682 }
7683
7684 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7685 if (rc != 0) {
7686 pr_err("error %d\n", rc);
7687 goto rw_error;
7688 }
7689 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7690 if (rc != 0) {
7691 pr_err("error %d\n", rc);
7692 goto rw_error;
7693 }
7694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7695 if (rc != 0) {
7696 pr_err("error %d\n", rc);
7697 goto rw_error;
7698 }
7699 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7700 if (rc != 0) {
7701 pr_err("error %d\n", rc);
7702 goto rw_error;
7703 }
7704 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7705 if (rc != 0) {
7706 pr_err("error %d\n", rc);
7707 goto rw_error;
7708 }
7709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7710 if (rc != 0) {
7711 pr_err("error %d\n", rc);
7712 goto rw_error;
7713 }
7714 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7715 if (rc != 0) {
7716 pr_err("error %d\n", rc);
7717 goto rw_error;
7718 }
7719
7720 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7721 if (rc != 0) {
7722 pr_err("error %d\n", rc);
7723 goto rw_error;
7724 }
7725 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7726 if (rc != 0) {
7727 pr_err("error %d\n", rc);
7728 goto rw_error;
7729 }
7730 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7731 if (rc != 0) {
7732 pr_err("error %d\n", rc);
7733 goto rw_error;
7734 }
7735 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7736 if (rc != 0) {
7737 pr_err("error %d\n", rc);
7738 goto rw_error;
7739 }
7740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7741 if (rc != 0) {
7742 pr_err("error %d\n", rc);
7743 goto rw_error;
7744 }
7745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7746 if (rc != 0) {
7747 pr_err("error %d\n", rc);
7748 goto rw_error;
7749 }
7750 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7751 if (rc != 0) {
7752 pr_err("error %d\n", rc);
7753 goto rw_error;
7754 }
7755 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7756 if (rc != 0) {
7757 pr_err("error %d\n", rc);
7758 goto rw_error;
7759 }
7760 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7761 if (rc != 0) {
7762 pr_err("error %d\n", rc);
7763 goto rw_error;
7764 }
7765 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7766 if (rc != 0) {
7767 pr_err("error %d\n", rc);
7768 goto rw_error;
7769 }
7770 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7771 if (rc != 0) {
7772 pr_err("error %d\n", rc);
7773 goto rw_error;
7774 }
7775 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7776 if (rc != 0) {
7777 pr_err("error %d\n", rc);
7778 goto rw_error;
7779 }
7780 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7781 if (rc != 0) {
7782 pr_err("error %d\n", rc);
7783 goto rw_error;
7784 }
7785 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7786 if (rc != 0) {
7787 pr_err("error %d\n", rc);
7788 goto rw_error;
7789 }
7790 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7791 if (rc != 0) {
7792 pr_err("error %d\n", rc);
7793 goto rw_error;
7794 }
7795 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7796 if (rc != 0) {
7797 pr_err("error %d\n", rc);
7798 goto rw_error;
7799 }
7800 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7801 if (rc != 0) {
7802 pr_err("error %d\n", rc);
7803 goto rw_error;
7804 }
7805 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7806 if (rc != 0) {
7807 pr_err("error %d\n", rc);
7808 goto rw_error;
7809 }
7810 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7811 if (rc != 0) {
7812 pr_err("error %d\n", rc);
7813 goto rw_error;
7814 }
7815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7816 if (rc != 0) {
7817 pr_err("error %d\n", rc);
7818 goto rw_error;
7819 }
7820
7821 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7822 if (rc != 0) {
7823 pr_err("error %d\n", rc);
7824 goto rw_error;
7825 }
7826
7827 return 0;
7828rw_error:
7829 return rc;
7830}
7831
7832
7833#define QAM_SET_OP_ALL 0x1
7834#define QAM_SET_OP_CONSTELLATION 0x2
7835#define QAM_SET_OP_SPECTRUM 0X4
7836
7837
7838
7839
7840
7841
7842
7843
7844static int
7845set_qam(struct drx_demod_instance *demod,
7846 struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
7847{
7848 struct i2c_device_addr *dev_addr = NULL;
7849 struct drxj_data *ext_attr = NULL;
7850 struct drx_common_attr *common_attr = NULL;
7851 int rc;
7852 u32 adc_frequency = 0;
7853 u32 iqm_rc_rate = 0;
7854 u16 cmd_result = 0;
7855 u16 lc_symbol_freq = 0;
7856 u16 iqm_rc_stretch = 0;
7857 u16 set_env_parameters = 0;
7858 u16 set_param_parameters[2] = { 0 };
7859 struct drxjscu_cmd cmd_scu = { 0,
7860 0,
7861 0,
7862 NULL,
7863 NULL
7864 };
7865 const u8 qam_a_taps[] = {
7866 DRXJ_16TO8(-1),
7867 DRXJ_16TO8(1),
7868 DRXJ_16TO8(1),
7869 DRXJ_16TO8(-1),
7870 DRXJ_16TO8(-1),
7871 DRXJ_16TO8(2),
7872 DRXJ_16TO8(1),
7873 DRXJ_16TO8(-2),
7874 DRXJ_16TO8(0),
7875 DRXJ_16TO8(3),
7876 DRXJ_16TO8(-1),
7877 DRXJ_16TO8(-3),
7878 DRXJ_16TO8(4),
7879 DRXJ_16TO8(1),
7880 DRXJ_16TO8(-8),
7881 DRXJ_16TO8(4),
7882 DRXJ_16TO8(13),
7883 DRXJ_16TO8(-13),
7884 DRXJ_16TO8(-19),
7885 DRXJ_16TO8(28),
7886 DRXJ_16TO8(25),
7887 DRXJ_16TO8(-53),
7888 DRXJ_16TO8(-31),
7889 DRXJ_16TO8(96),
7890 DRXJ_16TO8(37),
7891 DRXJ_16TO8(-190),
7892 DRXJ_16TO8(-40),
7893 DRXJ_16TO8(619)
7894 };
7895 const u8 qam_b64_taps[] = {
7896 DRXJ_16TO8(0),
7897 DRXJ_16TO8(-2),
7898 DRXJ_16TO8(1),
7899 DRXJ_16TO8(2),
7900 DRXJ_16TO8(-2),
7901 DRXJ_16TO8(0),
7902 DRXJ_16TO8(4),
7903 DRXJ_16TO8(-2),
7904 DRXJ_16TO8(-4),
7905 DRXJ_16TO8(4),
7906 DRXJ_16TO8(3),
7907 DRXJ_16TO8(-6),
7908 DRXJ_16TO8(0),
7909 DRXJ_16TO8(6),
7910 DRXJ_16TO8(-5),
7911 DRXJ_16TO8(-3),
7912 DRXJ_16TO8(11),
7913 DRXJ_16TO8(-4),
7914 DRXJ_16TO8(-19),
7915 DRXJ_16TO8(19),
7916 DRXJ_16TO8(28),
7917 DRXJ_16TO8(-45),
7918 DRXJ_16TO8(-36),
7919 DRXJ_16TO8(90),
7920 DRXJ_16TO8(42),
7921 DRXJ_16TO8(-185),
7922 DRXJ_16TO8(-46),
7923 DRXJ_16TO8(614)
7924 };
7925 const u8 qam_b256_taps[] = {
7926 DRXJ_16TO8(-2),
7927 DRXJ_16TO8(4),
7928 DRXJ_16TO8(1),
7929 DRXJ_16TO8(-4),
7930 DRXJ_16TO8(0),
7931 DRXJ_16TO8(4),
7932 DRXJ_16TO8(-2),
7933 DRXJ_16TO8(-4),
7934 DRXJ_16TO8(5),
7935 DRXJ_16TO8(2),
7936 DRXJ_16TO8(-8),
7937 DRXJ_16TO8(2),
7938 DRXJ_16TO8(11),
7939 DRXJ_16TO8(-8),
7940 DRXJ_16TO8(-15),
7941 DRXJ_16TO8(16),
7942 DRXJ_16TO8(19),
7943 DRXJ_16TO8(-27),
7944 DRXJ_16TO8(-22),
7945 DRXJ_16TO8(44),
7946 DRXJ_16TO8(26),
7947 DRXJ_16TO8(-69),
7948 DRXJ_16TO8(-28),
7949 DRXJ_16TO8(110),
7950 DRXJ_16TO8(31),
7951 DRXJ_16TO8(-201),
7952 DRXJ_16TO8(-32),
7953 DRXJ_16TO8(628)
7954 };
7955 const u8 qam_c_taps[] = {
7956 DRXJ_16TO8(-3),
7957 DRXJ_16TO8(3),
7958 DRXJ_16TO8(2),
7959 DRXJ_16TO8(-4),
7960 DRXJ_16TO8(0),
7961 DRXJ_16TO8(4),
7962 DRXJ_16TO8(-1),
7963 DRXJ_16TO8(-4),
7964 DRXJ_16TO8(3),
7965 DRXJ_16TO8(3),
7966 DRXJ_16TO8(-5),
7967 DRXJ_16TO8(0),
7968 DRXJ_16TO8(9),
7969 DRXJ_16TO8(-4),
7970 DRXJ_16TO8(-12),
7971 DRXJ_16TO8(10),
7972 DRXJ_16TO8(16),
7973 DRXJ_16TO8(-21),
7974 DRXJ_16TO8(-20),
7975 DRXJ_16TO8(37),
7976 DRXJ_16TO8(25),
7977 DRXJ_16TO8(-62),
7978 DRXJ_16TO8(-28),
7979 DRXJ_16TO8(105),
7980 DRXJ_16TO8(31),
7981 DRXJ_16TO8(-197),
7982 DRXJ_16TO8(-33),
7983 DRXJ_16TO8(626)
7984 };
7985
7986 dev_addr = demod->my_i2c_dev_addr;
7987 ext_attr = (struct drxj_data *) demod->my_ext_attr;
7988 common_attr = (struct drx_common_attr *) demod->my_common_attr;
7989
7990 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
7991 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
7992 switch (channel->constellation) {
7993 case DRX_CONSTELLATION_QAM256:
7994 iqm_rc_rate = 0x00AE3562;
7995 lc_symbol_freq =
7996 QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
7997 channel->symbolrate = 5360537;
7998 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
7999 break;
8000 case DRX_CONSTELLATION_QAM64:
8001 iqm_rc_rate = 0x00C05A0E;
8002 lc_symbol_freq = 409;
8003 channel->symbolrate = 5056941;
8004 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
8005 break;
8006 default:
8007 return -EINVAL;
8008 }
8009 } else {
8010 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
8011 if (channel->symbolrate == 0) {
8012 pr_err("error: channel symbolrate is zero!\n");
8013 return -EIO;
8014 }
8015 iqm_rc_rate =
8016 (adc_frequency / channel->symbolrate) * (1 << 21) +
8017 (frac28
8018 ((adc_frequency % channel->symbolrate),
8019 channel->symbolrate) >> 7) - (1 << 23);
8020 lc_symbol_freq =
8021 (u16) (frac28
8022 (channel->symbolrate +
8023 (adc_frequency >> 13),
8024 adc_frequency) >> 16);
8025 if (lc_symbol_freq > 511)
8026 lc_symbol_freq = 511;
8027
8028 iqm_rc_stretch = 21;
8029 }
8030
8031 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8032 set_env_parameters = QAM_TOP_ANNEX_A;
8033 set_param_parameters[0] = channel->constellation;
8034 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17;
8035 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8036 set_env_parameters = QAM_TOP_ANNEX_B;
8037 set_param_parameters[0] = channel->constellation;
8038 set_param_parameters[1] = channel->interleavemode;
8039 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8040 set_env_parameters = QAM_TOP_ANNEX_C;
8041 set_param_parameters[0] = channel->constellation;
8042 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17;
8043 } else {
8044 return -EINVAL;
8045 }
8046 }
8047
8048 if (op & QAM_SET_OP_ALL) {
8049
8050
8051
8052
8053
8054
8055 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8056 if (rc != 0) {
8057 pr_err("error %d\n", rc);
8058 goto rw_error;
8059 }
8060 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8061 if (rc != 0) {
8062 pr_err("error %d\n", rc);
8063 goto rw_error;
8064 }
8065 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8066 if (rc != 0) {
8067 pr_err("error %d\n", rc);
8068 goto rw_error;
8069 }
8070 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8071 if (rc != 0) {
8072 pr_err("error %d\n", rc);
8073 goto rw_error;
8074 }
8075 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8076 if (rc != 0) {
8077 pr_err("error %d\n", rc);
8078 goto rw_error;
8079 }
8080 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8081 if (rc != 0) {
8082 pr_err("error %d\n", rc);
8083 goto rw_error;
8084 }
8085 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8086 if (rc != 0) {
8087 pr_err("error %d\n", rc);
8088 goto rw_error;
8089 }
8090
8091 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8092 SCU_RAM_COMMAND_CMD_DEMOD_RESET;
8093 cmd_scu.parameter_len = 0;
8094 cmd_scu.result_len = 1;
8095 cmd_scu.parameter = NULL;
8096 cmd_scu.result = &cmd_result;
8097 rc = scu_command(dev_addr, &cmd_scu);
8098 if (rc != 0) {
8099 pr_err("error %d\n", rc);
8100 goto rw_error;
8101 }
8102 }
8103
8104 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8105
8106
8107
8108
8109
8110 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8111 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
8112 cmd_scu.parameter_len = 1;
8113 cmd_scu.result_len = 1;
8114 cmd_scu.parameter = &set_env_parameters;
8115 cmd_scu.result = &cmd_result;
8116 rc = scu_command(dev_addr, &cmd_scu);
8117 if (rc != 0) {
8118 pr_err("error %d\n", rc);
8119 goto rw_error;
8120 }
8121
8122 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8123 SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
8124 cmd_scu.parameter_len = 2;
8125 cmd_scu.result_len = 1;
8126 cmd_scu.parameter = set_param_parameters;
8127 cmd_scu.result = &cmd_result;
8128 rc = scu_command(dev_addr, &cmd_scu);
8129 if (rc != 0) {
8130 pr_err("error %d\n", rc);
8131 goto rw_error;
8132 }
8133
8134 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8135 if (rc != 0) {
8136 pr_err("error %d\n", rc);
8137 goto rw_error;
8138 }
8139 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8140 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8141 if (rc != 0) {
8142 pr_err("error %d\n", rc);
8143 goto rw_error;
8144 }
8145 }
8146
8147
8148
8149
8150 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
8151 rc = set_frequency(demod, channel, tuner_freq_offset);
8152 if (rc != 0) {
8153 pr_err("error %d\n", rc);
8154 goto rw_error;
8155 }
8156 }
8157
8158 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8159
8160 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8161 if (rc != 0) {
8162 pr_err("error %d\n", rc);
8163 goto rw_error;
8164 }
8165 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8166 if (rc != 0) {
8167 pr_err("error %d\n", rc);
8168 goto rw_error;
8169 }
8170 }
8171
8172 if (op & QAM_SET_OP_ALL) {
8173 if (!ext_attr->has_lna) {
8174 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8175 if (rc != 0) {
8176 pr_err("error %d\n", rc);
8177 goto rw_error;
8178 }
8179 }
8180 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8181 if (rc != 0) {
8182 pr_err("error %d\n", rc);
8183 goto rw_error;
8184 }
8185 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8186 if (rc != 0) {
8187 pr_err("error %d\n", rc);
8188 goto rw_error;
8189 }
8190 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8191 if (rc != 0) {
8192 pr_err("error %d\n", rc);
8193 goto rw_error;
8194 }
8195
8196 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8197 if (rc != 0) {
8198 pr_err("error %d\n", rc);
8199 goto rw_error;
8200 }
8201
8202 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8203 if (rc != 0) {
8204 pr_err("error %d\n", rc);
8205 goto rw_error;
8206 }
8207 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8208 if (rc != 0) {
8209 pr_err("error %d\n", rc);
8210 goto rw_error;
8211 }
8212 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8213 if (rc != 0) {
8214 pr_err("error %d\n", rc);
8215 goto rw_error;
8216 }
8217 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8218 if (rc != 0) {
8219 pr_err("error %d\n", rc);
8220 goto rw_error;
8221 }
8222 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8223 if (rc != 0) {
8224 pr_err("error %d\n", rc);
8225 goto rw_error;
8226 }
8227 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8228 if (rc != 0) {
8229 pr_err("error %d\n", rc);
8230 goto rw_error;
8231 }
8232 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8233 if (rc != 0) {
8234 pr_err("error %d\n", rc);
8235 goto rw_error;
8236 }
8237
8238 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8239 if (rc != 0) {
8240 pr_err("error %d\n", rc);
8241 goto rw_error;
8242 }
8243 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8244 if (rc != 0) {
8245 pr_err("error %d\n", rc);
8246 goto rw_error;
8247 }
8248
8249 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8250 if (rc != 0) {
8251 pr_err("error %d\n", rc);
8252 goto rw_error;
8253 }
8254 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8255 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8256 if (rc != 0) {
8257 pr_err("error %d\n", rc);
8258 goto rw_error;
8259 }
8260 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8261 if (rc != 0) {
8262 pr_err("error %d\n", rc);
8263 goto rw_error;
8264 }
8265 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8266 if (rc != 0) {
8267 pr_err("error %d\n", rc);
8268 goto rw_error;
8269 }
8270 } else {
8271 switch (channel->constellation) {
8272 case DRX_CONSTELLATION_QAM16:
8273 case DRX_CONSTELLATION_QAM64:
8274 case DRX_CONSTELLATION_QAM256:
8275 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8276 if (rc != 0) {
8277 pr_err("error %d\n", rc);
8278 goto rw_error;
8279 }
8280 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8281 if (rc != 0) {
8282 pr_err("error %d\n", rc);
8283 goto rw_error;
8284 }
8285 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8286 if (rc != 0) {
8287 pr_err("error %d\n", rc);
8288 goto rw_error;
8289 }
8290 break;
8291 case DRX_CONSTELLATION_QAM32:
8292 case DRX_CONSTELLATION_QAM128:
8293 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8294 if (rc != 0) {
8295 pr_err("error %d\n", rc);
8296 goto rw_error;
8297 }
8298 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8299 if (rc != 0) {
8300 pr_err("error %d\n", rc);
8301 goto rw_error;
8302 }
8303 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8304 if (rc != 0) {
8305 pr_err("error %d\n", rc);
8306 goto rw_error;
8307 }
8308 break;
8309 default:
8310 return -EIO;
8311 }
8312 }
8313
8314 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8315 if (rc != 0) {
8316 pr_err("error %d\n", rc);
8317 goto rw_error;
8318 }
8319 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8320 if (rc != 0) {
8321 pr_err("error %d\n", rc);
8322 goto rw_error;
8323 }
8324 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8325 if (rc != 0) {
8326 pr_err("error %d\n", rc);
8327 goto rw_error;
8328 }
8329 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8330 if (rc != 0) {
8331 pr_err("error %d\n", rc);
8332 goto rw_error;
8333 }
8334 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8335 if (rc != 0) {
8336 pr_err("error %d\n", rc);
8337 goto rw_error;
8338 }
8339 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8340 if (rc != 0) {
8341 pr_err("error %d\n", rc);
8342 goto rw_error;
8343 }
8344 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8345 if (rc != 0) {
8346 pr_err("error %d\n", rc);
8347 goto rw_error;
8348 }
8349 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8350 if (rc != 0) {
8351 pr_err("error %d\n", rc);
8352 goto rw_error;
8353 }
8354 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8355 if (rc != 0) {
8356 pr_err("error %d\n", rc);
8357 goto rw_error;
8358 }
8359 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8360 if (rc != 0) {
8361 pr_err("error %d\n", rc);
8362 goto rw_error;
8363 }
8364 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8365 if (rc != 0) {
8366 pr_err("error %d\n", rc);
8367 goto rw_error;
8368 }
8369 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8370 if (rc != 0) {
8371 pr_err("error %d\n", rc);
8372 goto rw_error;
8373 }
8374 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8375 if (rc != 0) {
8376 pr_err("error %d\n", rc);
8377 goto rw_error;
8378 }
8379 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8380 if (rc != 0) {
8381 pr_err("error %d\n", rc);
8382 goto rw_error;
8383 }
8384 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8385 if (rc != 0) {
8386 pr_err("error %d\n", rc);
8387 goto rw_error;
8388 }
8389 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8390 if (rc != 0) {
8391 pr_err("error %d\n", rc);
8392 goto rw_error;
8393 }
8394 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8395 if (rc != 0) {
8396 pr_err("error %d\n", rc);
8397 goto rw_error;
8398 }
8399 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8400 if (rc != 0) {
8401 pr_err("error %d\n", rc);
8402 goto rw_error;
8403 }
8404 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8405 if (rc != 0) {
8406 pr_err("error %d\n", rc);
8407 goto rw_error;
8408 }
8409 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8410 if (rc != 0) {
8411 pr_err("error %d\n", rc);
8412 goto rw_error;
8413 }
8414
8415 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8416 if (rc != 0) {
8417 pr_err("error %d\n", rc);
8418 goto rw_error;
8419 }
8420 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8421 if (rc != 0) {
8422 pr_err("error %d\n", rc);
8423 goto rw_error;
8424 }
8425 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8426 if (rc != 0) {
8427 pr_err("error %d\n", rc);
8428 goto rw_error;
8429 }
8430 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8431 if (rc != 0) {
8432 pr_err("error %d\n", rc);
8433 goto rw_error;
8434 }
8435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8436 if (rc != 0) {
8437 pr_err("error %d\n", rc);
8438 goto rw_error;
8439 }
8440
8441
8442
8443
8444 rc = set_iqm_af(demod, true);
8445 if (rc != 0) {
8446 pr_err("error %d\n", rc);
8447 goto rw_error;
8448 }
8449 rc = adc_synchronization(demod);
8450 if (rc != 0) {
8451 pr_err("error %d\n", rc);
8452 goto rw_error;
8453 }
8454
8455 rc = init_agc(demod);
8456 if (rc != 0) {
8457 pr_err("error %d\n", rc);
8458 goto rw_error;
8459 }
8460 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8461 if (rc != 0) {
8462 pr_err("error %d\n", rc);
8463 goto rw_error;
8464 }
8465 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8466 if (rc != 0) {
8467 pr_err("error %d\n", rc);
8468 goto rw_error;
8469 }
8470 {
8471
8472
8473 struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
8474
8475 qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8476 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8477 if (rc != 0) {
8478 pr_err("error %d\n", rc);
8479 goto rw_error;
8480 }
8481 }
8482 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8483 if (rc != 0) {
8484 pr_err("error %d\n", rc);
8485 goto rw_error;
8486 }
8487 }
8488
8489 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8490 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8491 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8492 if (rc != 0) {
8493 pr_err("error %d\n", rc);
8494 goto rw_error;
8495 }
8496 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8497 if (rc != 0) {
8498 pr_err("error %d\n", rc);
8499 goto rw_error;
8500 }
8501 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8502 switch (channel->constellation) {
8503 case DRX_CONSTELLATION_QAM64:
8504 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8505 if (rc != 0) {
8506 pr_err("error %d\n", rc);
8507 goto rw_error;
8508 }
8509 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8510 if (rc != 0) {
8511 pr_err("error %d\n", rc);
8512 goto rw_error;
8513 }
8514 break;
8515 case DRX_CONSTELLATION_QAM256:
8516 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8517 if (rc != 0) {
8518 pr_err("error %d\n", rc);
8519 goto rw_error;
8520 }
8521 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8522 if (rc != 0) {
8523 pr_err("error %d\n", rc);
8524 goto rw_error;
8525 }
8526 break;
8527 default:
8528 return -EIO;
8529 }
8530 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8531 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8532 if (rc != 0) {
8533 pr_err("error %d\n", rc);
8534 goto rw_error;
8535 }
8536 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8537 if (rc != 0) {
8538 pr_err("error %d\n", rc);
8539 goto rw_error;
8540 }
8541 }
8542
8543
8544 switch (channel->constellation) {
8545 case DRX_CONSTELLATION_QAM16:
8546 rc = set_qam16(demod);
8547 if (rc != 0) {
8548 pr_err("error %d\n", rc);
8549 goto rw_error;
8550 }
8551 break;
8552 case DRX_CONSTELLATION_QAM32:
8553 rc = set_qam32(demod);
8554 if (rc != 0) {
8555 pr_err("error %d\n", rc);
8556 goto rw_error;
8557 }
8558 break;
8559 case DRX_CONSTELLATION_QAM64:
8560 rc = set_qam64(demod);
8561 if (rc != 0) {
8562 pr_err("error %d\n", rc);
8563 goto rw_error;
8564 }
8565 break;
8566 case DRX_CONSTELLATION_QAM128:
8567 rc = set_qam128(demod);
8568 if (rc != 0) {
8569 pr_err("error %d\n", rc);
8570 goto rw_error;
8571 }
8572 break;
8573 case DRX_CONSTELLATION_QAM256:
8574 rc = set_qam256(demod);
8575 if (rc != 0) {
8576 pr_err("error %d\n", rc);
8577 goto rw_error;
8578 }
8579 break;
8580 default:
8581 return -EIO;
8582 }
8583 }
8584
8585 if ((op & QAM_SET_OP_ALL)) {
8586 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8587 if (rc != 0) {
8588 pr_err("error %d\n", rc);
8589 goto rw_error;
8590 }
8591
8592
8593 rc = set_mpegtei_handling(demod);
8594 if (rc != 0) {
8595 pr_err("error %d\n", rc);
8596 goto rw_error;
8597 }
8598 rc = bit_reverse_mpeg_output(demod);
8599 if (rc != 0) {
8600 pr_err("error %d\n", rc);
8601 goto rw_error;
8602 }
8603 rc = set_mpeg_start_width(demod);
8604 if (rc != 0) {
8605 pr_err("error %d\n", rc);
8606 goto rw_error;
8607 }
8608 {
8609
8610
8611 struct drx_cfg_mpeg_output cfg_mpeg_output;
8612
8613 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
8614 cfg_mpeg_output.enable_mpeg_output = true;
8615
8616 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8617 if (rc != 0) {
8618 pr_err("error %d\n", rc);
8619 goto rw_error;
8620 }
8621 }
8622 }
8623
8624 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8625
8626
8627 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8628 SCU_RAM_COMMAND_CMD_DEMOD_START;
8629 cmd_scu.parameter_len = 0;
8630 cmd_scu.result_len = 1;
8631 cmd_scu.parameter = NULL;
8632 cmd_scu.result = &cmd_result;
8633 rc = scu_command(dev_addr, &cmd_scu);
8634 if (rc != 0) {
8635 pr_err("error %d\n", rc);
8636 goto rw_error;
8637 }
8638 }
8639
8640 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8641 if (rc != 0) {
8642 pr_err("error %d\n", rc);
8643 goto rw_error;
8644 }
8645 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8646 if (rc != 0) {
8647 pr_err("error %d\n", rc);
8648 goto rw_error;
8649 }
8650 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8651 if (rc != 0) {
8652 pr_err("error %d\n", rc);
8653 goto rw_error;
8654 }
8655
8656 return 0;
8657rw_error:
8658 return rc;
8659}
8660
8661
8662static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
8663
8664static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
8665{
8666 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8667 struct drxj_data *ext_attr = demod->my_ext_attr;
8668 int rc;
8669 u32 iqm_fs_rate_ofs = 0;
8670 u32 iqm_fs_rate_lo = 0;
8671 u16 qam_ctl_ena = 0;
8672 u16 data = 0;
8673 u16 equ_mode = 0;
8674 u16 fsm_state = 0;
8675 int i = 0;
8676 int ofsofs = 0;
8677
8678
8679 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8680 if (rc != 0) {
8681 pr_err("error %d\n", rc);
8682 goto rw_error;
8683 }
8684 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8685 if (rc != 0) {
8686 pr_err("error %d\n", rc);
8687 goto rw_error;
8688 }
8689
8690
8691 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8692 if (rc != 0) {
8693 pr_err("error %d\n", rc);
8694 goto rw_error;
8695 }
8696 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8697 if (rc != 0) {
8698 pr_err("error %d\n", rc);
8699 goto rw_error;
8700 }
8701
8702 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8703 if (rc != 0) {
8704 pr_err("error %d\n", rc);
8705 goto rw_error;
8706 }
8707 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8708 if (rc != 0) {
8709 pr_err("error %d\n", rc);
8710 goto rw_error;
8711 }
8712 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
8713 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
8714 iqm_fs_rate_ofs -= 2 * ofsofs;
8715
8716
8717 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8718 if (rc != 0) {
8719 pr_err("error %d\n", rc);
8720 goto rw_error;
8721 }
8722 data = (data & 0xfff9);
8723 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8724 if (rc != 0) {
8725 pr_err("error %d\n", rc);
8726 goto rw_error;
8727 }
8728 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8729 if (rc != 0) {
8730 pr_err("error %d\n", rc);
8731 goto rw_error;
8732 }
8733
8734
8735 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8736 if (rc != 0) {
8737 pr_err("error %d\n", rc);
8738 goto rw_error;
8739 }
8740 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8741 if (rc != 0) {
8742 pr_err("error %d\n", rc);
8743 goto rw_error;
8744 }
8745 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8746 if (rc != 0) {
8747 pr_err("error %d\n", rc);
8748 goto rw_error;
8749 }
8750
8751
8752 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8753 if (rc != 0) {
8754 pr_err("error %d\n", rc);
8755 goto rw_error;
8756 }
8757 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8758 ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
8759
8760
8761 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8762 if (rc != 0) {
8763 pr_err("error %d\n", rc);
8764 goto rw_error;
8765 }
8766 equ_mode = data;
8767 data = (data & 0xfff9);
8768 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8769 if (rc != 0) {
8770 pr_err("error %d\n", rc);
8771 goto rw_error;
8772 }
8773 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8774 if (rc != 0) {
8775 pr_err("error %d\n", rc);
8776 goto rw_error;
8777 }
8778
8779 for (i = 0; i < 28; i++) {
8780 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8781 if (rc != 0) {
8782 pr_err("error %d\n", rc);
8783 goto rw_error;
8784 }
8785 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8786 if (rc != 0) {
8787 pr_err("error %d\n", rc);
8788 goto rw_error;
8789 }
8790 }
8791
8792 for (i = 0; i < 24; i++) {
8793 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8794 if (rc != 0) {
8795 pr_err("error %d\n", rc);
8796 goto rw_error;
8797 }
8798 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8799 if (rc != 0) {
8800 pr_err("error %d\n", rc);
8801 goto rw_error;
8802 }
8803 }
8804
8805 data = equ_mode;
8806 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8807 if (rc != 0) {
8808 pr_err("error %d\n", rc);
8809 goto rw_error;
8810 }
8811 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8812 if (rc != 0) {
8813 pr_err("error %d\n", rc);
8814 goto rw_error;
8815 }
8816
8817 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8818 if (rc != 0) {
8819 pr_err("error %d\n", rc);
8820 goto rw_error;
8821 }
8822
8823 i = 0;
8824 while ((fsm_state != 4) && (i++ < 100)) {
8825 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8826 if (rc != 0) {
8827 pr_err("error %d\n", rc);
8828 goto rw_error;
8829 }
8830 }
8831 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8832 if (rc != 0) {
8833 pr_err("error %d\n", rc);
8834 goto rw_error;
8835 }
8836
8837 return 0;
8838rw_error:
8839 return rc;
8840
8841}
8842
8843#define NO_LOCK 0x0
8844#define DEMOD_LOCKED 0x1
8845#define SYNC_FLIPPED 0x2
8846#define SPEC_MIRRORED 0x4
8847
8848
8849
8850
8851
8852
8853
8854
8855
8856static int
8857qam64auto(struct drx_demod_instance *demod,
8858 struct drx_channel *channel,
8859 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
8860{
8861 struct drxj_data *ext_attr = demod->my_ext_attr;
8862 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8863 struct drx39xxj_state *state = dev_addr->user_data;
8864 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
8865 int rc;
8866 u32 lck_state = NO_LOCK;
8867 u32 start_time = 0;
8868 u32 d_locked_time = 0;
8869 u32 timeout_ofs = 0;
8870 u16 data = 0;
8871
8872
8873 *lock_status = DRX_NOT_LOCKED;
8874 start_time = jiffies_to_msecs(jiffies);
8875 lck_state = NO_LOCK;
8876 do {
8877 rc = ctrl_lock_status(demod, lock_status);
8878 if (rc != 0) {
8879 pr_err("error %d\n", rc);
8880 goto rw_error;
8881 }
8882
8883 switch (lck_state) {
8884 case NO_LOCK:
8885 if (*lock_status == DRXJ_DEMOD_LOCK) {
8886 rc = ctrl_get_qam_sig_quality(demod);
8887 if (rc != 0) {
8888 pr_err("error %d\n", rc);
8889 goto rw_error;
8890 }
8891 if (p->cnr.stat[0].svalue > 20800) {
8892 lck_state = DEMOD_LOCKED;
8893
8894 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
8895 d_locked_time = jiffies_to_msecs(jiffies);
8896 }
8897 }
8898 break;
8899 case DEMOD_LOCKED:
8900 if ((*lock_status == DRXJ_DEMOD_LOCK) &&
8901 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8902 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8903 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8904 if (rc != 0) {
8905 pr_err("error %d\n", rc);
8906 goto rw_error;
8907 }
8908 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8909 if (rc != 0) {
8910 pr_err("error %d\n", rc);
8911 goto rw_error;
8912 }
8913 lck_state = SYNC_FLIPPED;
8914 msleep(10);
8915 }
8916 break;
8917 case SYNC_FLIPPED:
8918 if (*lock_status == DRXJ_DEMOD_LOCK) {
8919 if (channel->mirror == DRX_MIRROR_AUTO) {
8920
8921 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8922 if (rc != 0) {
8923 pr_err("error %d\n", rc);
8924 goto rw_error;
8925 }
8926 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8927 if (rc != 0) {
8928 pr_err("error %d\n", rc);
8929 goto rw_error;
8930 }
8931
8932 ext_attr->mirror = DRX_MIRROR_YES;
8933 rc = qam_flip_spec(demod, channel);
8934 if (rc != 0) {
8935 pr_err("error %d\n", rc);
8936 goto rw_error;
8937 }
8938 lck_state = SPEC_MIRRORED;
8939
8940 start_time = d_locked_time =
8941 jiffies_to_msecs(jiffies);
8942 timeout_ofs = 0;
8943 } else {
8944
8945 start_time =
8946 jiffies_to_msecs(jiffies) -
8947 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8948 }
8949 }
8950 break;
8951 case SPEC_MIRRORED:
8952 if ((*lock_status == DRXJ_DEMOD_LOCK) &&
8953 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8954 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8955 rc = ctrl_get_qam_sig_quality(demod);
8956 if (rc != 0) {
8957 pr_err("error %d\n", rc);
8958 goto rw_error;
8959 }
8960 if (p->cnr.stat[0].svalue > 20800) {
8961 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8962 if (rc != 0) {
8963 pr_err("error %d\n", rc);
8964 goto rw_error;
8965 }
8966 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8967 if (rc != 0) {
8968 pr_err("error %d\n", rc);
8969 goto rw_error;
8970 }
8971
8972 start_time =
8973 jiffies_to_msecs(jiffies) -
8974 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8975 }
8976 }
8977 break;
8978 default:
8979 break;
8980 }
8981 msleep(10);
8982 } while
8983 ((*lock_status != DRX_LOCKED) &&
8984 (*lock_status != DRX_NEVER_LOCK) &&
8985 ((jiffies_to_msecs(jiffies) - start_time) <
8986 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
8987 );
8988
8989
8990 return 0;
8991rw_error:
8992 return rc;
8993}
8994
8995
8996
8997
8998
8999
9000
9001
9002
9003
9004static int
9005qam256auto(struct drx_demod_instance *demod,
9006 struct drx_channel *channel,
9007 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
9008{
9009 struct drxj_data *ext_attr = demod->my_ext_attr;
9010 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9011 struct drx39xxj_state *state = dev_addr->user_data;
9012 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9013 int rc;
9014 u32 lck_state = NO_LOCK;
9015 u32 start_time = 0;
9016 u32 d_locked_time = 0;
9017 u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
9018
9019
9020 *lock_status = DRX_NOT_LOCKED;
9021 start_time = jiffies_to_msecs(jiffies);
9022 lck_state = NO_LOCK;
9023 do {
9024 rc = ctrl_lock_status(demod, lock_status);
9025 if (rc != 0) {
9026 pr_err("error %d\n", rc);
9027 goto rw_error;
9028 }
9029 switch (lck_state) {
9030 case NO_LOCK:
9031 if (*lock_status == DRXJ_DEMOD_LOCK) {
9032 rc = ctrl_get_qam_sig_quality(demod);
9033 if (rc != 0) {
9034 pr_err("error %d\n", rc);
9035 goto rw_error;
9036 }
9037 if (p->cnr.stat[0].svalue > 26800) {
9038 lck_state = DEMOD_LOCKED;
9039 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
9040 d_locked_time = jiffies_to_msecs(jiffies);
9041 }
9042 }
9043 break;
9044 case DEMOD_LOCKED:
9045 if (*lock_status == DRXJ_DEMOD_LOCK) {
9046 if ((channel->mirror == DRX_MIRROR_AUTO) &&
9047 ((jiffies_to_msecs(jiffies) - d_locked_time) >
9048 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
9049 ext_attr->mirror = DRX_MIRROR_YES;
9050 rc = qam_flip_spec(demod, channel);
9051 if (rc != 0) {
9052 pr_err("error %d\n", rc);
9053 goto rw_error;
9054 }
9055 lck_state = SPEC_MIRRORED;
9056
9057 start_time = jiffies_to_msecs(jiffies);
9058 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
9059 }
9060 }
9061 break;
9062 case SPEC_MIRRORED:
9063 break;
9064 default:
9065 break;
9066 }
9067 msleep(10);
9068 } while
9069 ((*lock_status < DRX_LOCKED) &&
9070 (*lock_status != DRX_NEVER_LOCK) &&
9071 ((jiffies_to_msecs(jiffies) - start_time) <
9072 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
9073
9074 return 0;
9075rw_error:
9076 return rc;
9077}
9078
9079
9080
9081
9082
9083
9084
9085
9086static int
9087set_qam_channel(struct drx_demod_instance *demod,
9088 struct drx_channel *channel, s32 tuner_freq_offset)
9089{
9090 struct drxj_data *ext_attr = NULL;
9091 int rc;
9092 enum drx_lock_status lock_status = DRX_NOT_LOCKED;
9093 bool auto_flag = false;
9094
9095
9096 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9097
9098
9099 switch (channel->constellation) {
9100 case DRX_CONSTELLATION_QAM16:
9101 case DRX_CONSTELLATION_QAM32:
9102 case DRX_CONSTELLATION_QAM128:
9103 return -EINVAL;
9104 case DRX_CONSTELLATION_QAM64:
9105 case DRX_CONSTELLATION_QAM256:
9106 if (ext_attr->standard != DRX_STANDARD_ITU_B)
9107 return -EINVAL;
9108
9109 ext_attr->constellation = channel->constellation;
9110 if (channel->mirror == DRX_MIRROR_AUTO)
9111 ext_attr->mirror = DRX_MIRROR_NO;
9112 else
9113 ext_attr->mirror = channel->mirror;
9114
9115 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9116 if (rc != 0) {
9117 pr_err("error %d\n", rc);
9118 goto rw_error;
9119 }
9120
9121 if (channel->constellation == DRX_CONSTELLATION_QAM64)
9122 rc = qam64auto(demod, channel, tuner_freq_offset,
9123 &lock_status);
9124 else
9125 rc = qam256auto(demod, channel, tuner_freq_offset,
9126 &lock_status);
9127 if (rc != 0) {
9128 pr_err("error %d\n", rc);
9129 goto rw_error;
9130 }
9131 break;
9132 case DRX_CONSTELLATION_AUTO:
9133 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9134 u16 qam_ctl_ena = 0;
9135
9136 auto_flag = true;
9137
9138
9139 channel->constellation = DRX_CONSTELLATION_QAM256;
9140 ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9141 if (channel->mirror == DRX_MIRROR_AUTO)
9142 ext_attr->mirror = DRX_MIRROR_NO;
9143 else
9144 ext_attr->mirror = channel->mirror;
9145 rc = set_qam(demod, channel, tuner_freq_offset,
9146 QAM_SET_OP_ALL);
9147 if (rc != 0) {
9148 pr_err("error %d\n", rc);
9149 goto rw_error;
9150 }
9151 rc = qam256auto(demod, channel, tuner_freq_offset,
9152 &lock_status);
9153 if (rc != 0) {
9154 pr_err("error %d\n", rc);
9155 goto rw_error;
9156 }
9157
9158 if (lock_status >= DRX_LOCKED) {
9159 channel->constellation = DRX_CONSTELLATION_AUTO;
9160 break;
9161 }
9162
9163
9164 channel->constellation = DRX_CONSTELLATION_QAM64;
9165 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9166 if (channel->mirror == DRX_MIRROR_AUTO)
9167 ext_attr->mirror = DRX_MIRROR_NO;
9168 else
9169 ext_attr->mirror = channel->mirror;
9170
9171 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9172 SCU_RAM_QAM_CTL_ENA__A,
9173 &qam_ctl_ena, 0);
9174 if (rc != 0) {
9175 pr_err("error %d\n", rc);
9176 goto rw_error;
9177 }
9178 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9179 SCU_RAM_QAM_CTL_ENA__A,
9180 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9181 if (rc != 0) {
9182 pr_err("error %d\n", rc);
9183 goto rw_error;
9184 }
9185 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9186 SCU_RAM_QAM_FSM_STATE_TGT__A,
9187 0x2, 0);
9188 if (rc != 0) {
9189 pr_err("error %d\n", rc);
9190 goto rw_error;
9191 }
9192
9193 rc = set_qam(demod, channel, tuner_freq_offset,
9194 QAM_SET_OP_CONSTELLATION);
9195 if (rc != 0) {
9196 pr_err("error %d\n", rc);
9197 goto rw_error;
9198 }
9199 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9200 SCU_RAM_QAM_CTL_ENA__A,
9201 qam_ctl_ena, 0);
9202 if (rc != 0) {
9203 pr_err("error %d\n", rc);
9204 goto rw_error;
9205 }
9206
9207 rc = qam64auto(demod, channel, tuner_freq_offset,
9208 &lock_status);
9209 if (rc != 0) {
9210 pr_err("error %d\n", rc);
9211 goto rw_error;
9212 }
9213
9214 channel->constellation = DRX_CONSTELLATION_AUTO;
9215 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9216 u16 qam_ctl_ena = 0;
9217
9218 channel->constellation = DRX_CONSTELLATION_QAM64;
9219 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9220 auto_flag = true;
9221
9222 if (channel->mirror == DRX_MIRROR_AUTO)
9223 ext_attr->mirror = DRX_MIRROR_NO;
9224 else
9225 ext_attr->mirror = channel->mirror;
9226 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9227 SCU_RAM_QAM_CTL_ENA__A,
9228 &qam_ctl_ena, 0);
9229 if (rc != 0) {
9230 pr_err("error %d\n", rc);
9231 goto rw_error;
9232 }
9233 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9234 SCU_RAM_QAM_CTL_ENA__A,
9235 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9236 if (rc != 0) {
9237 pr_err("error %d\n", rc);
9238 goto rw_error;
9239 }
9240 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9241 SCU_RAM_QAM_FSM_STATE_TGT__A,
9242 0x2, 0);
9243 if (rc != 0) {
9244 pr_err("error %d\n", rc);
9245 goto rw_error;
9246 }
9247
9248 rc = set_qam(demod, channel, tuner_freq_offset,
9249 QAM_SET_OP_CONSTELLATION);
9250 if (rc != 0) {
9251 pr_err("error %d\n", rc);
9252 goto rw_error;
9253 }
9254 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9255 SCU_RAM_QAM_CTL_ENA__A,
9256 qam_ctl_ena, 0);
9257 if (rc != 0) {
9258 pr_err("error %d\n", rc);
9259 goto rw_error;
9260 }
9261 rc = qam64auto(demod, channel, tuner_freq_offset,
9262 &lock_status);
9263 if (rc != 0) {
9264 pr_err("error %d\n", rc);
9265 goto rw_error;
9266 }
9267 channel->constellation = DRX_CONSTELLATION_AUTO;
9268 } else {
9269 return -EINVAL;
9270 }
9271 break;
9272 default:
9273 return -EINVAL;
9274 }
9275
9276 return 0;
9277rw_error:
9278
9279 if (auto_flag)
9280 channel->constellation = DRX_CONSTELLATION_AUTO;
9281 return rc;
9282}
9283
9284
9285
9286
9287
9288
9289
9290
9291
9292
9293
9294static int
9295get_qamrs_err_count(struct i2c_device_addr *dev_addr,
9296 struct drxjrs_errors *rs_errors)
9297{
9298 int rc;
9299 u16 nr_bit_errors = 0,
9300 nr_symbol_errors = 0,
9301 nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
9302
9303
9304 if (dev_addr == NULL)
9305 return -EINVAL;
9306
9307
9308
9309
9310 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9311 if (rc != 0) {
9312 pr_err("error %d\n", rc);
9313 goto rw_error;
9314 }
9315
9316 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9317 if (rc != 0) {
9318 pr_err("error %d\n", rc);
9319 goto rw_error;
9320 }
9321
9322 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9323 if (rc != 0) {
9324 pr_err("error %d\n", rc);
9325 goto rw_error;
9326 }
9327
9328 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9329 if (rc != 0) {
9330 pr_err("error %d\n", rc);
9331 goto rw_error;
9332 }
9333
9334 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9335 if (rc != 0) {
9336 pr_err("error %d\n", rc);
9337 goto rw_error;
9338 }
9339
9340
9341
9342
9343 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
9344 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
9345 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
9346 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
9347 rs_errors->nr_snc_par_fail_count =
9348 nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
9349
9350 return 0;
9351rw_error:
9352 return rc;
9353}
9354
9355
9356
9357
9358
9359
9360
9361
9362
9363
9364
9365
9366
9367#define DRXJ_AGC_TOP 0x2800
9368#define DRXJ_AGC_SNS 0x1600
9369#define DRXJ_RFAGC_MAX 0x3fff
9370#define DRXJ_RFAGC_MIN 0x800
9371
9372static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
9373{
9374 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9375 int rc;
9376 u16 rf_gain = 0;
9377 u16 if_gain = 0;
9378 u16 if_agc_sns = 0;
9379 u16 if_agc_top = 0;
9380 u16 rf_agc_max = 0;
9381 u16 rf_agc_min = 0;
9382
9383 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9384 if (rc != 0) {
9385 pr_err("error %d\n", rc);
9386 goto rw_error;
9387 }
9388 if_gain &= IQM_AF_AGC_IF__M;
9389 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9390 if (rc != 0) {
9391 pr_err("error %d\n", rc);
9392 goto rw_error;
9393 }
9394 rf_gain &= IQM_AF_AGC_RF__M;
9395
9396 if_agc_sns = DRXJ_AGC_SNS;
9397 if_agc_top = DRXJ_AGC_TOP;
9398 rf_agc_max = DRXJ_RFAGC_MAX;
9399 rf_agc_min = DRXJ_RFAGC_MIN;
9400
9401 if (if_gain > if_agc_top) {
9402 if (rf_gain > rf_agc_max)
9403 *sig_strength = 100;
9404 else if (rf_gain > rf_agc_min) {
9405 if (rf_agc_max == rf_agc_min) {
9406 pr_err("error: rf_agc_max == rf_agc_min\n");
9407 return -EIO;
9408 }
9409 *sig_strength =
9410 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
9411 rf_agc_min);
9412 } else
9413 *sig_strength = 75;
9414 } else if (if_gain > if_agc_sns) {
9415 if (if_agc_top == if_agc_sns) {
9416 pr_err("error: if_agc_top == if_agc_sns\n");
9417 return -EIO;
9418 }
9419 *sig_strength =
9420 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
9421 } else {
9422 if (!if_agc_sns) {
9423 pr_err("error: if_agc_sns is zero!\n");
9424 return -EIO;
9425 }
9426 *sig_strength = (20 * if_gain / if_agc_sns);
9427 }
9428
9429 if (*sig_strength <= 7)
9430 *sig_strength = 0;
9431
9432 return 0;
9433rw_error:
9434 return rc;
9435}
9436
9437
9438
9439
9440
9441
9442
9443
9444
9445
9446
9447
9448
9449static int
9450ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
9451{
9452 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9453 struct drxj_data *ext_attr = demod->my_ext_attr;
9454 struct drx39xxj_state *state = dev_addr->user_data;
9455 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9456 struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
9457 enum drx_modulation constellation = ext_attr->constellation;
9458 int rc;
9459
9460 u32 pre_bit_err_rs = 0;
9461 u32 post_bit_err_rs = 0;
9462 u32 pkt_errs = 0;
9463 u16 qam_sl_err_power = 0;
9464 u16 qsym_err_vd = 0;
9465 u16 fec_oc_period = 0;
9466 u16 fec_rs_prescale = 0;
9467 u16 fec_rs_period = 0;
9468
9469 u32 rs_bit_cnt = 0;
9470 u32 qam_sl_sig_power = 0;
9471
9472 u32 e = 0;
9473 u32 m = 0;
9474 u32 ber_cnt = 0;
9475
9476 u32 qam_sl_mer = 0;
9477 u32 qam_pre_rs_ber = 0;
9478 u32 qam_post_rs_ber = 0;
9479 u32 qam_vd_ser = 0;
9480 u16 qam_vd_prescale = 0;
9481 u16 qam_vd_period = 0;
9482 u32 vd_bit_cnt = 0;
9483
9484 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9485
9486
9487
9488 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9489 if (rc != 0) {
9490 pr_err("error %d\n", rc);
9491 goto rw_error;
9492 }
9493
9494 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9495 if (rc != 0) {
9496 pr_err("error %d\n", rc);
9497 goto rw_error;
9498 }
9499
9500 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9501 if (rc != 0) {
9502 pr_err("error %d\n", rc);
9503 goto rw_error;
9504 }
9505
9506
9507 fec_rs_period = ext_attr->fec_rs_period;
9508 fec_rs_prescale = ext_attr->fec_rs_prescale;
9509 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9510 qam_vd_period = ext_attr->qam_vd_period;
9511 qam_vd_prescale = ext_attr->qam_vd_prescale;
9512 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9513
9514
9515 switch (constellation) {
9516 case DRX_CONSTELLATION_QAM16:
9517 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
9518 break;
9519 case DRX_CONSTELLATION_QAM32:
9520 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
9521 break;
9522 case DRX_CONSTELLATION_QAM64:
9523 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
9524 break;
9525 case DRX_CONSTELLATION_QAM128:
9526 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
9527 break;
9528 case DRX_CONSTELLATION_QAM256:
9529 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
9530 break;
9531 default:
9532 return -EIO;
9533 }
9534
9535
9536
9537
9538
9539
9540
9541 if (qam_sl_err_power == 0)
9542 qam_sl_mer = 0;
9543 else
9544 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
9545
9546
9547
9548
9549
9550
9551
9552
9553 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9554 if (rc != 0) {
9555 pr_err("error %d\n", rc);
9556 goto rw_error;
9557 }
9558
9559
9560 e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
9561 QAM_VD_NR_QSYM_ERRORS_EXP__B;
9562 m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
9563 QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
9564
9565 if ((m << e) >> 3 > 549752)
9566 qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9567 else
9568 qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
9569
9570
9571
9572
9573
9574
9575
9576 pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
9577 pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
9578
9579
9580
9581 e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
9582 FEC_RS_NR_BIT_ERRORS_EXP__B;
9583 m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
9584 FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
9585
9586 ber_cnt = m << e;
9587
9588
9589 if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
9590 qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
9591 else
9592 qam_pre_rs_ber = ber_cnt;
9593
9594
9595
9596
9597
9598
9599
9600
9601
9602
9603
9604
9605 if (!fec_oc_period) {
9606 qam_post_rs_ber = 0xFFFFFFFF;
9607 } else {
9608 e = post_bit_err_rs * 742686;
9609 m = fec_oc_period * 100;
9610 qam_post_rs_ber = e / m;
9611 }
9612
9613
9614 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9615 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9616 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9617 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9618 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
9619 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
9620
9621 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
9622 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9623 p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
9624 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9625 } else {
9626 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
9627 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9628 }
9629
9630 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
9631 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9632
9633 p->block_error.stat[0].uvalue += pkt_errs;
9634
9635#ifdef DRXJ_SIGNAL_ACCUM_ERR
9636 rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9637 if (rc != 0) {
9638 pr_err("error %d\n", rc);
9639 goto rw_error;
9640 }
9641#endif
9642
9643 return 0;
9644rw_error:
9645 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9646 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9647 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9648 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9649 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9650 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9651
9652 return rc;
9653}
9654
9655#endif
9656
9657
9658
9659
9660
9661
9662
9663
9664
9665
9666
9667
9668
9669
9670
9671
9672
9673
9674
9675
9676
9677
9678
9679
9680
9681
9682
9683
9684
9685
9686
9687
9688
9689
9690
9691
9692
9693
9694
9695
9696
9697
9698
9699
9700
9701
9702
9703
9704
9705
9706
9707
9708
9709
9710
9711
9712
9713
9714
9715
9716
9717
9718
9719
9720
9721
9722
9723
9724
9725
9726
9727
9728
9729
9730
9731
9732
9733
9734static int
9735power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
9736{
9737 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9738 struct drxjscu_cmd cmd_scu = { 0,
9739 0,
9740 0,
9741 NULL,
9742 NULL
9743 };
9744 int rc;
9745 u16 cmd_result = 0;
9746
9747
9748
9749
9750 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
9751 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9752 cmd_scu.parameter_len = 0;
9753 cmd_scu.result_len = 1;
9754 cmd_scu.parameter = NULL;
9755 cmd_scu.result = &cmd_result;
9756 rc = scu_command(dev_addr, &cmd_scu);
9757 if (rc != 0) {
9758 pr_err("error %d\n", rc);
9759 goto rw_error;
9760 }
9761
9762 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9763 if (rc != 0) {
9764 pr_err("error %d\n", rc);
9765 goto rw_error;
9766 }
9767
9768 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9769 if (rc != 0) {
9770 pr_err("error %d\n", rc);
9771 goto rw_error;
9772 }
9773 if (primary) {
9774 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9775 if (rc != 0) {
9776 pr_err("error %d\n", rc);
9777 goto rw_error;
9778 }
9779 rc = set_iqm_af(demod, false);
9780 if (rc != 0) {
9781 pr_err("error %d\n", rc);
9782 goto rw_error;
9783 }
9784 } else {
9785 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9786 if (rc != 0) {
9787 pr_err("error %d\n", rc);
9788 goto rw_error;
9789 }
9790 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9791 if (rc != 0) {
9792 pr_err("error %d\n", rc);
9793 goto rw_error;
9794 }
9795 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9796 if (rc != 0) {
9797 pr_err("error %d\n", rc);
9798 goto rw_error;
9799 }
9800 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9801 if (rc != 0) {
9802 pr_err("error %d\n", rc);
9803 goto rw_error;
9804 }
9805 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9806 if (rc != 0) {
9807 pr_err("error %d\n", rc);
9808 goto rw_error;
9809 }
9810 }
9811 rc = power_down_aud(demod);
9812 if (rc != 0) {
9813 pr_err("error %d\n", rc);
9814 goto rw_error;
9815 }
9816
9817 return 0;
9818rw_error:
9819 return rc;
9820}
9821
9822
9823
9824
9825
9826
9827
9828
9829
9830static int power_down_aud(struct drx_demod_instance *demod)
9831{
9832 struct i2c_device_addr *dev_addr = NULL;
9833 struct drxj_data *ext_attr = NULL;
9834 int rc;
9835
9836 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
9837 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9838
9839 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9840 if (rc != 0) {
9841 pr_err("error %d\n", rc);
9842 goto rw_error;
9843 }
9844
9845 ext_attr->aud_data.audio_is_active = false;
9846
9847 return 0;
9848rw_error:
9849 return rc;
9850}
9851
9852
9853
9854
9855
9856
9857
9858
9859static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
9860{
9861 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9862 int rc;
9863 u16 data = 0;
9864
9865
9866 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9867 if (rc != 0) {
9868 pr_err("error %d\n", rc);
9869 goto rw_error;
9870 }
9871 if (!active)
9872 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
9873 else
9874 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
9875 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9876 if (rc != 0) {
9877 pr_err("error %d\n", rc);
9878 goto rw_error;
9879 }
9880
9881 return 0;
9882rw_error:
9883 return rc;
9884}
9885
9886
9887
9888
9889
9890
9891
9892
9893
9894
9895
9896
9897
9898
9899
9900
9901
9902
9903#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140}
9904#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145}
9905#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128}
9906
9907
9908#define NYQFILTERLEN 27
9909
9910static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
9911{
9912 int rc;
9913 s32 freq = 0;
9914 struct i2c_device_addr *dev_addr = NULL;
9915 struct drxj_data *ext_attr = NULL;
9916 u16 i = 0;
9917 bool mirror_freq_spect_oob = false;
9918 u16 trk_filter_value = 0;
9919 struct drxjscu_cmd scu_cmd;
9920 u16 set_param_parameters[3];
9921 u16 cmd_result[2] = { 0, 0 };
9922 s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
9923 IMPULSE_COSINE_ALPHA_0_3,
9924 IMPULSE_COSINE_ALPHA_0_3,
9925 IMPULSE_COSINE_ALPHA_0_5,
9926 IMPULSE_COSINE_ALPHA_RO_0_5
9927 };
9928 u8 mode_val[4] = { 2, 2, 0, 1 };
9929 u8 pfi_coeffs[4][6] = {
9930 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)},
9931 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)},
9932 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)},
9933 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}
9934 };
9935 u16 mode_index;
9936
9937 dev_addr = demod->my_i2c_dev_addr;
9938 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9939 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9940
9941
9942 if (oob_param == NULL) {
9943
9944 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9945 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9946 scu_cmd.parameter_len = 0;
9947 scu_cmd.result_len = 1;
9948 scu_cmd.result = cmd_result;
9949 rc = scu_command(dev_addr, &scu_cmd);
9950 if (rc != 0) {
9951 pr_err("error %d\n", rc);
9952 goto rw_error;
9953 }
9954 rc = set_orx_nsu_aox(demod, false);
9955 if (rc != 0) {
9956 pr_err("error %d\n", rc);
9957 goto rw_error;
9958 }
9959 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9960 if (rc != 0) {
9961 pr_err("error %d\n", rc);
9962 goto rw_error;
9963 }
9964
9965 ext_attr->oob_power_on = false;
9966 return 0;
9967 }
9968
9969 freq = oob_param->frequency;
9970 if ((freq < 70000) || (freq > 130000))
9971 return -EIO;
9972 freq = (freq - 50000) / 50;
9973
9974 {
9975 u16 index = 0;
9976 u16 remainder = 0;
9977 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
9978
9979 index = (u16) ((freq - 400) / 200);
9980 remainder = (u16) ((freq - 400) % 200);
9981 trk_filter_value =
9982 trk_filtercfg[index] - (trk_filtercfg[index] -
9983 trk_filtercfg[index +
9984 1]) / 10 * remainder /
9985 20;
9986 }
9987
9988
9989
9990
9991 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9992 if (rc != 0) {
9993 pr_err("error %d\n", rc);
9994 goto rw_error;
9995 }
9996 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9997 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9998 scu_cmd.parameter_len = 0;
9999 scu_cmd.result_len = 1;
10000 scu_cmd.result = cmd_result;
10001 rc = scu_command(dev_addr, &scu_cmd);
10002 if (rc != 0) {
10003 pr_err("error %d\n", rc);
10004 goto rw_error;
10005 }
10006
10007
10008
10009 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10010 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
10011 scu_cmd.parameter_len = 0;
10012 scu_cmd.result_len = 1;
10013 scu_cmd.result = cmd_result;
10014 rc = scu_command(dev_addr, &scu_cmd);
10015 if (rc != 0) {
10016 pr_err("error %d\n", rc);
10017 goto rw_error;
10018 }
10019
10020
10021
10022
10023 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10024 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
10025 scu_cmd.parameter_len = 3;
10026
10027 switch (oob_param->standard) {
10028 case DRX_OOB_MODE_A:
10029 if (
10030
10031 ((oob_param->spectrum_inverted == true) &&
10032
10033 (!mirror_freq_spect_oob)) |
10034
10035
10036 ((oob_param->spectrum_inverted == false) &&
10037
10038 (mirror_freq_spect_oob))
10039 )
10040 set_param_parameters[0] =
10041 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
10042 else
10043 set_param_parameters[0] =
10044 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
10045 break;
10046 case DRX_OOB_MODE_B_GRADE_A:
10047 if (
10048
10049 ((oob_param->spectrum_inverted == true) &&
10050
10051 (!mirror_freq_spect_oob)) |
10052
10053
10054 ((oob_param->spectrum_inverted == false) &&
10055
10056 (mirror_freq_spect_oob))
10057 )
10058 set_param_parameters[0] =
10059 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
10060 else
10061 set_param_parameters[0] =
10062 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
10063 break;
10064 case DRX_OOB_MODE_B_GRADE_B:
10065 default:
10066 if (
10067
10068 ((oob_param->spectrum_inverted == true) &&
10069
10070 (!mirror_freq_spect_oob)) |
10071
10072
10073 ((oob_param->spectrum_inverted == false) &&
10074
10075 (mirror_freq_spect_oob))
10076 )
10077 set_param_parameters[0] =
10078 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
10079 else
10080 set_param_parameters[0] =
10081 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
10082 break;
10083 }
10084 set_param_parameters[1] = (u16) (freq & 0xFFFF);
10085 set_param_parameters[2] = trk_filter_value;
10086 scu_cmd.parameter = set_param_parameters;
10087 scu_cmd.result_len = 1;
10088 scu_cmd.result = cmd_result;
10089 mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
10090 rc = scu_command(dev_addr, &scu_cmd);
10091 if (rc != 0) {
10092 pr_err("error %d\n", rc);
10093 goto rw_error;
10094 }
10095
10096 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10097 if (rc != 0) {
10098 pr_err("error %d\n", rc);
10099 goto rw_error;
10100 }
10101 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10102 if (rc != 0) {
10103 pr_err("error %d\n", rc);
10104 goto rw_error;
10105 }
10106 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10107 if (rc != 0) {
10108 pr_err("error %d\n", rc);
10109 goto rw_error;
10110 }
10111 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10112 if (rc != 0) {
10113 pr_err("error %d\n", rc);
10114 goto rw_error;
10115 }
10116
10117 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10118 if (rc != 0) {
10119 pr_err("error %d\n", rc);
10120 goto rw_error;
10121 }
10122 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10123 if (rc != 0) {
10124 pr_err("error %d\n", rc);
10125 goto rw_error;
10126 }
10127 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10128 if (rc != 0) {
10129 pr_err("error %d\n", rc);
10130 goto rw_error;
10131 }
10132
10133
10134 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10135 if (rc != 0) {
10136 pr_err("error %d\n", rc);
10137 goto rw_error;
10138 }
10139
10140
10141 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10142 if (rc != 0) {
10143 pr_err("error %d\n", rc);
10144 goto rw_error;
10145 }
10146
10147
10148 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10149 if (rc != 0) {
10150 pr_err("error %d\n", rc);
10151 goto rw_error;
10152 }
10153 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10154 if (rc != 0) {
10155 pr_err("error %d\n", rc);
10156 goto rw_error;
10157 }
10158
10159
10160 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10161 if (rc != 0) {
10162 pr_err("error %d\n", rc);
10163 goto rw_error;
10164 }
10165 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10166 if (rc != 0) {
10167 pr_err("error %d\n", rc);
10168 goto rw_error;
10169 }
10170 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10171 if (rc != 0) {
10172 pr_err("error %d\n", rc);
10173 goto rw_error;
10174 }
10175 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10176 if (rc != 0) {
10177 pr_err("error %d\n", rc);
10178 goto rw_error;
10179 }
10180
10181
10182 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10183 if (rc != 0) {
10184 pr_err("error %d\n", rc);
10185 goto rw_error;
10186 }
10187 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10188 if (rc != 0) {
10189 pr_err("error %d\n", rc);
10190 goto rw_error;
10191 }
10192 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10193 if (rc != 0) {
10194 pr_err("error %d\n", rc);
10195 goto rw_error;
10196 }
10197 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10198 if (rc != 0) {
10199 pr_err("error %d\n", rc);
10200 goto rw_error;
10201 }
10202 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10203 if (rc != 0) {
10204 pr_err("error %d\n", rc);
10205 goto rw_error;
10206 }
10207
10208
10209 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10210 if (rc != 0) {
10211 pr_err("error %d\n", rc);
10212 goto rw_error;
10213 }
10214 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10215 if (rc != 0) {
10216 pr_err("error %d\n", rc);
10217 goto rw_error;
10218 }
10219 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10220 if (rc != 0) {
10221 pr_err("error %d\n", rc);
10222 goto rw_error;
10223 }
10224 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10225 if (rc != 0) {
10226 pr_err("error %d\n", rc);
10227 goto rw_error;
10228 }
10229 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10230 if (rc != 0) {
10231 pr_err("error %d\n", rc);
10232 goto rw_error;
10233 }
10234
10235
10236 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10237 if (rc != 0) {
10238 pr_err("error %d\n", rc);
10239 goto rw_error;
10240 }
10241 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10242 if (rc != 0) {
10243 pr_err("error %d\n", rc);
10244 goto rw_error;
10245 }
10246 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10247 if (rc != 0) {
10248 pr_err("error %d\n", rc);
10249 goto rw_error;
10250 }
10251 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10252 if (rc != 0) {
10253 pr_err("error %d\n", rc);
10254 goto rw_error;
10255 }
10256 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10257 if (rc != 0) {
10258 pr_err("error %d\n", rc);
10259 goto rw_error;
10260 }
10261
10262
10263 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10264 if (rc != 0) {
10265 pr_err("error %d\n", rc);
10266 goto rw_error;
10267 }
10268 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10269 if (rc != 0) {
10270 pr_err("error %d\n", rc);
10271 goto rw_error;
10272 }
10273 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10274 if (rc != 0) {
10275 pr_err("error %d\n", rc);
10276 goto rw_error;
10277 }
10278 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10279 if (rc != 0) {
10280 pr_err("error %d\n", rc);
10281 goto rw_error;
10282 }
10283 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10284 if (rc != 0) {
10285 pr_err("error %d\n", rc);
10286 goto rw_error;
10287 }
10288
10289
10290 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10291 if (rc != 0) {
10292 pr_err("error %d\n", rc);
10293 goto rw_error;
10294 }
10295 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10296 if (rc != 0) {
10297 pr_err("error %d\n", rc);
10298 goto rw_error;
10299 }
10300 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10301 if (rc != 0) {
10302 pr_err("error %d\n", rc);
10303 goto rw_error;
10304 }
10305 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10306 if (rc != 0) {
10307 pr_err("error %d\n", rc);
10308 goto rw_error;
10309 }
10310 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10311 if (rc != 0) {
10312 pr_err("error %d\n", rc);
10313 goto rw_error;
10314 }
10315
10316
10317 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10318 if (rc != 0) {
10319 pr_err("error %d\n", rc);
10320 goto rw_error;
10321 }
10322 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10323 if (rc != 0) {
10324 pr_err("error %d\n", rc);
10325 goto rw_error;
10326 }
10327 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10328 if (rc != 0) {
10329 pr_err("error %d\n", rc);
10330 goto rw_error;
10331 }
10332 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10333 if (rc != 0) {
10334 pr_err("error %d\n", rc);
10335 goto rw_error;
10336 }
10337 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10338 if (rc != 0) {
10339 pr_err("error %d\n", rc);
10340 goto rw_error;
10341 }
10342
10343
10344 rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10345 if (rc != 0) {
10346 pr_err("error %d\n", rc);
10347 goto rw_error;
10348 }
10349 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10350 if (rc != 0) {
10351 pr_err("error %d\n", rc);
10352 goto rw_error;
10353 }
10354
10355
10356 for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
10357 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10358 if (rc != 0) {
10359 pr_err("error %d\n", rc);
10360 goto rw_error;
10361 }
10362 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10363 if (rc != 0) {
10364 pr_err("error %d\n", rc);
10365 goto rw_error;
10366 }
10367 }
10368 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10369 if (rc != 0) {
10370 pr_err("error %d\n", rc);
10371 goto rw_error;
10372 }
10373 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10374 if (rc != 0) {
10375 pr_err("error %d\n", rc);
10376 goto rw_error;
10377 }
10378
10379
10380
10381 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10382 | SCU_RAM_COMMAND_CMD_DEMOD_START;
10383 scu_cmd.parameter_len = 0;
10384 scu_cmd.result_len = 1;
10385 scu_cmd.result = cmd_result;
10386 rc = scu_command(dev_addr, &scu_cmd);
10387 if (rc != 0) {
10388 pr_err("error %d\n", rc);
10389 goto rw_error;
10390 }
10391
10392 rc = set_orx_nsu_aox(demod, true);
10393 if (rc != 0) {
10394 pr_err("error %d\n", rc);
10395 goto rw_error;
10396 }
10397 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10398 if (rc != 0) {
10399 pr_err("error %d\n", rc);
10400 goto rw_error;
10401 }
10402
10403 ext_attr->oob_power_on = true;
10404
10405 return 0;
10406rw_error:
10407 return rc;
10408}
10409
10410
10411
10412
10413
10414
10415
10416
10417
10418
10419
10420
10421
10422
10423
10424
10425
10426
10427
10428
10429
10430
10431
10432static int
10433ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
10434{
10435 int rc;
10436 s32 tuner_freq_offset = 0;
10437 struct drxj_data *ext_attr = NULL;
10438 struct i2c_device_addr *dev_addr = NULL;
10439 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10440#ifndef DRXJ_VSB_ONLY
10441 u32 min_symbol_rate = 0;
10442 u32 max_symbol_rate = 0;
10443 int bandwidth_temp = 0;
10444 int bandwidth = 0;
10445#endif
10446
10447 if ((demod == NULL) || (channel == NULL))
10448 return -EINVAL;
10449
10450 dev_addr = demod->my_i2c_dev_addr;
10451 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10452 standard = ext_attr->standard;
10453
10454
10455 switch (standard) {
10456 case DRX_STANDARD_8VSB:
10457#ifndef DRXJ_VSB_ONLY
10458 case DRX_STANDARD_ITU_A:
10459 case DRX_STANDARD_ITU_B:
10460 case DRX_STANDARD_ITU_C:
10461#endif
10462 break;
10463 case DRX_STANDARD_UNKNOWN:
10464 default:
10465 return -EINVAL;
10466 }
10467
10468
10469 if ((standard == DRX_STANDARD_ITU_B) ||
10470 (standard == DRX_STANDARD_8VSB) ||
10471 (standard == DRX_STANDARD_NTSC)) {
10472 switch (channel->bandwidth) {
10473 case DRX_BANDWIDTH_6MHZ:
10474 case DRX_BANDWIDTH_UNKNOWN:
10475 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10476 break;
10477 case DRX_BANDWIDTH_8MHZ:
10478 case DRX_BANDWIDTH_7MHZ:
10479 default:
10480 return -EINVAL;
10481 }
10482 }
10483
10484
10485
10486
10487
10488#ifndef DRXJ_VSB_ONLY
10489 if ((standard == DRX_STANDARD_ITU_A) ||
10490 (standard == DRX_STANDARD_ITU_C)) {
10491 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
10492 int bw_rolloff_factor = 0;
10493
10494 bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
10495 min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
10496 max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
10497
10498 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10499 if (rc != 0) {
10500 pr_err("error %d\n", rc);
10501 goto rw_error;
10502 }
10503
10504 if (channel->symbolrate < min_symbol_rate ||
10505 channel->symbolrate > max_symbol_rate) {
10506 return -EINVAL;
10507 }
10508
10509 switch (channel->constellation) {
10510 case DRX_CONSTELLATION_QAM16:
10511 case DRX_CONSTELLATION_QAM32:
10512 case DRX_CONSTELLATION_QAM64:
10513 case DRX_CONSTELLATION_QAM128:
10514 case DRX_CONSTELLATION_QAM256:
10515 bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10516 bandwidth = bandwidth_temp / 100;
10517
10518 if ((bandwidth_temp % 100) >= 50)
10519 bandwidth++;
10520
10521 if (bandwidth <= 6100000) {
10522 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10523 } else if ((bandwidth > 6100000)
10524 && (bandwidth <= 7100000)) {
10525 channel->bandwidth = DRX_BANDWIDTH_7MHZ;
10526 } else if (bandwidth > 7100000) {
10527 channel->bandwidth = DRX_BANDWIDTH_8MHZ;
10528 }
10529 break;
10530 default:
10531 return -EINVAL;
10532 }
10533 }
10534
10535
10536
10537
10538 if (standard == DRX_STANDARD_ITU_B) {
10539 switch (channel->constellation) {
10540 case DRX_CONSTELLATION_AUTO:
10541 case DRX_CONSTELLATION_QAM256:
10542 case DRX_CONSTELLATION_QAM64:
10543 break;
10544 default:
10545 return -EINVAL;
10546 }
10547
10548 switch (channel->interleavemode) {
10549 case DRX_INTERLEAVEMODE_I128_J1:
10550 case DRX_INTERLEAVEMODE_I128_J1_V2:
10551 case DRX_INTERLEAVEMODE_I128_J2:
10552 case DRX_INTERLEAVEMODE_I64_J2:
10553 case DRX_INTERLEAVEMODE_I128_J3:
10554 case DRX_INTERLEAVEMODE_I32_J4:
10555 case DRX_INTERLEAVEMODE_I128_J4:
10556 case DRX_INTERLEAVEMODE_I16_J8:
10557 case DRX_INTERLEAVEMODE_I128_J5:
10558 case DRX_INTERLEAVEMODE_I8_J16:
10559 case DRX_INTERLEAVEMODE_I128_J6:
10560 case DRX_INTERLEAVEMODE_I128_J7:
10561 case DRX_INTERLEAVEMODE_I128_J8:
10562 case DRX_INTERLEAVEMODE_I12_J17:
10563 case DRX_INTERLEAVEMODE_I5_J4:
10564 case DRX_INTERLEAVEMODE_B52_M240:
10565 case DRX_INTERLEAVEMODE_B52_M720:
10566 case DRX_INTERLEAVEMODE_UNKNOWN:
10567 case DRX_INTERLEAVEMODE_AUTO:
10568 break;
10569 default:
10570 return -EINVAL;
10571 }
10572 }
10573
10574 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10575
10576 struct drxuio_data uio1 = { DRX_UIO1, false };
10577
10578 switch (channel->bandwidth) {
10579 case DRX_BANDWIDTH_8MHZ:
10580 uio1.value = true;
10581 break;
10582 case DRX_BANDWIDTH_7MHZ:
10583 uio1.value = false;
10584 break;
10585 case DRX_BANDWIDTH_6MHZ:
10586 uio1.value = false;
10587 break;
10588 case DRX_BANDWIDTH_UNKNOWN:
10589 default:
10590 return -EINVAL;
10591 }
10592
10593 rc = ctrl_uio_write(demod, &uio1);
10594 if (rc != 0) {
10595 pr_err("error %d\n", rc);
10596 goto rw_error;
10597 }
10598 }
10599#endif
10600 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10601 if (rc != 0) {
10602 pr_err("error %d\n", rc);
10603 goto rw_error;
10604 }
10605
10606 tuner_freq_offset = 0;
10607
10608
10609 switch (standard) {
10610 case DRX_STANDARD_8VSB:
10611 if (channel->mirror == DRX_MIRROR_AUTO)
10612 ext_attr->mirror = DRX_MIRROR_NO;
10613 else
10614 ext_attr->mirror = channel->mirror;
10615 rc = set_vsb(demod);
10616 if (rc != 0) {
10617 pr_err("error %d\n", rc);
10618 goto rw_error;
10619 }
10620 rc = set_frequency(demod, channel, tuner_freq_offset);
10621 if (rc != 0) {
10622 pr_err("error %d\n", rc);
10623 goto rw_error;
10624 }
10625 break;
10626#ifndef DRXJ_VSB_ONLY
10627 case DRX_STANDARD_ITU_A:
10628 case DRX_STANDARD_ITU_B:
10629 case DRX_STANDARD_ITU_C:
10630 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10631 if (rc != 0) {
10632 pr_err("error %d\n", rc);
10633 goto rw_error;
10634 }
10635 break;
10636#endif
10637 case DRX_STANDARD_UNKNOWN:
10638 default:
10639 return -EIO;
10640 }
10641
10642
10643 ext_attr->reset_pkt_err_acc = true;
10644
10645 return 0;
10646rw_error:
10647 return rc;
10648}
10649
10650
10651
10652
10653
10654
10655
10656
10657
10658
10659
10660
10661
10662
10663
10664
10665static int
10666ctrl_sig_quality(struct drx_demod_instance *demod,
10667 enum drx_lock_status lock_status)
10668{
10669 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
10670 struct drxj_data *ext_attr = demod->my_ext_attr;
10671 struct drx39xxj_state *state = dev_addr->user_data;
10672 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
10673 enum drx_standard standard = ext_attr->standard;
10674 int rc;
10675 u32 ber, cnt, err, pkt;
10676 u16 mer, strength = 0;
10677
10678 rc = get_sig_strength(demod, &strength);
10679 if (rc < 0) {
10680 pr_err("error getting signal strength %d\n", rc);
10681 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10682 } else {
10683 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
10684 p->strength.stat[0].uvalue = 65535UL * strength/ 100;
10685 }
10686
10687 switch (standard) {
10688 case DRX_STANDARD_8VSB:
10689#ifdef DRXJ_SIGNAL_ACCUM_ERR
10690 rc = get_acc_pkt_err(demod, &pkt);
10691 if (rc != 0) {
10692 pr_err("error %d\n", rc);
10693 goto rw_error;
10694 }
10695#endif
10696 if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
10697 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10698 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10699 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10700 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10701 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10702 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10703 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10704 } else {
10705 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10706 if (rc != 0) {
10707 pr_err("error %d getting UCB\n", rc);
10708 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10709 } else {
10710 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
10711 p->block_error.stat[0].uvalue += err;
10712 p->block_count.stat[0].scale = FE_SCALE_COUNTER;
10713 p->block_count.stat[0].uvalue += pkt;
10714 }
10715
10716
10717 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10718 if (rc != 0) {
10719 pr_err("error %d getting pre-ber\n", rc);
10720 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10721 } else {
10722 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10723 p->pre_bit_error.stat[0].uvalue += ber;
10724 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10725 p->pre_bit_count.stat[0].uvalue += cnt;
10726 }
10727
10728 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10729 if (rc != 0) {
10730 pr_err("error %d getting post-ber\n", rc);
10731 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10732 } else {
10733 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10734 p->post_bit_error.stat[0].uvalue += ber;
10735 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10736 p->post_bit_count.stat[0].uvalue += cnt;
10737 }
10738 rc = get_vsbmer(dev_addr, &mer);
10739 if (rc != 0) {
10740 pr_err("error %d getting MER\n", rc);
10741 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10742 } else {
10743 p->cnr.stat[0].svalue = mer * 100;
10744 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
10745 }
10746 }
10747 break;
10748#ifndef DRXJ_VSB_ONLY
10749 case DRX_STANDARD_ITU_A:
10750 case DRX_STANDARD_ITU_B:
10751 case DRX_STANDARD_ITU_C:
10752 rc = ctrl_get_qam_sig_quality(demod);
10753 if (rc != 0) {
10754 pr_err("error %d\n", rc);
10755 goto rw_error;
10756 }
10757 break;
10758#endif
10759 default:
10760 return -EIO;
10761 }
10762
10763 return 0;
10764rw_error:
10765 return rc;
10766}
10767
10768
10769
10770
10771
10772
10773
10774
10775
10776
10777
10778static int
10779ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
10780{
10781 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10782 struct drxj_data *ext_attr = NULL;
10783 struct i2c_device_addr *dev_addr = NULL;
10784 struct drxjscu_cmd cmd_scu = { 0,
10785 0,
10786 0,
10787 NULL,
10788 NULL
10789 };
10790 int rc;
10791 u16 cmd_result[2] = { 0, 0 };
10792 u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
10793
10794
10795 if ((demod == NULL) || (lock_stat == NULL))
10796 return -EINVAL;
10797
10798 dev_addr = demod->my_i2c_dev_addr;
10799 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10800 standard = ext_attr->standard;
10801
10802 *lock_stat = DRX_NOT_LOCKED;
10803
10804
10805 switch (standard) {
10806 case DRX_STANDARD_8VSB:
10807 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
10808 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10809 demod_lock |= 0x6;
10810 break;
10811#ifndef DRXJ_VSB_ONLY
10812 case DRX_STANDARD_ITU_A:
10813 case DRX_STANDARD_ITU_B:
10814 case DRX_STANDARD_ITU_C:
10815 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
10816 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10817 break;
10818#endif
10819 case DRX_STANDARD_UNKNOWN:
10820 default:
10821 return -EIO;
10822 }
10823
10824
10825 cmd_scu.parameter_len = 0;
10826 cmd_scu.result_len = 2;
10827 cmd_scu.parameter = NULL;
10828 cmd_scu.result = cmd_result;
10829 rc = scu_command(dev_addr, &cmd_scu);
10830 if (rc != 0) {
10831 pr_err("error %d\n", rc);
10832 goto rw_error;
10833 }
10834
10835
10836 if (cmd_scu.result[1] < demod_lock) {
10837
10838 *lock_stat = DRX_NOT_LOCKED;
10839 } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
10840 *lock_stat = DRXJ_DEMOD_LOCK;
10841 } else if (cmd_scu.result[1] <
10842 SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
10843
10844 *lock_stat = DRX_LOCKED;
10845 } else {
10846
10847
10848 *lock_stat = DRX_NEVER_LOCK;
10849 }
10850
10851 return 0;
10852rw_error:
10853 return rc;
10854}
10855
10856
10857
10858
10859
10860
10861
10862
10863
10864
10865
10866
10867
10868static int
10869ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
10870{
10871 struct drxj_data *ext_attr = NULL;
10872 int rc;
10873 enum drx_standard prev_standard;
10874
10875
10876 if ((standard == NULL) || (demod == NULL))
10877 return -EINVAL;
10878
10879 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10880 prev_standard = ext_attr->standard;
10881
10882
10883
10884
10885 switch (prev_standard) {
10886#ifndef DRXJ_VSB_ONLY
10887 case DRX_STANDARD_ITU_A:
10888 case DRX_STANDARD_ITU_B:
10889 case DRX_STANDARD_ITU_C:
10890 rc = power_down_qam(demod, false);
10891 if (rc != 0) {
10892 pr_err("error %d\n", rc);
10893 goto rw_error;
10894 }
10895 break;
10896#endif
10897 case DRX_STANDARD_8VSB:
10898 rc = power_down_vsb(demod, false);
10899 if (rc != 0) {
10900 pr_err("error %d\n", rc);
10901 goto rw_error;
10902 }
10903 break;
10904 case DRX_STANDARD_UNKNOWN:
10905
10906 break;
10907 case DRX_STANDARD_AUTO:
10908 default:
10909 return -EINVAL;
10910 }
10911
10912
10913
10914
10915
10916 ext_attr->standard = *standard;
10917
10918 switch (*standard) {
10919#ifndef DRXJ_VSB_ONLY
10920 case DRX_STANDARD_ITU_A:
10921 case DRX_STANDARD_ITU_B:
10922 case DRX_STANDARD_ITU_C:
10923 do {
10924 u16 dummy;
10925 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10926 if (rc != 0) {
10927 pr_err("error %d\n", rc);
10928 goto rw_error;
10929 }
10930 } while (0);
10931 break;
10932#endif
10933 case DRX_STANDARD_8VSB:
10934 rc = set_vsb_leak_n_gain(demod);
10935 if (rc != 0) {
10936 pr_err("error %d\n", rc);
10937 goto rw_error;
10938 }
10939 break;
10940 default:
10941 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10942 return -EINVAL;
10943 break;
10944 }
10945
10946 return 0;
10947rw_error:
10948
10949 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10950 return rc;
10951}
10952
10953
10954
10955static void drxj_reset_mode(struct drxj_data *ext_attr)
10956{
10957
10958 if (ext_attr->has_lna) {
10959
10960#ifndef DRXJ_VSB_ONLY
10961 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10962 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10963 ext_attr->qam_pga_cfg = 140 + (11 * 13);
10964#endif
10965 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10966 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10967 ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10968 } else {
10969
10970#ifndef DRXJ_VSB_ONLY
10971 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10972 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10973 ext_attr->qam_if_agc_cfg.min_output_level = 0;
10974 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10975 ext_attr->qam_if_agc_cfg.speed = 3;
10976 ext_attr->qam_if_agc_cfg.top = 1297;
10977 ext_attr->qam_pga_cfg = 140;
10978#endif
10979 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10980 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10981 ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10982 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10983 ext_attr->vsb_if_agc_cfg.speed = 3;
10984 ext_attr->vsb_if_agc_cfg.top = 1024;
10985 ext_attr->vsb_pga_cfg = 140;
10986 }
10987
10988
10989#ifndef DRXJ_VSB_ONLY
10990 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
10991 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10992 ext_attr->qam_rf_agc_cfg.min_output_level = 0;
10993 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
10994 ext_attr->qam_rf_agc_cfg.speed = 3;
10995 ext_attr->qam_rf_agc_cfg.top = 9500;
10996 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
10997 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
10998 ext_attr->qam_pre_saw_cfg.reference = 0x07;
10999 ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
11000#endif
11001
11002 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
11003 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11004 ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
11005 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11006 ext_attr->vsb_rf_agc_cfg.speed = 3;
11007 ext_attr->vsb_rf_agc_cfg.top = 9500;
11008 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11009 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11010 ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11011 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11012}
11013
11014
11015
11016
11017
11018
11019
11020
11021
11022
11023
11024
11025
11026static int
11027ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
11028{
11029 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
11030 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
11031 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
11032 int rc;
11033 u16 sio_cc_pwd_mode = 0;
11034
11035 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11036 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11037 dev_addr = demod->my_i2c_dev_addr;
11038
11039
11040 if (mode == NULL)
11041 return -EINVAL;
11042
11043
11044 if (common_attr->current_power_mode == *mode)
11045 return 0;
11046
11047 switch (*mode) {
11048 case DRX_POWER_UP:
11049 case DRXJ_POWER_DOWN_MAIN_PATH:
11050 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
11051 break;
11052 case DRXJ_POWER_DOWN_CORE:
11053 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
11054 break;
11055 case DRXJ_POWER_DOWN_PLL:
11056 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
11057 break;
11058 case DRX_POWER_DOWN:
11059 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
11060 break;
11061 default:
11062
11063 return -EINVAL;
11064 break;
11065 }
11066
11067
11068 if ((common_attr->current_power_mode != DRX_POWER_UP)) {
11069 rc = power_up_device(demod);
11070 if (rc != 0) {
11071 pr_err("error %d\n", rc);
11072 goto rw_error;
11073 }
11074 }
11075
11076 if ((*mode == DRX_POWER_UP)) {
11077
11078
11079
11080 drxj_reset_mode(ext_attr);
11081 } else {
11082
11083
11084
11085
11086
11087
11088
11089
11090
11091
11092
11093 switch (ext_attr->standard) {
11094 case DRX_STANDARD_ITU_A:
11095 case DRX_STANDARD_ITU_B:
11096 case DRX_STANDARD_ITU_C:
11097 rc = power_down_qam(demod, true);
11098 if (rc != 0) {
11099 pr_err("error %d\n", rc);
11100 goto rw_error;
11101 }
11102 break;
11103 case DRX_STANDARD_8VSB:
11104 rc = power_down_vsb(demod, true);
11105 if (rc != 0) {
11106 pr_err("error %d\n", rc);
11107 goto rw_error;
11108 }
11109 break;
11110 case DRX_STANDARD_PAL_SECAM_BG:
11111 case DRX_STANDARD_PAL_SECAM_DK:
11112 case DRX_STANDARD_PAL_SECAM_I:
11113 case DRX_STANDARD_PAL_SECAM_L:
11114 case DRX_STANDARD_PAL_SECAM_LP:
11115 case DRX_STANDARD_NTSC:
11116 case DRX_STANDARD_FM:
11117 rc = power_down_atv(demod, ext_attr->standard, true);
11118 if (rc != 0) {
11119 pr_err("error %d\n", rc);
11120 goto rw_error;
11121 }
11122 break;
11123 case DRX_STANDARD_UNKNOWN:
11124
11125 break;
11126 case DRX_STANDARD_AUTO:
11127 default:
11128 return -EIO;
11129 }
11130 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11131 }
11132
11133 if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
11134 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11135 if (rc != 0) {
11136 pr_err("error %d\n", rc);
11137 goto rw_error;
11138 }
11139 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11140 if (rc != 0) {
11141 pr_err("error %d\n", rc);
11142 goto rw_error;
11143 }
11144
11145 if ((*mode != DRX_POWER_UP)) {
11146
11147 rc = init_hi(demod);
11148 if (rc != 0) {
11149 pr_err("error %d\n", rc);
11150 goto rw_error;
11151 }
11152
11153 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11154 rc = hi_cfg_command(demod);
11155 if (rc != 0) {
11156 pr_err("error %d\n", rc);
11157 goto rw_error;
11158 }
11159 }
11160 }
11161
11162 common_attr->current_power_mode = *mode;
11163
11164 return 0;
11165rw_error:
11166 return rc;
11167}
11168
11169
11170
11171
11172
11173
11174
11175
11176
11177
11178
11179
11180
11181
11182
11183
11184static int
11185ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
11186{
11187 struct i2c_device_addr *dev_addr = NULL;
11188 struct drxj_data *ext_attr = NULL;
11189 int rc;
11190
11191 dev_addr = demod->my_i2c_dev_addr;
11192 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11193
11194
11195 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
11196 ) {
11197 return -EINVAL;
11198 }
11199
11200
11201 if ((ext_attr->standard == pre_saw->standard) ||
11202 (DRXJ_ISQAMSTD(ext_attr->standard) &&
11203 DRXJ_ISQAMSTD(pre_saw->standard)) ||
11204 (DRXJ_ISATVSTD(ext_attr->standard) &&
11205 DRXJ_ISATVSTD(pre_saw->standard))) {
11206 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11207 if (rc != 0) {
11208 pr_err("error %d\n", rc);
11209 goto rw_error;
11210 }
11211 }
11212
11213
11214 switch (pre_saw->standard) {
11215 case DRX_STANDARD_8VSB:
11216 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11217 break;
11218#ifndef DRXJ_VSB_ONLY
11219 case DRX_STANDARD_ITU_A:
11220 case DRX_STANDARD_ITU_B:
11221 case DRX_STANDARD_ITU_C:
11222 ext_attr->qam_pre_saw_cfg = *pre_saw;
11223 break;
11224#endif
11225 default:
11226 return -EINVAL;
11227 }
11228
11229 return 0;
11230rw_error:
11231 return rc;
11232}
11233
11234
11235
11236
11237
11238
11239
11240
11241
11242
11243
11244
11245
11246
11247static int
11248ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
11249{
11250 struct i2c_device_addr *dev_addr = NULL;
11251 struct drxj_data *ext_attr = NULL;
11252 int rc;
11253 u8 gain = 0;
11254
11255
11256 if (afe_gain == NULL)
11257 return -EINVAL;
11258
11259 dev_addr = demod->my_i2c_dev_addr;
11260 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11261
11262 switch (afe_gain->standard) {
11263 case DRX_STANDARD_8VSB:
11264#ifndef DRXJ_VSB_ONLY
11265 case DRX_STANDARD_ITU_A:
11266 case DRX_STANDARD_ITU_B:
11267 case DRX_STANDARD_ITU_C:
11268#endif
11269
11270 break;
11271 default:
11272 return -EINVAL;
11273 }
11274
11275
11276
11277
11278 if (afe_gain->gain >= 329)
11279 gain = 15;
11280 else if (afe_gain->gain <= 147)
11281 gain = 0;
11282 else
11283 gain = (afe_gain->gain - 140 + 6) / 13;
11284
11285
11286 if (ext_attr->standard == afe_gain->standard) {
11287 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11288 if (rc != 0) {
11289 pr_err("error %d\n", rc);
11290 goto rw_error;
11291 }
11292 }
11293
11294
11295 switch (afe_gain->standard) {
11296 case DRX_STANDARD_8VSB:
11297 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11298 break;
11299#ifndef DRXJ_VSB_ONLY
11300 case DRX_STANDARD_ITU_A:
11301 case DRX_STANDARD_ITU_B:
11302 case DRX_STANDARD_ITU_C:
11303 ext_attr->qam_pga_cfg = gain * 13 + 140;
11304 break;
11305#endif
11306 default:
11307 return -EIO;
11308 }
11309
11310 return 0;
11311rw_error:
11312 return rc;
11313}
11314
11315
11316
11317
11318
11319
11320
11321static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11322 struct drxu_code_info *mc_info,
11323 enum drxu_code_action action);
11324static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
11325
11326
11327
11328
11329
11330
11331
11332
11333
11334
11335
11336
11337static int drxj_open(struct drx_demod_instance *demod)
11338{
11339 struct i2c_device_addr *dev_addr = NULL;
11340 struct drxj_data *ext_attr = NULL;
11341 struct drx_common_attr *common_attr = NULL;
11342 u32 driver_version = 0;
11343 struct drxu_code_info ucode_info;
11344 struct drx_cfg_mpeg_output cfg_mpeg_output;
11345 int rc;
11346 enum drx_power_mode power_mode = DRX_POWER_UP;
11347
11348 if ((demod == NULL) ||
11349 (demod->my_common_attr == NULL) ||
11350 (demod->my_ext_attr == NULL) ||
11351 (demod->my_i2c_dev_addr == NULL) ||
11352 (demod->my_common_attr->is_opened)) {
11353 return -EINVAL;
11354 }
11355
11356
11357 if (demod->my_ext_attr == NULL)
11358 return -EINVAL;
11359
11360 dev_addr = demod->my_i2c_dev_addr;
11361 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11362 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11363
11364 rc = ctrl_power_mode(demod, &power_mode);
11365 if (rc != 0) {
11366 pr_err("error %d\n", rc);
11367 goto rw_error;
11368 }
11369 if (power_mode != DRX_POWER_UP) {
11370 rc = -EINVAL;
11371 pr_err("failed to powerup device\n");
11372 goto rw_error;
11373 }
11374
11375
11376 rc = get_device_capabilities(demod);
11377 if (rc != 0) {
11378 pr_err("error %d\n", rc);
11379 goto rw_error;
11380 }
11381
11382
11383
11384
11385
11386
11387
11388
11389
11390 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11391 if (rc != 0) {
11392 pr_err("error %d\n", rc);
11393 goto rw_error;
11394 }
11395 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11396 if (rc != 0) {
11397 pr_err("error %d\n", rc);
11398 goto rw_error;
11399 }
11400 msleep(1);
11401
11402
11403
11404 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11405 if (rc != 0) {
11406 pr_err("error %d\n", rc);
11407 goto rw_error;
11408 }
11409
11410 rc = set_iqm_af(demod, false);
11411 if (rc != 0) {
11412 pr_err("error %d\n", rc);
11413 goto rw_error;
11414 }
11415 rc = set_orx_nsu_aox(demod, false);
11416 if (rc != 0) {
11417 pr_err("error %d\n", rc);
11418 goto rw_error;
11419 }
11420
11421 rc = init_hi(demod);
11422 if (rc != 0) {
11423 pr_err("error %d\n", rc);
11424 goto rw_error;
11425 }
11426
11427
11428 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
11429 cfg_mpeg_output.enable_mpeg_output = false;
11430
11431 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11432 if (rc != 0) {
11433 pr_err("error %d\n", rc);
11434 goto rw_error;
11435 }
11436
11437 rc = power_down_aud(demod);
11438 if (rc != 0) {
11439 pr_err("error %d\n", rc);
11440 goto rw_error;
11441 }
11442
11443 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11444 if (rc != 0) {
11445 pr_err("error %d\n", rc);
11446 goto rw_error;
11447 }
11448
11449
11450 if (common_attr->microcode_file != NULL) {
11451
11452
11453 common_attr->is_opened = true;
11454 ucode_info.mc_file = common_attr->microcode_file;
11455
11456 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
11457 pr_err("Should powerup before loading the firmware.");
11458 return -EINVAL;
11459 }
11460
11461 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11462 if (rc != 0) {
11463 pr_err("error %d while uploading the firmware\n", rc);
11464 goto rw_error;
11465 }
11466 if (common_attr->verify_microcode == true) {
11467 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11468 if (rc != 0) {
11469 pr_err("error %d while verifying the firmware\n",
11470 rc);
11471 goto rw_error;
11472 }
11473 }
11474 common_attr->is_opened = false;
11475 }
11476
11477
11478 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11479 if (rc != 0) {
11480 pr_err("error %d\n", rc);
11481 goto rw_error;
11482 }
11483
11484
11485 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
11486 common_attr->scan_desired_lock = DRX_LOCKED;
11487
11488 drxj_reset_mode(ext_attr);
11489 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11490
11491 rc = smart_ant_init(demod);
11492 if (rc != 0) {
11493 pr_err("error %d\n", rc);
11494 goto rw_error;
11495 }
11496
11497
11498
11499
11500
11501 driver_version = (VERSION_MAJOR / 100) % 10;
11502 driver_version <<= 4;
11503 driver_version += (VERSION_MAJOR / 10) % 10;
11504 driver_version <<= 4;
11505 driver_version += (VERSION_MAJOR % 10);
11506 driver_version <<= 4;
11507 driver_version += (VERSION_MINOR % 10);
11508 driver_version <<= 4;
11509 driver_version += (VERSION_PATCH / 1000) % 10;
11510 driver_version <<= 4;
11511 driver_version += (VERSION_PATCH / 100) % 10;
11512 driver_version <<= 4;
11513 driver_version += (VERSION_PATCH / 10) % 10;
11514 driver_version <<= 4;
11515 driver_version += (VERSION_PATCH % 10);
11516 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11517 if (rc != 0) {
11518 pr_err("error %d\n", rc);
11519 goto rw_error;
11520 }
11521 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11522 if (rc != 0) {
11523 pr_err("error %d\n", rc);
11524 goto rw_error;
11525 }
11526
11527 rc = ctrl_set_oob(demod, NULL);
11528 if (rc != 0) {
11529 pr_err("error %d\n", rc);
11530 goto rw_error;
11531 }
11532
11533
11534 ext_attr->aud_data = drxj_default_aud_data_g;
11535
11536 demod->my_common_attr->is_opened = true;
11537 drxj_set_lna_state(demod, false);
11538 return 0;
11539rw_error:
11540 common_attr->is_opened = false;
11541 return rc;
11542}
11543
11544
11545
11546
11547
11548
11549
11550
11551static int drxj_close(struct drx_demod_instance *demod)
11552{
11553 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11554 int rc;
11555 enum drx_power_mode power_mode = DRX_POWER_UP;
11556
11557 if ((demod->my_common_attr == NULL) ||
11558 (demod->my_ext_attr == NULL) ||
11559 (demod->my_i2c_dev_addr == NULL) ||
11560 (!demod->my_common_attr->is_opened)) {
11561 return -EINVAL;
11562 }
11563
11564
11565 rc = ctrl_power_mode(demod, &power_mode);
11566 if (rc != 0) {
11567 pr_err("error %d\n", rc);
11568 goto rw_error;
11569 }
11570
11571 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11572 if (rc != 0) {
11573 pr_err("error %d\n", rc);
11574 goto rw_error;
11575 }
11576 power_mode = DRX_POWER_DOWN;
11577 rc = ctrl_power_mode(demod, &power_mode);
11578 if (rc != 0) {
11579 pr_err("error %d\n", rc);
11580 goto rw_error;
11581 }
11582
11583 DRX_ATTR_ISOPENED(demod) = false;
11584
11585 return 0;
11586rw_error:
11587 DRX_ATTR_ISOPENED(demod) = false;
11588
11589 return rc;
11590}
11591
11592
11593
11594
11595
11596
11597
11598
11599
11600
11601
11602
11603static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
11604{
11605 u16 i = 0;
11606 u16 j = 0;
11607 u32 crc_word = 0;
11608 u32 carry = 0;
11609
11610 while (i < nr_words) {
11611 crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
11612 for (j = 0; j < 16; j++) {
11613 crc_word <<= 1;
11614 if (carry != 0)
11615 crc_word ^= 0x80050000UL;
11616 carry = crc_word & 0x80000000UL;
11617 }
11618 i++;
11619 block_data += (sizeof(u16));
11620 }
11621 return (u16)(crc_word >> 16);
11622}
11623
11624
11625
11626
11627
11628
11629
11630
11631static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
11632 unsigned size)
11633{
11634 struct drxu_code_block_hdr block_hdr;
11635 int i;
11636 unsigned count = 2 * sizeof(u16);
11637 u32 mc_dev_type, mc_version, mc_base_version;
11638 u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
11639
11640
11641
11642
11643
11644
11645
11646 DRX_ATTR_MCRECORD(demod).aux_type = 0;
11647 DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
11648 DRX_ATTR_MCRECORD(demod).mc_version = 0;
11649 DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
11650
11651 for (i = 0; i < mc_nr_of_blks; i++) {
11652 if (count + 3 * sizeof(u16) + sizeof(u32) > size)
11653 goto eof;
11654
11655
11656 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
11657 count += sizeof(u32);
11658 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
11659 count += sizeof(u16);
11660 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
11661 count += sizeof(u16);
11662 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
11663 count += sizeof(u16);
11664
11665 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11666 count, block_hdr.addr, block_hdr.size, block_hdr.flags,
11667 block_hdr.CRC);
11668
11669 if (block_hdr.flags & 0x8) {
11670 u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
11671 u16 auxtype;
11672
11673 if (block_hdr.addr + sizeof(u16) > size)
11674 goto eof;
11675
11676 auxtype = be16_to_cpu(*(__be16 *)(auxblk));
11677
11678
11679 if (DRX_ISMCVERTYPE(auxtype)) {
11680 if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
11681 goto eof;
11682
11683 auxblk += sizeof(u16);
11684 mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
11685 auxblk += sizeof(u32);
11686 mc_version = be32_to_cpu(*(__be32 *)(auxblk));
11687 auxblk += sizeof(u32);
11688 mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
11689
11690 DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
11691 DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
11692 DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
11693 DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
11694
11695 pr_info("Firmware dev %x, ver %x, base ver %x\n",
11696 mc_dev_type, mc_version, mc_base_version);
11697
11698 }
11699 } else if (count + block_hdr.size * sizeof(u16) > size)
11700 goto eof;
11701
11702 count += block_hdr.size * sizeof(u16);
11703 }
11704 return 0;
11705eof:
11706 pr_err("Firmware is truncated at pos %u/%u\n", count, size);
11707 return -EINVAL;
11708}
11709
11710
11711
11712
11713
11714
11715
11716
11717
11718
11719
11720
11721
11722
11723
11724
11725
11726
11727
11728
11729static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11730 struct drxu_code_info *mc_info,
11731 enum drxu_code_action action)
11732{
11733 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11734 int rc;
11735 u16 i = 0;
11736 u16 mc_nr_of_blks = 0;
11737 u16 mc_magic_word = 0;
11738 const u8 *mc_data_init = NULL;
11739 u8 *mc_data = NULL;
11740 unsigned size;
11741 char *mc_file;
11742
11743
11744 if (!mc_info || !mc_info->mc_file)
11745 return -EINVAL;
11746
11747 mc_file = mc_info->mc_file;
11748
11749 if (!demod->firmware) {
11750 const struct firmware *fw = NULL;
11751
11752 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11753 if (rc < 0) {
11754 pr_err("Couldn't read firmware %s\n", mc_file);
11755 return rc;
11756 }
11757 demod->firmware = fw;
11758
11759 if (demod->firmware->size < 2 * sizeof(u16)) {
11760 rc = -EINVAL;
11761 pr_err("Firmware is too short!\n");
11762 goto release;
11763 }
11764
11765 pr_info("Firmware %s, size %zu\n",
11766 mc_file, demod->firmware->size);
11767 }
11768
11769 mc_data_init = demod->firmware->data;
11770 size = demod->firmware->size;
11771
11772 mc_data = (void *)mc_data_init;
11773
11774 mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
11775 mc_data += sizeof(u16);
11776 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
11777 mc_data += sizeof(u16);
11778
11779 if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
11780 rc = -EINVAL;
11781 pr_err("Firmware magic word doesn't match\n");
11782 goto release;
11783 }
11784
11785 if (action == UCODE_UPLOAD) {
11786 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11787 if (rc)
11788 goto release;
11789 pr_info("Uploading firmware %s\n", mc_file);
11790 } else {
11791 pr_info("Verifying if firmware upload was ok.\n");
11792 }
11793
11794
11795 for (i = 0; i < mc_nr_of_blks; i++) {
11796 struct drxu_code_block_hdr block_hdr;
11797 u16 mc_block_nr_bytes = 0;
11798
11799
11800 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
11801 mc_data += sizeof(u32);
11802 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
11803 mc_data += sizeof(u16);
11804 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
11805 mc_data += sizeof(u16);
11806 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
11807 mc_data += sizeof(u16);
11808
11809 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11810 (unsigned)(mc_data - mc_data_init), block_hdr.addr,
11811 block_hdr.size, block_hdr.flags, block_hdr.CRC);
11812
11813
11814
11815
11816
11817 if ((block_hdr.size > 0x7FFF) ||
11818 (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
11819 (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
11820 ) {
11821
11822 rc = -EINVAL;
11823 pr_err("firmware CRC is wrong\n");
11824 goto release;
11825 }
11826
11827 if (!block_hdr.size)
11828 continue;
11829
11830 mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
11831
11832
11833 switch (action) {
11834 case UCODE_UPLOAD:
11835 if (drxdap_fasi_write_block(dev_addr,
11836 block_hdr.addr,
11837 mc_block_nr_bytes,
11838 mc_data, 0x0000)) {
11839 rc = -EIO;
11840 pr_err("error writing firmware at pos %u\n",
11841 (unsigned)(mc_data - mc_data_init));
11842 goto release;
11843 }
11844 break;
11845 case UCODE_VERIFY: {
11846 int result = 0;
11847 u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
11848 u32 bytes_to_comp = 0;
11849 u32 bytes_left = mc_block_nr_bytes;
11850 u32 curr_addr = block_hdr.addr;
11851 u8 *curr_ptr = mc_data;
11852
11853 while (bytes_left != 0) {
11854 if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
11855 bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
11856 else
11857 bytes_to_comp = bytes_left;
11858
11859 if (drxdap_fasi_read_block(dev_addr,
11860 curr_addr,
11861 (u16)bytes_to_comp,
11862 (u8 *)mc_data_buffer,
11863 0x0000)) {
11864 pr_err("error reading firmware at pos %u\n",
11865 (unsigned)(mc_data - mc_data_init));
11866 return -EIO;
11867 }
11868
11869 result = memcmp(curr_ptr, mc_data_buffer,
11870 bytes_to_comp);
11871
11872 if (result) {
11873 pr_err("error verifying firmware at pos %u\n",
11874 (unsigned)(mc_data - mc_data_init));
11875 return -EIO;
11876 }
11877
11878 curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
11879 curr_ptr =&(curr_ptr[bytes_to_comp]);
11880 bytes_left -=((u32) bytes_to_comp);
11881 }
11882 break;
11883 }
11884 default:
11885 return -EINVAL;
11886 break;
11887
11888 }
11889 mc_data += mc_block_nr_bytes;
11890 }
11891
11892 return 0;
11893
11894release:
11895 release_firmware(demod->firmware);
11896 demod->firmware = NULL;
11897
11898 return rc;
11899}
11900
11901
11902static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
11903{
11904 struct drxuio_cfg uio_cfg;
11905 struct drxuio_data uio_data;
11906 int result;
11907
11908 uio_cfg.uio = DRX_UIO1;
11909 uio_cfg.mode = DRX_UIO_MODE_READWRITE;
11910
11911 result = ctrl_set_uio_cfg(demod, &uio_cfg);
11912 if (result) {
11913 pr_err("Failed to setup LNA GPIO!\n");
11914 return result;
11915 }
11916
11917 uio_data.uio = DRX_UIO1;
11918 uio_data.value = state;
11919 result = ctrl_uio_write(demod, &uio_data);
11920 if (result != 0) {
11921 pr_err("Failed to %sable LNA!\n",
11922 state ? "en" : "dis");
11923 return result;
11924 }
11925 return 0;
11926}
11927
11928
11929
11930
11931
11932
11933
11934static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
11935{
11936 struct drx39xxj_state *state = fe->demodulator_priv;
11937 struct drx_demod_instance *demod = state->demod;
11938 int result;
11939 enum drx_power_mode power_mode;
11940
11941 if (enable)
11942 power_mode = DRX_POWER_UP;
11943 else
11944 power_mode = DRX_POWER_DOWN;
11945
11946 result = ctrl_power_mode(demod, &power_mode);
11947 if (result != 0) {
11948 pr_err("Power state change failed\n");
11949 return 0;
11950 }
11951
11952 return 0;
11953}
11954
11955static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status)
11956{
11957 struct drx39xxj_state *state = fe->demodulator_priv;
11958 struct drx_demod_instance *demod = state->demod;
11959 int result;
11960 enum drx_lock_status lock_status;
11961
11962 *status = 0;
11963
11964 result = ctrl_lock_status(demod, &lock_status);
11965 if (result != 0) {
11966 pr_err("drx39xxj: could not get lock status!\n");
11967 *status = 0;
11968 }
11969
11970 switch (lock_status) {
11971 case DRX_NEVER_LOCK:
11972 *status = 0;
11973 pr_err("drx says NEVER_LOCK\n");
11974 break;
11975 case DRX_NOT_LOCKED:
11976 *status = 0;
11977 break;
11978 case DRX_LOCK_STATE_1:
11979 case DRX_LOCK_STATE_2:
11980 case DRX_LOCK_STATE_3:
11981 case DRX_LOCK_STATE_4:
11982 case DRX_LOCK_STATE_5:
11983 case DRX_LOCK_STATE_6:
11984 case DRX_LOCK_STATE_7:
11985 case DRX_LOCK_STATE_8:
11986 case DRX_LOCK_STATE_9:
11987 *status = FE_HAS_SIGNAL
11988 | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
11989 break;
11990 case DRX_LOCKED:
11991 *status = FE_HAS_SIGNAL
11992 | FE_HAS_CARRIER
11993 | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
11994 break;
11995 default:
11996 pr_err("Lock state unknown %d\n", lock_status);
11997 }
11998 ctrl_sig_quality(demod, lock_status);
11999
12000 return 0;
12001}
12002
12003static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
12004{
12005 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12006
12007 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12008 *ber = 0;
12009 return 0;
12010 }
12011
12012 if (!p->pre_bit_count.stat[0].uvalue) {
12013 if (!p->pre_bit_error.stat[0].uvalue)
12014 *ber = 0;
12015 else
12016 *ber = 1000000;
12017 } else {
12018 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
12019 p->pre_bit_count.stat[0].uvalue);
12020 }
12021 return 0;
12022}
12023
12024static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
12025 u16 *strength)
12026{
12027 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12028
12029 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12030 *strength = 0;
12031 return 0;
12032 }
12033
12034 *strength = p->strength.stat[0].uvalue;
12035 return 0;
12036}
12037
12038static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
12039{
12040 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12041 u64 tmp64;
12042
12043 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12044 *snr = 0;
12045 return 0;
12046 }
12047
12048 tmp64 = p->cnr.stat[0].svalue;
12049 do_div(tmp64, 10);
12050 *snr = tmp64;
12051 return 0;
12052}
12053
12054static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
12055{
12056 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12057
12058 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12059 *ucb = 0;
12060 return 0;
12061 }
12062
12063 *ucb = p->block_error.stat[0].uvalue;
12064 return 0;
12065}
12066
12067static int drx39xxj_set_frontend(struct dvb_frontend *fe)
12068{
12069#ifdef DJH_DEBUG
12070 int i;
12071#endif
12072 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12073 struct drx39xxj_state *state = fe->demodulator_priv;
12074 struct drx_demod_instance *demod = state->demod;
12075 enum drx_standard standard = DRX_STANDARD_8VSB;
12076 struct drx_channel channel;
12077 int result;
12078 static const struct drx_channel def_channel = {
12079 0,
12080 DRX_BANDWIDTH_6MHZ,
12081 DRX_MIRROR_NO,
12082 DRX_CONSTELLATION_AUTO,
12083 DRX_HIERARCHY_UNKNOWN,
12084 DRX_PRIORITY_UNKNOWN,
12085 DRX_CODERATE_UNKNOWN,
12086 DRX_GUARD_UNKNOWN,
12087 DRX_FFTMODE_UNKNOWN,
12088 DRX_CLASSIFICATION_AUTO,
12089 5057000,
12090 DRX_INTERLEAVEMODE_UNKNOWN,
12091 DRX_LDPC_UNKNOWN,
12092 DRX_CARRIER_UNKNOWN,
12093 DRX_FRAMEMODE_UNKNOWN
12094 };
12095 u32 constellation = DRX_CONSTELLATION_AUTO;
12096
12097
12098 drx39xxj_set_powerstate(fe, 1);
12099
12100 if (fe->ops.tuner_ops.set_params) {
12101 u32 int_freq;
12102
12103 if (fe->ops.i2c_gate_ctrl)
12104 fe->ops.i2c_gate_ctrl(fe, 1);
12105
12106
12107 fe->ops.tuner_ops.set_params(fe);
12108
12109
12110 if (fe->ops.tuner_ops.get_if_frequency) {
12111 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
12112 demod->my_common_attr->intermediate_freq = int_freq / 1000;
12113 }
12114
12115 if (fe->ops.i2c_gate_ctrl)
12116 fe->ops.i2c_gate_ctrl(fe, 0);
12117 }
12118
12119 switch (p->delivery_system) {
12120 case SYS_ATSC:
12121 standard = DRX_STANDARD_8VSB;
12122 break;
12123 case SYS_DVBC_ANNEX_B:
12124 standard = DRX_STANDARD_ITU_B;
12125
12126 switch (p->modulation) {
12127 case QAM_64:
12128 constellation = DRX_CONSTELLATION_QAM64;
12129 break;
12130 case QAM_256:
12131 constellation = DRX_CONSTELLATION_QAM256;
12132 break;
12133 default:
12134 constellation = DRX_CONSTELLATION_AUTO;
12135 break;
12136 }
12137 break;
12138 default:
12139 return -EINVAL;
12140 }
12141
12142 result = ctrl_set_standard(demod, &standard);
12143 if (result != 0) {
12144 pr_err("Failed to set standard! result=%02x\n",
12145 result);
12146 return -EINVAL;
12147 }
12148
12149
12150 channel = def_channel;
12151 channel.frequency = p->frequency / 1000;
12152 channel.bandwidth = DRX_BANDWIDTH_6MHZ;
12153 channel.constellation = constellation;
12154
12155
12156 result = ctrl_set_channel(demod, &channel);
12157 if (result != 0) {
12158 pr_err("Failed to set channel!\n");
12159 return -EINVAL;
12160 }
12161
12162 drxj_set_lna_state(demod, false);
12163
12164
12165 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12166
12167 return 0;
12168}
12169
12170static int drx39xxj_sleep(struct dvb_frontend *fe)
12171{
12172
12173 return drx39xxj_set_powerstate(fe, 0);
12174}
12175
12176static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
12177{
12178 struct drx39xxj_state *state = fe->demodulator_priv;
12179 struct drx_demod_instance *demod = state->demod;
12180 bool i2c_gate_state;
12181 int result;
12182
12183#ifdef DJH_DEBUG
12184 pr_debug("i2c gate call: enable=%d state=%d\n", enable,
12185 state->i2c_gate_open);
12186#endif
12187
12188 if (enable)
12189 i2c_gate_state = true;
12190 else
12191 i2c_gate_state = false;
12192
12193 if (state->i2c_gate_open == enable) {
12194
12195 return 0;
12196 }
12197
12198 result = ctrl_i2c_bridge(demod, &i2c_gate_state);
12199 if (result != 0) {
12200 pr_err("drx39xxj: could not open i2c gate [%d]\n",
12201 result);
12202 dump_stack();
12203 } else {
12204 state->i2c_gate_open = enable;
12205 }
12206 return 0;
12207}
12208
12209static int drx39xxj_init(struct dvb_frontend *fe)
12210{
12211 struct drx39xxj_state *state = fe->demodulator_priv;
12212 struct drx_demod_instance *demod = state->demod;
12213 int rc = 0;
12214
12215 if (fe->exit == DVB_FE_DEVICE_RESUME) {
12216
12217 demod->my_common_attr->is_opened = false;
12218 rc = drxj_open(demod);
12219 if (rc != 0)
12220 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12221 } else
12222 drx39xxj_set_powerstate(fe, 1);
12223
12224 return rc;
12225}
12226
12227static int drx39xxj_set_lna(struct dvb_frontend *fe)
12228{
12229 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
12230 struct drx39xxj_state *state = fe->demodulator_priv;
12231 struct drx_demod_instance *demod = state->demod;
12232 struct drxj_data *ext_attr = demod->my_ext_attr;
12233
12234 if (c->lna) {
12235 if (!ext_attr->has_lna) {
12236 pr_err("LNA is not supported on this device!\n");
12237 return -EINVAL;
12238
12239 }
12240 }
12241
12242 return drxj_set_lna_state(demod, c->lna);
12243}
12244
12245static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
12246 struct dvb_frontend_tune_settings *tune)
12247{
12248 tune->min_delay_ms = 1000;
12249 return 0;
12250}
12251
12252static void drx39xxj_release(struct dvb_frontend *fe)
12253{
12254 struct drx39xxj_state *state = fe->demodulator_priv;
12255 struct drx_demod_instance *demod = state->demod;
12256
12257
12258 if (fe->exit != DVB_FE_DEVICE_REMOVED)
12259 drxj_close(demod);
12260
12261 kfree(demod->my_ext_attr);
12262 kfree(demod->my_common_attr);
12263 kfree(demod->my_i2c_dev_addr);
12264 release_firmware(demod->firmware);
12265 kfree(demod);
12266 kfree(state);
12267}
12268
12269static const struct dvb_frontend_ops drx39xxj_ops;
12270
12271struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
12272{
12273 struct drx39xxj_state *state = NULL;
12274 struct i2c_device_addr *demod_addr = NULL;
12275 struct drx_common_attr *demod_comm_attr = NULL;
12276 struct drxj_data *demod_ext_attr = NULL;
12277 struct drx_demod_instance *demod = NULL;
12278 struct dtv_frontend_properties *p;
12279 int result;
12280
12281
12282 state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
12283 if (state == NULL)
12284 goto error;
12285
12286 demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL);
12287 if (demod == NULL)
12288 goto error;
12289
12290 demod_addr = kmemdup(&drxj_default_addr_g,
12291 sizeof(struct i2c_device_addr), GFP_KERNEL);
12292 if (demod_addr == NULL)
12293 goto error;
12294
12295 demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
12296 sizeof(struct drx_common_attr), GFP_KERNEL);
12297 if (demod_comm_attr == NULL)
12298 goto error;
12299
12300 demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
12301 GFP_KERNEL);
12302 if (demod_ext_attr == NULL)
12303 goto error;
12304
12305
12306 state->i2c = i2c;
12307 state->demod = demod;
12308
12309
12310 memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance));
12311
12312 demod->my_i2c_dev_addr = demod_addr;
12313 demod->my_common_attr = demod_comm_attr;
12314 demod->my_i2c_dev_addr->user_data = state;
12315 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
12316 demod->my_common_attr->verify_microcode = true;
12317 demod->my_common_attr->intermediate_freq = 5000;
12318 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
12319 demod->my_ext_attr = demod_ext_attr;
12320 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
12321 demod->i2c = i2c;
12322
12323 result = drxj_open(demod);
12324 if (result != 0) {
12325 pr_err("DRX open failed! Aborting\n");
12326 goto error;
12327 }
12328
12329
12330 memcpy(&state->frontend.ops, &drx39xxj_ops,
12331 sizeof(struct dvb_frontend_ops));
12332
12333 state->frontend.demodulator_priv = state;
12334
12335
12336 p = &state->frontend.dtv_property_cache;
12337 p->strength.len = 1;
12338 p->pre_bit_count.len = 1;
12339 p->pre_bit_error.len = 1;
12340 p->post_bit_count.len = 1;
12341 p->post_bit_error.len = 1;
12342 p->block_count.len = 1;
12343 p->block_error.len = 1;
12344 p->cnr.len = 1;
12345
12346 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12347 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12348 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12349 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12350 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12351 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12352 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12353 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12354
12355 return &state->frontend;
12356
12357error:
12358 kfree(demod_ext_attr);
12359 kfree(demod_comm_attr);
12360 kfree(demod_addr);
12361 kfree(demod);
12362 kfree(state);
12363
12364 return NULL;
12365}
12366EXPORT_SYMBOL(drx39xxj_attach);
12367
12368static const struct dvb_frontend_ops drx39xxj_ops = {
12369 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
12370 .info = {
12371 .name = "Micronas DRX39xxj family Frontend",
12372 .frequency_stepsize = 62500,
12373 .frequency_min = 51000000,
12374 .frequency_max = 858000000,
12375 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
12376 },
12377
12378 .init = drx39xxj_init,
12379 .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
12380 .sleep = drx39xxj_sleep,
12381 .set_frontend = drx39xxj_set_frontend,
12382 .get_tune_settings = drx39xxj_get_tune_settings,
12383 .read_status = drx39xxj_read_status,
12384 .read_ber = drx39xxj_read_ber,
12385 .read_signal_strength = drx39xxj_read_signal_strength,
12386 .read_snr = drx39xxj_read_snr,
12387 .read_ucblocks = drx39xxj_read_ucblocks,
12388 .release = drx39xxj_release,
12389 .set_lna = drx39xxj_set_lna,
12390};
12391
12392MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
12393MODULE_AUTHOR("Devin Heitmueller");
12394MODULE_LICENSE("GPL");
12395MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE);
12396