linux/drivers/mmc/host/s3cmci.c
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   1/*
   2 *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3 *
   4 *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5 *
   6 * Current driver maintained by Ben Dooks and Simtec Electronics
   7 *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13
  14#include <linux/module.h>
  15#include <linux/dmaengine.h>
  16#include <linux/dma-mapping.h>
  17#include <linux/clk.h>
  18#include <linux/mmc/host.h>
  19#include <linux/platform_device.h>
  20#include <linux/cpufreq.h>
  21#include <linux/debugfs.h>
  22#include <linux/seq_file.h>
  23#include <linux/gpio.h>
  24#include <linux/interrupt.h>
  25#include <linux/irq.h>
  26#include <linux/io.h>
  27#include <linux/of.h>
  28#include <linux/of_device.h>
  29#include <linux/of_gpio.h>
  30#include <linux/mmc/slot-gpio.h>
  31
  32#include <plat/gpio-cfg.h>
  33#include <mach/dma.h>
  34#include <mach/gpio-samsung.h>
  35
  36#include <linux/platform_data/mmc-s3cmci.h>
  37
  38#include "s3cmci.h"
  39
  40#define DRIVER_NAME "s3c-mci"
  41
  42#define S3C2410_SDICON                  (0x00)
  43#define S3C2410_SDIPRE                  (0x04)
  44#define S3C2410_SDICMDARG               (0x08)
  45#define S3C2410_SDICMDCON               (0x0C)
  46#define S3C2410_SDICMDSTAT              (0x10)
  47#define S3C2410_SDIRSP0                 (0x14)
  48#define S3C2410_SDIRSP1                 (0x18)
  49#define S3C2410_SDIRSP2                 (0x1C)
  50#define S3C2410_SDIRSP3                 (0x20)
  51#define S3C2410_SDITIMER                (0x24)
  52#define S3C2410_SDIBSIZE                (0x28)
  53#define S3C2410_SDIDCON                 (0x2C)
  54#define S3C2410_SDIDCNT                 (0x30)
  55#define S3C2410_SDIDSTA                 (0x34)
  56#define S3C2410_SDIFSTA                 (0x38)
  57
  58#define S3C2410_SDIDATA                 (0x3C)
  59#define S3C2410_SDIIMSK                 (0x40)
  60
  61#define S3C2440_SDIDATA                 (0x40)
  62#define S3C2440_SDIIMSK                 (0x3C)
  63
  64#define S3C2440_SDICON_SDRESET          (1 << 8)
  65#define S3C2410_SDICON_SDIOIRQ          (1 << 3)
  66#define S3C2410_SDICON_FIFORESET        (1 << 1)
  67#define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
  68
  69#define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
  70#define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
  71#define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
  72#define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
  73#define S3C2410_SDICMDCON_INDEX         (0x3f)
  74
  75#define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
  76#define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
  77#define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
  78#define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
  79
  80#define S3C2440_SDIDCON_DS_WORD         (2 << 22)
  81#define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
  82#define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
  83#define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
  84#define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
  85#define S3C2410_SDIDCON_DMAEN           (1 << 15)
  86#define S3C2410_SDIDCON_STOP            (1 << 14)
  87#define S3C2440_SDIDCON_DATSTART        (1 << 14)
  88
  89#define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
  90#define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
  91
  92#define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
  93
  94#define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
  95#define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
  96#define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
  97#define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
  98#define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
  99#define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
 100#define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
 101#define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
 102
 103#define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
 104#define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
 105#define S3C2410_SDIFSTA_TFDET           (1 << 13)
 106#define S3C2410_SDIFSTA_RFDET           (1 << 12)
 107#define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
 108
 109#define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
 110#define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
 111#define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
 112#define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
 113#define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
 114#define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
 115#define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
 116#define S3C2410_SDIIMSK_DATACRC         (1 << 9)
 117#define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
 118#define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
 119#define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
 120#define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
 121#define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
 122
 123enum dbg_channels {
 124        dbg_err   = (1 << 0),
 125        dbg_debug = (1 << 1),
 126        dbg_info  = (1 << 2),
 127        dbg_irq   = (1 << 3),
 128        dbg_sg    = (1 << 4),
 129        dbg_dma   = (1 << 5),
 130        dbg_pio   = (1 << 6),
 131        dbg_fail  = (1 << 7),
 132        dbg_conf  = (1 << 8),
 133};
 134
 135static const int dbgmap_err   = dbg_fail;
 136static const int dbgmap_info  = dbg_info | dbg_conf;
 137static const int dbgmap_debug = dbg_err | dbg_debug;
 138
 139#define dbg(host, channels, args...)              \
 140        do {                                      \
 141        if (dbgmap_err & channels)                \
 142                dev_err(&host->pdev->dev, args);  \
 143        else if (dbgmap_info & channels)          \
 144                dev_info(&host->pdev->dev, args); \
 145        else if (dbgmap_debug & channels)         \
 146                dev_dbg(&host->pdev->dev, args);  \
 147        } while (0)
 148
 149static void finalize_request(struct s3cmci_host *host);
 150static void s3cmci_send_request(struct mmc_host *mmc);
 151static void s3cmci_reset(struct s3cmci_host *host);
 152
 153#ifdef CONFIG_MMC_DEBUG
 154
 155static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
 156{
 157        u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
 158        u32 datcon, datcnt, datsta, fsta, imask;
 159
 160        con     = readl(host->base + S3C2410_SDICON);
 161        pre     = readl(host->base + S3C2410_SDIPRE);
 162        cmdarg  = readl(host->base + S3C2410_SDICMDARG);
 163        cmdcon  = readl(host->base + S3C2410_SDICMDCON);
 164        cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
 165        r0      = readl(host->base + S3C2410_SDIRSP0);
 166        r1      = readl(host->base + S3C2410_SDIRSP1);
 167        r2      = readl(host->base + S3C2410_SDIRSP2);
 168        r3      = readl(host->base + S3C2410_SDIRSP3);
 169        timer   = readl(host->base + S3C2410_SDITIMER);
 170        bsize   = readl(host->base + S3C2410_SDIBSIZE);
 171        datcon  = readl(host->base + S3C2410_SDIDCON);
 172        datcnt  = readl(host->base + S3C2410_SDIDCNT);
 173        datsta  = readl(host->base + S3C2410_SDIDSTA);
 174        fsta    = readl(host->base + S3C2410_SDIFSTA);
 175        imask   = readl(host->base + host->sdiimsk);
 176
 177        dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
 178                                prefix, con, pre, timer);
 179
 180        dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
 181                                prefix, cmdcon, cmdarg, cmdsta);
 182
 183        dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 184                               " DSTA:[%08x] DCNT:[%08x]\n",
 185                                prefix, datcon, fsta, datsta, datcnt);
 186
 187        dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 188                               "   R2:[%08x]   R3:[%08x]\n",
 189                                prefix, r0, r1, r2, r3);
 190}
 191
 192static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 193                           int stop)
 194{
 195        snprintf(host->dbgmsg_cmd, 300,
 196                 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 197                 host->ccnt, (stop ? " (STOP)" : ""),
 198                 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 199
 200        if (cmd->data) {
 201                snprintf(host->dbgmsg_dat, 300,
 202                         "#%u bsize:%u blocks:%u bytes:%u",
 203                         host->dcnt, cmd->data->blksz,
 204                         cmd->data->blocks,
 205                         cmd->data->blocks * cmd->data->blksz);
 206        } else {
 207                host->dbgmsg_dat[0] = '\0';
 208        }
 209}
 210
 211static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 212                        int fail)
 213{
 214        unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 215
 216        if (!cmd)
 217                return;
 218
 219        if (cmd->error == 0) {
 220                dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 221                        host->dbgmsg_cmd, cmd->resp[0]);
 222        } else {
 223                dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 224                        cmd->error, host->dbgmsg_cmd, host->status);
 225        }
 226
 227        if (!cmd->data)
 228                return;
 229
 230        if (cmd->data->error == 0) {
 231                dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 232        } else {
 233                dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 234                        cmd->data->error, host->dbgmsg_dat,
 235                        readl(host->base + S3C2410_SDIDCNT));
 236        }
 237}
 238#else
 239static void dbg_dumpcmd(struct s3cmci_host *host,
 240                        struct mmc_command *cmd, int fail) { }
 241
 242static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 243                           int stop) { }
 244
 245static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 246
 247#endif /* CONFIG_MMC_DEBUG */
 248
 249/**
 250 * s3cmci_host_usedma - return whether the host is using dma or pio
 251 * @host: The host state
 252 *
 253 * Return true if the host is using DMA to transfer data, else false
 254 * to use PIO mode. Will return static data depending on the driver
 255 * configuration.
 256 */
 257static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 258{
 259#ifdef CONFIG_MMC_S3C_PIO
 260        return false;
 261#else /* CONFIG_MMC_S3C_DMA */
 262        return true;
 263#endif
 264}
 265
 266static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 267{
 268        u32 newmask;
 269
 270        newmask = readl(host->base + host->sdiimsk);
 271        newmask |= imask;
 272
 273        writel(newmask, host->base + host->sdiimsk);
 274
 275        return newmask;
 276}
 277
 278static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 279{
 280        u32 newmask;
 281
 282        newmask = readl(host->base + host->sdiimsk);
 283        newmask &= ~imask;
 284
 285        writel(newmask, host->base + host->sdiimsk);
 286
 287        return newmask;
 288}
 289
 290static inline void clear_imask(struct s3cmci_host *host)
 291{
 292        u32 mask = readl(host->base + host->sdiimsk);
 293
 294        /* preserve the SDIO IRQ mask state */
 295        mask &= S3C2410_SDIIMSK_SDIOIRQ;
 296        writel(mask, host->base + host->sdiimsk);
 297}
 298
 299/**
 300 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 301 * @host: The host to check.
 302 *
 303 * Test to see if the SDIO interrupt is being signalled in case the
 304 * controller has failed to re-detect a card interrupt. Read GPE8 and
 305 * see if it is low and if so, signal a SDIO interrupt.
 306 *
 307 * This is currently called if a request is finished (we assume that the
 308 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 309 * already being indicated.
 310*/
 311static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 312{
 313        if (host->sdio_irqen) {
 314                if (gpio_get_value(S3C2410_GPE(8)) == 0) {
 315                        pr_debug("%s: signalling irq\n", __func__);
 316                        mmc_signal_sdio_irq(host->mmc);
 317                }
 318        }
 319}
 320
 321static inline int get_data_buffer(struct s3cmci_host *host,
 322                                  u32 *bytes, u32 **pointer)
 323{
 324        struct scatterlist *sg;
 325
 326        if (host->pio_active == XFER_NONE)
 327                return -EINVAL;
 328
 329        if ((!host->mrq) || (!host->mrq->data))
 330                return -EINVAL;
 331
 332        if (host->pio_sgptr >= host->mrq->data->sg_len) {
 333                dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 334                      host->pio_sgptr, host->mrq->data->sg_len);
 335                return -EBUSY;
 336        }
 337        sg = &host->mrq->data->sg[host->pio_sgptr];
 338
 339        *bytes = sg->length;
 340        *pointer = sg_virt(sg);
 341
 342        host->pio_sgptr++;
 343
 344        dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 345            host->pio_sgptr, host->mrq->data->sg_len);
 346
 347        return 0;
 348}
 349
 350static inline u32 fifo_count(struct s3cmci_host *host)
 351{
 352        u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 353
 354        fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 355        return fifostat;
 356}
 357
 358static inline u32 fifo_free(struct s3cmci_host *host)
 359{
 360        u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 361
 362        fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 363        return 63 - fifostat;
 364}
 365
 366/**
 367 * s3cmci_enable_irq - enable IRQ, after having disabled it.
 368 * @host: The device state.
 369 * @more: True if more IRQs are expected from transfer.
 370 *
 371 * Enable the main IRQ if needed after it has been disabled.
 372 *
 373 * The IRQ can be one of the following states:
 374 *      - disabled during IDLE
 375 *      - disabled whilst processing data
 376 *      - enabled during transfer
 377 *      - enabled whilst awaiting SDIO interrupt detection
 378 */
 379static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 380{
 381        unsigned long flags;
 382        bool enable = false;
 383
 384        local_irq_save(flags);
 385
 386        host->irq_enabled = more;
 387        host->irq_disabled = false;
 388
 389        enable = more | host->sdio_irqen;
 390
 391        if (host->irq_state != enable) {
 392                host->irq_state = enable;
 393
 394                if (enable)
 395                        enable_irq(host->irq);
 396                else
 397                        disable_irq(host->irq);
 398        }
 399
 400        local_irq_restore(flags);
 401}
 402
 403/**
 404 *
 405 */
 406static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 407{
 408        unsigned long flags;
 409
 410        local_irq_save(flags);
 411
 412        /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 413
 414        host->irq_disabled = transfer;
 415
 416        if (transfer && host->irq_state) {
 417                host->irq_state = false;
 418                disable_irq(host->irq);
 419        }
 420
 421        local_irq_restore(flags);
 422}
 423
 424static void do_pio_read(struct s3cmci_host *host)
 425{
 426        int res;
 427        u32 fifo;
 428        u32 *ptr;
 429        u32 fifo_words;
 430        void __iomem *from_ptr;
 431
 432        /* write real prescaler to host, it might be set slow to fix */
 433        writel(host->prescaler, host->base + S3C2410_SDIPRE);
 434
 435        from_ptr = host->base + host->sdidata;
 436
 437        while ((fifo = fifo_count(host))) {
 438                if (!host->pio_bytes) {
 439                        res = get_data_buffer(host, &host->pio_bytes,
 440                                              &host->pio_ptr);
 441                        if (res) {
 442                                host->pio_active = XFER_NONE;
 443                                host->complete_what = COMPLETION_FINALIZE;
 444
 445                                dbg(host, dbg_pio, "pio_read(): "
 446                                    "complete (no more data).\n");
 447                                return;
 448                        }
 449
 450                        dbg(host, dbg_pio,
 451                            "pio_read(): new target: [%i]@[%p]\n",
 452                            host->pio_bytes, host->pio_ptr);
 453                }
 454
 455                dbg(host, dbg_pio,
 456                    "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 457                    fifo, host->pio_bytes,
 458                    readl(host->base + S3C2410_SDIDCNT));
 459
 460                /* If we have reached the end of the block, we can
 461                 * read a word and get 1 to 3 bytes.  If we in the
 462                 * middle of the block, we have to read full words,
 463                 * otherwise we will write garbage, so round down to
 464                 * an even multiple of 4. */
 465                if (fifo >= host->pio_bytes)
 466                        fifo = host->pio_bytes;
 467                else
 468                        fifo -= fifo & 3;
 469
 470                host->pio_bytes -= fifo;
 471                host->pio_count += fifo;
 472
 473                fifo_words = fifo >> 2;
 474                ptr = host->pio_ptr;
 475                while (fifo_words--)
 476                        *ptr++ = readl(from_ptr);
 477                host->pio_ptr = ptr;
 478
 479                if (fifo & 3) {
 480                        u32 n = fifo & 3;
 481                        u32 data = readl(from_ptr);
 482                        u8 *p = (u8 *)host->pio_ptr;
 483
 484                        while (n--) {
 485                                *p++ = data;
 486                                data >>= 8;
 487                        }
 488                }
 489        }
 490
 491        if (!host->pio_bytes) {
 492                res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 493                if (res) {
 494                        dbg(host, dbg_pio,
 495                            "pio_read(): complete (no more buffers).\n");
 496                        host->pio_active = XFER_NONE;
 497                        host->complete_what = COMPLETION_FINALIZE;
 498
 499                        return;
 500                }
 501        }
 502
 503        enable_imask(host,
 504                     S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 505}
 506
 507static void do_pio_write(struct s3cmci_host *host)
 508{
 509        void __iomem *to_ptr;
 510        int res;
 511        u32 fifo;
 512        u32 *ptr;
 513
 514        to_ptr = host->base + host->sdidata;
 515
 516        while ((fifo = fifo_free(host)) > 3) {
 517                if (!host->pio_bytes) {
 518                        res = get_data_buffer(host, &host->pio_bytes,
 519                                                        &host->pio_ptr);
 520                        if (res) {
 521                                dbg(host, dbg_pio,
 522                                    "pio_write(): complete (no more data).\n");
 523                                host->pio_active = XFER_NONE;
 524
 525                                return;
 526                        }
 527
 528                        dbg(host, dbg_pio,
 529                            "pio_write(): new source: [%i]@[%p]\n",
 530                            host->pio_bytes, host->pio_ptr);
 531
 532                }
 533
 534                /* If we have reached the end of the block, we have to
 535                 * write exactly the remaining number of bytes.  If we
 536                 * in the middle of the block, we have to write full
 537                 * words, so round down to an even multiple of 4. */
 538                if (fifo >= host->pio_bytes)
 539                        fifo = host->pio_bytes;
 540                else
 541                        fifo -= fifo & 3;
 542
 543                host->pio_bytes -= fifo;
 544                host->pio_count += fifo;
 545
 546                fifo = (fifo + 3) >> 2;
 547                ptr = host->pio_ptr;
 548                while (fifo--)
 549                        writel(*ptr++, to_ptr);
 550                host->pio_ptr = ptr;
 551        }
 552
 553        enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 554}
 555
 556static void pio_tasklet(unsigned long data)
 557{
 558        struct s3cmci_host *host = (struct s3cmci_host *) data;
 559
 560        s3cmci_disable_irq(host, true);
 561
 562        if (host->pio_active == XFER_WRITE)
 563                do_pio_write(host);
 564
 565        if (host->pio_active == XFER_READ)
 566                do_pio_read(host);
 567
 568        if (host->complete_what == COMPLETION_FINALIZE) {
 569                clear_imask(host);
 570                if (host->pio_active != XFER_NONE) {
 571                        dbg(host, dbg_err, "unfinished %s "
 572                            "- pio_count:[%u] pio_bytes:[%u]\n",
 573                            (host->pio_active == XFER_READ) ? "read" : "write",
 574                            host->pio_count, host->pio_bytes);
 575
 576                        if (host->mrq->data)
 577                                host->mrq->data->error = -EINVAL;
 578                }
 579
 580                s3cmci_enable_irq(host, false);
 581                finalize_request(host);
 582        } else
 583                s3cmci_enable_irq(host, true);
 584}
 585
 586/*
 587 * ISR for SDI Interface IRQ
 588 * Communication between driver and ISR works as follows:
 589 *   host->mrq                  points to current request
 590 *   host->complete_what        Indicates when the request is considered done
 591 *     COMPLETION_CMDSENT         when the command was sent
 592 *     COMPLETION_RSPFIN          when a response was received
 593 *     COMPLETION_XFERFINISH      when the data transfer is finished
 594 *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 595 *   host->complete_request     is the completion-object the driver waits for
 596 *
 597 * 1) Driver sets up host->mrq and host->complete_what
 598 * 2) Driver prepares the transfer
 599 * 3) Driver enables interrupts
 600 * 4) Driver starts transfer
 601 * 5) Driver waits for host->complete_rquest
 602 * 6) ISR checks for request status (errors and success)
 603 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 604 * 7) ISR completes host->complete_request
 605 * 8) ISR disables interrupts
 606 * 9) Driver wakes up and takes care of the request
 607 *
 608 * Note: "->error"-fields are expected to be set to 0 before the request
 609 *       was issued by mmc.c - therefore they are only set, when an error
 610 *       contition comes up
 611 */
 612
 613static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 614{
 615        struct s3cmci_host *host = dev_id;
 616        struct mmc_command *cmd;
 617        u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 618        u32 mci_cclear = 0, mci_dclear;
 619        unsigned long iflags;
 620
 621        mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 622        mci_imsk = readl(host->base + host->sdiimsk);
 623
 624        if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 625                if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 626                        mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 627                        writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 628
 629                        mmc_signal_sdio_irq(host->mmc);
 630                        return IRQ_HANDLED;
 631                }
 632        }
 633
 634        spin_lock_irqsave(&host->complete_lock, iflags);
 635
 636        mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 637        mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 638        mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 639        mci_dclear = 0;
 640
 641        if ((host->complete_what == COMPLETION_NONE) ||
 642            (host->complete_what == COMPLETION_FINALIZE)) {
 643                host->status = "nothing to complete";
 644                clear_imask(host);
 645                goto irq_out;
 646        }
 647
 648        if (!host->mrq) {
 649                host->status = "no active mrq";
 650                clear_imask(host);
 651                goto irq_out;
 652        }
 653
 654        cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 655
 656        if (!cmd) {
 657                host->status = "no active cmd";
 658                clear_imask(host);
 659                goto irq_out;
 660        }
 661
 662        if (!s3cmci_host_usedma(host)) {
 663                if ((host->pio_active == XFER_WRITE) &&
 664                    (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 665
 666                        disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 667                        tasklet_schedule(&host->pio_tasklet);
 668                        host->status = "pio tx";
 669                }
 670
 671                if ((host->pio_active == XFER_READ) &&
 672                    (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 673
 674                        disable_imask(host,
 675                                      S3C2410_SDIIMSK_RXFIFOHALF |
 676                                      S3C2410_SDIIMSK_RXFIFOLAST);
 677
 678                        tasklet_schedule(&host->pio_tasklet);
 679                        host->status = "pio rx";
 680                }
 681        }
 682
 683        if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 684                dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 685                cmd->error = -ETIMEDOUT;
 686                host->status = "error: command timeout";
 687                goto fail_transfer;
 688        }
 689
 690        if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 691                if (host->complete_what == COMPLETION_CMDSENT) {
 692                        host->status = "ok: command sent";
 693                        goto close_transfer;
 694                }
 695
 696                mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 697        }
 698
 699        if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 700                if (cmd->flags & MMC_RSP_CRC) {
 701                        if (host->mrq->cmd->flags & MMC_RSP_136) {
 702                                dbg(host, dbg_irq,
 703                                    "fixup: ignore CRC fail with long rsp\n");
 704                        } else {
 705                                /* note, we used to fail the transfer
 706                                 * here, but it seems that this is just
 707                                 * the hardware getting it wrong.
 708                                 *
 709                                 * cmd->error = -EILSEQ;
 710                                 * host->status = "error: bad command crc";
 711                                 * goto fail_transfer;
 712                                */
 713                        }
 714                }
 715
 716                mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 717        }
 718
 719        if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 720                if (host->complete_what == COMPLETION_RSPFIN) {
 721                        host->status = "ok: command response received";
 722                        goto close_transfer;
 723                }
 724
 725                if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 726                        host->complete_what = COMPLETION_XFERFINISH;
 727
 728                mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 729        }
 730
 731        /* errors handled after this point are only relevant
 732           when a data transfer is in progress */
 733
 734        if (!cmd->data)
 735                goto clear_status_bits;
 736
 737        /* Check for FIFO failure */
 738        if (host->is2440) {
 739                if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 740                        dbg(host, dbg_err, "FIFO failure\n");
 741                        host->mrq->data->error = -EILSEQ;
 742                        host->status = "error: 2440 fifo failure";
 743                        goto fail_transfer;
 744                }
 745        } else {
 746                if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 747                        dbg(host, dbg_err, "FIFO failure\n");
 748                        cmd->data->error = -EILSEQ;
 749                        host->status = "error:  fifo failure";
 750                        goto fail_transfer;
 751                }
 752        }
 753
 754        if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 755                dbg(host, dbg_err, "bad data crc (outgoing)\n");
 756                cmd->data->error = -EILSEQ;
 757                host->status = "error: bad data crc (outgoing)";
 758                goto fail_transfer;
 759        }
 760
 761        if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 762                dbg(host, dbg_err, "bad data crc (incoming)\n");
 763                cmd->data->error = -EILSEQ;
 764                host->status = "error: bad data crc (incoming)";
 765                goto fail_transfer;
 766        }
 767
 768        if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 769                dbg(host, dbg_err, "data timeout\n");
 770                cmd->data->error = -ETIMEDOUT;
 771                host->status = "error: data timeout";
 772                goto fail_transfer;
 773        }
 774
 775        if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 776                if (host->complete_what == COMPLETION_XFERFINISH) {
 777                        host->status = "ok: data transfer completed";
 778                        goto close_transfer;
 779                }
 780
 781                if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 782                        host->complete_what = COMPLETION_RSPFIN;
 783
 784                mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 785        }
 786
 787clear_status_bits:
 788        writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 789        writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 790
 791        goto irq_out;
 792
 793fail_transfer:
 794        host->pio_active = XFER_NONE;
 795
 796close_transfer:
 797        host->complete_what = COMPLETION_FINALIZE;
 798
 799        clear_imask(host);
 800        tasklet_schedule(&host->pio_tasklet);
 801
 802        goto irq_out;
 803
 804irq_out:
 805        dbg(host, dbg_irq,
 806            "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 807            mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 808
 809        spin_unlock_irqrestore(&host->complete_lock, iflags);
 810        return IRQ_HANDLED;
 811
 812}
 813
 814static void s3cmci_dma_done_callback(void *arg)
 815{
 816        struct s3cmci_host *host = arg;
 817        unsigned long iflags;
 818
 819        BUG_ON(!host->mrq);
 820        BUG_ON(!host->mrq->data);
 821
 822        spin_lock_irqsave(&host->complete_lock, iflags);
 823
 824        dbg(host, dbg_dma, "DMA FINISHED\n");
 825
 826        host->dma_complete = 1;
 827        host->complete_what = COMPLETION_FINALIZE;
 828
 829        tasklet_schedule(&host->pio_tasklet);
 830        spin_unlock_irqrestore(&host->complete_lock, iflags);
 831
 832}
 833
 834static void finalize_request(struct s3cmci_host *host)
 835{
 836        struct mmc_request *mrq = host->mrq;
 837        struct mmc_command *cmd;
 838        int debug_as_failure = 0;
 839
 840        if (host->complete_what != COMPLETION_FINALIZE)
 841                return;
 842
 843        if (!mrq)
 844                return;
 845        cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 846
 847        if (cmd->data && (cmd->error == 0) &&
 848            (cmd->data->error == 0)) {
 849                if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 850                        dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 851                            host->dma_complete);
 852                        return;
 853                }
 854        }
 855
 856        /* Read response from controller. */
 857        cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 858        cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 859        cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 860        cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 861
 862        writel(host->prescaler, host->base + S3C2410_SDIPRE);
 863
 864        if (cmd->error)
 865                debug_as_failure = 1;
 866
 867        if (cmd->data && cmd->data->error)
 868                debug_as_failure = 1;
 869
 870        dbg_dumpcmd(host, cmd, debug_as_failure);
 871
 872        /* Cleanup controller */
 873        writel(0, host->base + S3C2410_SDICMDARG);
 874        writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 875        writel(0, host->base + S3C2410_SDICMDCON);
 876        clear_imask(host);
 877
 878        if (cmd->data && cmd->error)
 879                cmd->data->error = cmd->error;
 880
 881        if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 882                host->cmd_is_stop = 1;
 883                s3cmci_send_request(host->mmc);
 884                return;
 885        }
 886
 887        /* If we have no data transfer we are finished here */
 888        if (!mrq->data)
 889                goto request_done;
 890
 891        /* Calculate the amout of bytes transfer if there was no error */
 892        if (mrq->data->error == 0) {
 893                mrq->data->bytes_xfered =
 894                        (mrq->data->blocks * mrq->data->blksz);
 895        } else {
 896                mrq->data->bytes_xfered = 0;
 897        }
 898
 899        /* If we had an error while transferring data we flush the
 900         * DMA channel and the fifo to clear out any garbage. */
 901        if (mrq->data->error != 0) {
 902                if (s3cmci_host_usedma(host))
 903                        dmaengine_terminate_all(host->dma);
 904
 905                if (host->is2440) {
 906                        /* Clear failure register and reset fifo. */
 907                        writel(S3C2440_SDIFSTA_FIFORESET |
 908                               S3C2440_SDIFSTA_FIFOFAIL,
 909                               host->base + S3C2410_SDIFSTA);
 910                } else {
 911                        u32 mci_con;
 912
 913                        /* reset fifo */
 914                        mci_con = readl(host->base + S3C2410_SDICON);
 915                        mci_con |= S3C2410_SDICON_FIFORESET;
 916
 917                        writel(mci_con, host->base + S3C2410_SDICON);
 918                }
 919        }
 920
 921request_done:
 922        host->complete_what = COMPLETION_NONE;
 923        host->mrq = NULL;
 924
 925        s3cmci_check_sdio_irq(host);
 926        mmc_request_done(host->mmc, mrq);
 927}
 928
 929static void s3cmci_send_command(struct s3cmci_host *host,
 930                                        struct mmc_command *cmd)
 931{
 932        u32 ccon, imsk;
 933
 934        imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 935                S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 936                S3C2410_SDIIMSK_RESPONSECRC;
 937
 938        enable_imask(host, imsk);
 939
 940        if (cmd->data)
 941                host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 942        else if (cmd->flags & MMC_RSP_PRESENT)
 943                host->complete_what = COMPLETION_RSPFIN;
 944        else
 945                host->complete_what = COMPLETION_CMDSENT;
 946
 947        writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 948
 949        ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 950        ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 951
 952        if (cmd->flags & MMC_RSP_PRESENT)
 953                ccon |= S3C2410_SDICMDCON_WAITRSP;
 954
 955        if (cmd->flags & MMC_RSP_136)
 956                ccon |= S3C2410_SDICMDCON_LONGRSP;
 957
 958        writel(ccon, host->base + S3C2410_SDICMDCON);
 959}
 960
 961static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 962{
 963        u32 dcon, imsk, stoptries = 3;
 964
 965        /* write DCON register */
 966
 967        if (!data) {
 968                writel(0, host->base + S3C2410_SDIDCON);
 969                return 0;
 970        }
 971
 972        if ((data->blksz & 3) != 0) {
 973                /* We cannot deal with unaligned blocks with more than
 974                 * one block being transferred. */
 975
 976                if (data->blocks > 1) {
 977                        pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
 978                                __func__, data->blksz);
 979                        return -EINVAL;
 980                }
 981        }
 982
 983        while (readl(host->base + S3C2410_SDIDSTA) &
 984               (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 985
 986                dbg(host, dbg_err,
 987                    "mci_setup_data() transfer stillin progress.\n");
 988
 989                writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 990                s3cmci_reset(host);
 991
 992                if ((stoptries--) == 0) {
 993                        dbg_dumpregs(host, "DRF");
 994                        return -EINVAL;
 995                }
 996        }
 997
 998        dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 999
1000        if (s3cmci_host_usedma(host))
1001                dcon |= S3C2410_SDIDCON_DMAEN;
1002
1003        if (host->bus_width == MMC_BUS_WIDTH_4)
1004                dcon |= S3C2410_SDIDCON_WIDEBUS;
1005
1006        dcon |= S3C2410_SDIDCON_BLOCKMODE;
1007
1008        if (data->flags & MMC_DATA_WRITE) {
1009                dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1010                dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1011        }
1012
1013        if (data->flags & MMC_DATA_READ) {
1014                dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1015                dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1016        }
1017
1018        if (host->is2440) {
1019                dcon |= S3C2440_SDIDCON_DS_WORD;
1020                dcon |= S3C2440_SDIDCON_DATSTART;
1021        }
1022
1023        writel(dcon, host->base + S3C2410_SDIDCON);
1024
1025        /* write BSIZE register */
1026
1027        writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1028
1029        /* add to IMASK register */
1030        imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1031               S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1032
1033        enable_imask(host, imsk);
1034
1035        /* write TIMER register */
1036
1037        if (host->is2440) {
1038                writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1039        } else {
1040                writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1041
1042                /* FIX: set slow clock to prevent timeouts on read */
1043                if (data->flags & MMC_DATA_READ)
1044                        writel(0xFF, host->base + S3C2410_SDIPRE);
1045        }
1046
1047        return 0;
1048}
1049
1050#define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1051
1052static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1053{
1054        int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1055
1056        BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1057
1058        host->pio_sgptr = 0;
1059        host->pio_bytes = 0;
1060        host->pio_count = 0;
1061        host->pio_active = rw ? XFER_WRITE : XFER_READ;
1062
1063        if (rw) {
1064                do_pio_write(host);
1065                enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1066        } else {
1067                enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1068                             | S3C2410_SDIIMSK_RXFIFOLAST);
1069        }
1070
1071        return 0;
1072}
1073
1074static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1075{
1076        int rw = data->flags & MMC_DATA_WRITE;
1077        struct dma_async_tx_descriptor *desc;
1078        struct dma_slave_config conf = {
1079                .src_addr = host->mem->start + host->sdidata,
1080                .dst_addr = host->mem->start + host->sdidata,
1081                .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1082                .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1083        };
1084
1085        BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1086
1087        /* Restore prescaler value */
1088        writel(host->prescaler, host->base + S3C2410_SDIPRE);
1089
1090        if (!rw)
1091                conf.direction = DMA_DEV_TO_MEM;
1092        else
1093                conf.direction = DMA_MEM_TO_DEV;
1094
1095        dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1096                   mmc_get_dma_dir(data));
1097
1098        dmaengine_slave_config(host->dma, &conf);
1099        desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1100                conf.direction,
1101                DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1102        if (!desc)
1103                goto unmap_exit;
1104        desc->callback = s3cmci_dma_done_callback;
1105        desc->callback_param = host;
1106        dmaengine_submit(desc);
1107        dma_async_issue_pending(host->dma);
1108
1109        return 0;
1110
1111unmap_exit:
1112        dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1113                     mmc_get_dma_dir(data));
1114        return -ENOMEM;
1115}
1116
1117static void s3cmci_send_request(struct mmc_host *mmc)
1118{
1119        struct s3cmci_host *host = mmc_priv(mmc);
1120        struct mmc_request *mrq = host->mrq;
1121        struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1122
1123        host->ccnt++;
1124        prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1125
1126        /* Clear command, data and fifo status registers
1127           Fifo clear only necessary on 2440, but doesn't hurt on 2410
1128        */
1129        writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1130        writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1131        writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1132
1133        if (cmd->data) {
1134                int res = s3cmci_setup_data(host, cmd->data);
1135
1136                host->dcnt++;
1137
1138                if (res) {
1139                        dbg(host, dbg_err, "setup data error %d\n", res);
1140                        cmd->error = res;
1141                        cmd->data->error = res;
1142
1143                        mmc_request_done(mmc, mrq);
1144                        return;
1145                }
1146
1147                if (s3cmci_host_usedma(host))
1148                        res = s3cmci_prepare_dma(host, cmd->data);
1149                else
1150                        res = s3cmci_prepare_pio(host, cmd->data);
1151
1152                if (res) {
1153                        dbg(host, dbg_err, "data prepare error %d\n", res);
1154                        cmd->error = res;
1155                        cmd->data->error = res;
1156
1157                        mmc_request_done(mmc, mrq);
1158                        return;
1159                }
1160        }
1161
1162        /* Send command */
1163        s3cmci_send_command(host, cmd);
1164
1165        /* Enable Interrupt */
1166        s3cmci_enable_irq(host, true);
1167}
1168
1169static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1170{
1171        struct s3cmci_host *host = mmc_priv(mmc);
1172
1173        host->status = "mmc request";
1174        host->cmd_is_stop = 0;
1175        host->mrq = mrq;
1176
1177        if (mmc_gpio_get_cd(mmc) == 0) {
1178                dbg(host, dbg_err, "%s: no medium present\n", __func__);
1179                host->mrq->cmd->error = -ENOMEDIUM;
1180                mmc_request_done(mmc, mrq);
1181        } else
1182                s3cmci_send_request(mmc);
1183}
1184
1185static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1186{
1187        u32 mci_psc;
1188
1189        /* Set clock */
1190        for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1191                host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1192
1193                if (host->real_rate <= ios->clock)
1194                        break;
1195        }
1196
1197        if (mci_psc > 255)
1198                mci_psc = 255;
1199
1200        host->prescaler = mci_psc;
1201        writel(host->prescaler, host->base + S3C2410_SDIPRE);
1202
1203        /* If requested clock is 0, real_rate will be 0, too */
1204        if (ios->clock == 0)
1205                host->real_rate = 0;
1206}
1207
1208static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1209{
1210        struct s3cmci_host *host = mmc_priv(mmc);
1211        u32 mci_con;
1212
1213        /* Set the power state */
1214
1215        mci_con = readl(host->base + S3C2410_SDICON);
1216
1217        switch (ios->power_mode) {
1218        case MMC_POWER_ON:
1219        case MMC_POWER_UP:
1220                /* Configure GPE5...GPE10 pins in SD mode */
1221                if (!host->pdev->dev.of_node)
1222                        s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1223                                              S3C_GPIO_PULL_NONE);
1224
1225                if (host->pdata->set_power)
1226                        host->pdata->set_power(ios->power_mode, ios->vdd);
1227
1228                if (!host->is2440)
1229                        mci_con |= S3C2410_SDICON_FIFORESET;
1230
1231                break;
1232
1233        case MMC_POWER_OFF:
1234        default:
1235                if (!host->pdev->dev.of_node)
1236                        gpio_direction_output(S3C2410_GPE(5), 0);
1237
1238                if (host->is2440)
1239                        mci_con |= S3C2440_SDICON_SDRESET;
1240
1241                if (host->pdata->set_power)
1242                        host->pdata->set_power(ios->power_mode, ios->vdd);
1243
1244                break;
1245        }
1246
1247        s3cmci_set_clk(host, ios);
1248
1249        /* Set CLOCK_ENABLE */
1250        if (ios->clock)
1251                mci_con |= S3C2410_SDICON_CLOCKTYPE;
1252        else
1253                mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1254
1255        writel(mci_con, host->base + S3C2410_SDICON);
1256
1257        if ((ios->power_mode == MMC_POWER_ON) ||
1258            (ios->power_mode == MMC_POWER_UP)) {
1259                dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1260                        host->real_rate/1000, ios->clock/1000);
1261        } else {
1262                dbg(host, dbg_conf, "powered down.\n");
1263        }
1264
1265        host->bus_width = ios->bus_width;
1266}
1267
1268static void s3cmci_reset(struct s3cmci_host *host)
1269{
1270        u32 con = readl(host->base + S3C2410_SDICON);
1271
1272        con |= S3C2440_SDICON_SDRESET;
1273        writel(con, host->base + S3C2410_SDICON);
1274}
1275
1276static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1277{
1278        struct s3cmci_host *host = mmc_priv(mmc);
1279        unsigned long flags;
1280        u32 con;
1281
1282        local_irq_save(flags);
1283
1284        con = readl(host->base + S3C2410_SDICON);
1285        host->sdio_irqen = enable;
1286
1287        if (enable == host->sdio_irqen)
1288                goto same_state;
1289
1290        if (enable) {
1291                con |= S3C2410_SDICON_SDIOIRQ;
1292                enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1293
1294                if (!host->irq_state && !host->irq_disabled) {
1295                        host->irq_state = true;
1296                        enable_irq(host->irq);
1297                }
1298        } else {
1299                disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1300                con &= ~S3C2410_SDICON_SDIOIRQ;
1301
1302                if (!host->irq_enabled && host->irq_state) {
1303                        disable_irq_nosync(host->irq);
1304                        host->irq_state = false;
1305                }
1306        }
1307
1308        writel(con, host->base + S3C2410_SDICON);
1309
1310 same_state:
1311        local_irq_restore(flags);
1312
1313        s3cmci_check_sdio_irq(host);
1314}
1315
1316static struct mmc_host_ops s3cmci_ops = {
1317        .request        = s3cmci_request,
1318        .set_ios        = s3cmci_set_ios,
1319        .get_ro         = mmc_gpio_get_ro,
1320        .get_cd         = mmc_gpio_get_cd,
1321        .enable_sdio_irq = s3cmci_enable_sdio_irq,
1322};
1323
1324static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1325        /* This is currently here to avoid a number of if (host->pdata)
1326         * checks. Any zero fields to ensure reasonable defaults are picked. */
1327         .no_wprotect = 1,
1328         .no_detect = 1,
1329};
1330
1331#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1332
1333static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1334                                     unsigned long val, void *data)
1335{
1336        struct s3cmci_host *host;
1337        struct mmc_host *mmc;
1338        unsigned long newclk;
1339        unsigned long flags;
1340
1341        host = container_of(nb, struct s3cmci_host, freq_transition);
1342        newclk = clk_get_rate(host->clk);
1343        mmc = host->mmc;
1344
1345        if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1346            (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1347                spin_lock_irqsave(&mmc->lock, flags);
1348
1349                host->clk_rate = newclk;
1350
1351                if (mmc->ios.power_mode != MMC_POWER_OFF &&
1352                    mmc->ios.clock != 0)
1353                        s3cmci_set_clk(host, &mmc->ios);
1354
1355                spin_unlock_irqrestore(&mmc->lock, flags);
1356        }
1357
1358        return 0;
1359}
1360
1361static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1362{
1363        host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1364
1365        return cpufreq_register_notifier(&host->freq_transition,
1366                                         CPUFREQ_TRANSITION_NOTIFIER);
1367}
1368
1369static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1370{
1371        cpufreq_unregister_notifier(&host->freq_transition,
1372                                    CPUFREQ_TRANSITION_NOTIFIER);
1373}
1374
1375#else
1376static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1377{
1378        return 0;
1379}
1380
1381static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1382{
1383}
1384#endif
1385
1386
1387#ifdef CONFIG_DEBUG_FS
1388
1389static int s3cmci_state_show(struct seq_file *seq, void *v)
1390{
1391        struct s3cmci_host *host = seq->private;
1392
1393        seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1394        seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1395        seq_printf(seq, "Prescale = %d\n", host->prescaler);
1396        seq_printf(seq, "is2440 = %d\n", host->is2440);
1397        seq_printf(seq, "IRQ = %d\n", host->irq);
1398        seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1399        seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1400        seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1401        seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1402        seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1403        seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1404        seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1405
1406        return 0;
1407}
1408
1409static int s3cmci_state_open(struct inode *inode, struct file *file)
1410{
1411        return single_open(file, s3cmci_state_show, inode->i_private);
1412}
1413
1414static const struct file_operations s3cmci_fops_state = {
1415        .owner          = THIS_MODULE,
1416        .open           = s3cmci_state_open,
1417        .read           = seq_read,
1418        .llseek         = seq_lseek,
1419        .release        = single_release,
1420};
1421
1422#define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1423
1424struct s3cmci_reg {
1425        unsigned short  addr;
1426        unsigned char   *name;
1427} debug_regs[] = {
1428        DBG_REG(CON),
1429        DBG_REG(PRE),
1430        DBG_REG(CMDARG),
1431        DBG_REG(CMDCON),
1432        DBG_REG(CMDSTAT),
1433        DBG_REG(RSP0),
1434        DBG_REG(RSP1),
1435        DBG_REG(RSP2),
1436        DBG_REG(RSP3),
1437        DBG_REG(TIMER),
1438        DBG_REG(BSIZE),
1439        DBG_REG(DCON),
1440        DBG_REG(DCNT),
1441        DBG_REG(DSTA),
1442        DBG_REG(FSTA),
1443        {}
1444};
1445
1446static int s3cmci_regs_show(struct seq_file *seq, void *v)
1447{
1448        struct s3cmci_host *host = seq->private;
1449        struct s3cmci_reg *rptr = debug_regs;
1450
1451        for (; rptr->name; rptr++)
1452                seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1453                           readl(host->base + rptr->addr));
1454
1455        seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1456
1457        return 0;
1458}
1459
1460static int s3cmci_regs_open(struct inode *inode, struct file *file)
1461{
1462        return single_open(file, s3cmci_regs_show, inode->i_private);
1463}
1464
1465static const struct file_operations s3cmci_fops_regs = {
1466        .owner          = THIS_MODULE,
1467        .open           = s3cmci_regs_open,
1468        .read           = seq_read,
1469        .llseek         = seq_lseek,
1470        .release        = single_release,
1471};
1472
1473static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1474{
1475        struct device *dev = &host->pdev->dev;
1476
1477        host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1478        if (IS_ERR(host->debug_root)) {
1479                dev_err(dev, "failed to create debugfs root\n");
1480                return;
1481        }
1482
1483        host->debug_state = debugfs_create_file("state", 0444,
1484                                                host->debug_root, host,
1485                                                &s3cmci_fops_state);
1486
1487        if (IS_ERR(host->debug_state))
1488                dev_err(dev, "failed to create debug state file\n");
1489
1490        host->debug_regs = debugfs_create_file("regs", 0444,
1491                                               host->debug_root, host,
1492                                               &s3cmci_fops_regs);
1493
1494        if (IS_ERR(host->debug_regs))
1495                dev_err(dev, "failed to create debug regs file\n");
1496}
1497
1498static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1499{
1500        debugfs_remove(host->debug_regs);
1501        debugfs_remove(host->debug_state);
1502        debugfs_remove(host->debug_root);
1503}
1504
1505#else
1506static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1507static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1508
1509#endif /* CONFIG_DEBUG_FS */
1510
1511static int s3cmci_probe_pdata(struct s3cmci_host *host)
1512{
1513        struct platform_device *pdev = host->pdev;
1514        struct mmc_host *mmc = host->mmc;
1515        struct s3c24xx_mci_pdata *pdata;
1516        int i, ret;
1517
1518        host->is2440 = platform_get_device_id(pdev)->driver_data;
1519
1520        for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1521                ret = gpio_request(i, dev_name(&pdev->dev));
1522                if (ret) {
1523                        dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1524
1525                        for (i--; i >= S3C2410_GPE(5); i--)
1526                                gpio_free(i);
1527
1528                        return ret;
1529                }
1530        }
1531
1532        if (!pdev->dev.platform_data)
1533                pdev->dev.platform_data = &s3cmci_def_pdata;
1534
1535        pdata = pdev->dev.platform_data;
1536
1537        if (pdata->no_wprotect)
1538                mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1539
1540        if (pdata->no_detect)
1541                mmc->caps |= MMC_CAP_NEEDS_POLL;
1542
1543        if (pdata->wprotect_invert)
1544                mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1545
1546        if (pdata->detect_invert)
1547                 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1548
1549        if (gpio_is_valid(pdata->gpio_detect)) {
1550                ret = mmc_gpio_request_cd(mmc, pdata->gpio_detect, 0);
1551                if (ret) {
1552                        dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
1553                                ret);
1554                        return ret;
1555                }
1556        }
1557
1558        if (gpio_is_valid(pdata->gpio_wprotect)) {
1559                ret = mmc_gpio_request_ro(mmc, pdata->gpio_wprotect);
1560                if (ret) {
1561                        dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
1562                                ret);
1563                        return ret;
1564                }
1565        }
1566
1567        return 0;
1568}
1569
1570static int s3cmci_probe_dt(struct s3cmci_host *host)
1571{
1572        struct platform_device *pdev = host->pdev;
1573        struct s3c24xx_mci_pdata *pdata;
1574        struct mmc_host *mmc = host->mmc;
1575        int ret;
1576
1577        host->is2440 = (int) of_device_get_match_data(&pdev->dev);
1578
1579        ret = mmc_of_parse(mmc);
1580        if (ret)
1581                return ret;
1582
1583        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1584        if (!pdata)
1585                return -ENOMEM;
1586
1587        pdev->dev.platform_data = pdata;
1588
1589        return 0;
1590}
1591
1592static int s3cmci_probe(struct platform_device *pdev)
1593{
1594        struct s3cmci_host *host;
1595        struct mmc_host *mmc;
1596        int ret;
1597        int i;
1598
1599        mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1600        if (!mmc) {
1601                ret = -ENOMEM;
1602                goto probe_out;
1603        }
1604
1605        host = mmc_priv(mmc);
1606        host->mmc       = mmc;
1607        host->pdev      = pdev;
1608
1609        if (pdev->dev.of_node)
1610                ret = s3cmci_probe_dt(host);
1611        else
1612                ret = s3cmci_probe_pdata(host);
1613
1614        if (ret)
1615                goto probe_free_host;
1616
1617        host->pdata = pdev->dev.platform_data;
1618
1619        spin_lock_init(&host->complete_lock);
1620        tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1621
1622        if (host->is2440) {
1623                host->sdiimsk   = S3C2440_SDIIMSK;
1624                host->sdidata   = S3C2440_SDIDATA;
1625                host->clk_div   = 1;
1626        } else {
1627                host->sdiimsk   = S3C2410_SDIIMSK;
1628                host->sdidata   = S3C2410_SDIDATA;
1629                host->clk_div   = 2;
1630        }
1631
1632        host->complete_what     = COMPLETION_NONE;
1633        host->pio_active        = XFER_NONE;
1634
1635        host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1636        if (!host->mem) {
1637                dev_err(&pdev->dev,
1638                        "failed to get io memory region resource.\n");
1639
1640                ret = -ENOENT;
1641                goto probe_free_gpio;
1642        }
1643
1644        host->mem = request_mem_region(host->mem->start,
1645                                       resource_size(host->mem), pdev->name);
1646
1647        if (!host->mem) {
1648                dev_err(&pdev->dev, "failed to request io memory region.\n");
1649                ret = -ENOENT;
1650                goto probe_free_gpio;
1651        }
1652
1653        host->base = ioremap(host->mem->start, resource_size(host->mem));
1654        if (!host->base) {
1655                dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1656                ret = -EINVAL;
1657                goto probe_free_mem_region;
1658        }
1659
1660        host->irq = platform_get_irq(pdev, 0);
1661        if (host->irq == 0) {
1662                dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1663                ret = -EINVAL;
1664                goto probe_iounmap;
1665        }
1666
1667        if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1668                dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1669                ret = -ENOENT;
1670                goto probe_iounmap;
1671        }
1672
1673        /* We get spurious interrupts even when we have set the IMSK
1674         * register to ignore everything, so use disable_irq() to make
1675         * ensure we don't lock the system with un-serviceable requests. */
1676
1677        disable_irq(host->irq);
1678        host->irq_state = false;
1679
1680        /* Depending on the dma state, get a DMA channel to use. */
1681
1682        if (s3cmci_host_usedma(host)) {
1683                host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1684                ret = PTR_ERR_OR_ZERO(host->dma);
1685                if (ret) {
1686                        dev_err(&pdev->dev, "cannot get DMA channel.\n");
1687                        goto probe_free_irq;
1688                }
1689        }
1690
1691        host->clk = clk_get(&pdev->dev, "sdi");
1692        if (IS_ERR(host->clk)) {
1693                dev_err(&pdev->dev, "failed to find clock source.\n");
1694                ret = PTR_ERR(host->clk);
1695                host->clk = NULL;
1696                goto probe_free_dma;
1697        }
1698
1699        ret = clk_prepare_enable(host->clk);
1700        if (ret) {
1701                dev_err(&pdev->dev, "failed to enable clock source.\n");
1702                goto clk_free;
1703        }
1704
1705        host->clk_rate = clk_get_rate(host->clk);
1706
1707        mmc->ops        = &s3cmci_ops;
1708        mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1709#ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1710        mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1711#else
1712        mmc->caps       = MMC_CAP_4_BIT_DATA;
1713#endif
1714        mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1715        mmc->f_max      = host->clk_rate / host->clk_div;
1716
1717        if (host->pdata->ocr_avail)
1718                mmc->ocr_avail = host->pdata->ocr_avail;
1719
1720        mmc->max_blk_count      = 4095;
1721        mmc->max_blk_size       = 4095;
1722        mmc->max_req_size       = 4095 * 512;
1723        mmc->max_seg_size       = mmc->max_req_size;
1724
1725        mmc->max_segs           = 128;
1726
1727        dbg(host, dbg_debug,
1728            "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1729            (host->is2440?"2440":""),
1730            host->base, host->irq, host->irq_cd, host->dma);
1731
1732        ret = s3cmci_cpufreq_register(host);
1733        if (ret) {
1734                dev_err(&pdev->dev, "failed to register cpufreq\n");
1735                goto free_dmabuf;
1736        }
1737
1738        ret = mmc_add_host(mmc);
1739        if (ret) {
1740                dev_err(&pdev->dev, "failed to add mmc host.\n");
1741                goto free_cpufreq;
1742        }
1743
1744        s3cmci_debugfs_attach(host);
1745
1746        platform_set_drvdata(pdev, mmc);
1747        dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1748                 s3cmci_host_usedma(host) ? "dma" : "pio",
1749                 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1750
1751        return 0;
1752
1753 free_cpufreq:
1754        s3cmci_cpufreq_deregister(host);
1755
1756 free_dmabuf:
1757        clk_disable_unprepare(host->clk);
1758
1759 clk_free:
1760        clk_put(host->clk);
1761
1762 probe_free_dma:
1763        if (s3cmci_host_usedma(host))
1764                dma_release_channel(host->dma);
1765
1766 probe_free_irq:
1767        free_irq(host->irq, host);
1768
1769 probe_iounmap:
1770        iounmap(host->base);
1771
1772 probe_free_mem_region:
1773        release_mem_region(host->mem->start, resource_size(host->mem));
1774
1775 probe_free_gpio:
1776        if (!pdev->dev.of_node)
1777                for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1778                        gpio_free(i);
1779
1780 probe_free_host:
1781        mmc_free_host(mmc);
1782
1783 probe_out:
1784        return ret;
1785}
1786
1787static void s3cmci_shutdown(struct platform_device *pdev)
1788{
1789        struct mmc_host *mmc = platform_get_drvdata(pdev);
1790        struct s3cmci_host *host = mmc_priv(mmc);
1791
1792        if (host->irq_cd >= 0)
1793                free_irq(host->irq_cd, host);
1794
1795        s3cmci_debugfs_remove(host);
1796        s3cmci_cpufreq_deregister(host);
1797        mmc_remove_host(mmc);
1798        clk_disable_unprepare(host->clk);
1799}
1800
1801static int s3cmci_remove(struct platform_device *pdev)
1802{
1803        struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1804        struct s3cmci_host      *host = mmc_priv(mmc);
1805        int i;
1806
1807        s3cmci_shutdown(pdev);
1808
1809        clk_put(host->clk);
1810
1811        tasklet_disable(&host->pio_tasklet);
1812
1813        if (s3cmci_host_usedma(host))
1814                dma_release_channel(host->dma);
1815
1816        free_irq(host->irq, host);
1817
1818        if (!pdev->dev.of_node)
1819                for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1820                        gpio_free(i);
1821
1822        iounmap(host->base);
1823        release_mem_region(host->mem->start, resource_size(host->mem));
1824
1825        mmc_free_host(mmc);
1826        return 0;
1827}
1828
1829static const struct of_device_id s3cmci_dt_match[] = {
1830        {
1831                .compatible = "samsung,s3c2410-sdi",
1832                .data = (void *)0,
1833        },
1834        {
1835                .compatible = "samsung,s3c2412-sdi",
1836                .data = (void *)1,
1837        },
1838        {
1839                .compatible = "samsung,s3c2440-sdi",
1840                .data = (void *)1,
1841        },
1842        { /* sentinel */ },
1843};
1844MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
1845
1846static const struct platform_device_id s3cmci_driver_ids[] = {
1847        {
1848                .name   = "s3c2410-sdi",
1849                .driver_data    = 0,
1850        }, {
1851                .name   = "s3c2412-sdi",
1852                .driver_data    = 1,
1853        }, {
1854                .name   = "s3c2440-sdi",
1855                .driver_data    = 1,
1856        },
1857        { }
1858};
1859
1860MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1861
1862static struct platform_driver s3cmci_driver = {
1863        .driver = {
1864                .name   = "s3c-sdi",
1865                .of_match_table = s3cmci_dt_match,
1866        },
1867        .id_table       = s3cmci_driver_ids,
1868        .probe          = s3cmci_probe,
1869        .remove         = s3cmci_remove,
1870        .shutdown       = s3cmci_shutdown,
1871};
1872
1873module_platform_driver(s3cmci_driver);
1874
1875MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1876MODULE_LICENSE("GPL v2");
1877MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
1878