/*
 *  Overview:
 *   This is the generic MTD driver for NAND flash devices. It should be
 *   capable of working with almost all NAND chips currently available.
 *
 *      Additional technical information is available on
 *      http://www.linux-mtd.infradead.org/doc/nand.html
 *
 *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
 *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
 *
 *  Credits:
 *      David Woodhouse for adding multichip support
 *
 *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
 *      rework for 2K page size chips
 *
 *  TODO:
 *      Enable cached programming for 2k page size chips
 *      Check, if mtd->ecctype should be set to MTD_ECC_HW
 *      if we have HW ECC support.
 *      BBT table is not serialized, has to be fixed
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/nmi.h>
#include <linux/types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/nand_bch.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/mtd/partitions.h>
#include <linux/of.h>

static int nand_get_device(struct mtd_info *mtd, int new_state);

static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
                             struct mtd_oob_ops *ops);

/* Define default oob placement schemes for large and small page devices */
static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
                                 struct mtd_oob_region *oobregion)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct nand_ecc_ctrl *ecc = &chip->ecc;

        if (section > 1)
                return -ERANGE;

        if (!section) {
                oobregion->offset = 0;
                if (mtd->oobsize == 16)
                        oobregion->length = 4;
                else
                        oobregion->length = 3;
        } else {
                if (mtd->oobsize == 8)
                        return -ERANGE;

                oobregion->offset = 6;
                oobregion->length = ecc->total - 4;
        }

        return 0;
}

static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
                                  struct mtd_oob_region *oobregion)
{
        if (section > 1)
                return -ERANGE;

        if (mtd->oobsize == 16) {
                if (section)
                        return -ERANGE;

                oobregion->length = 8;
                oobregion->offset = 8;
        } else {
                oobregion->length = 2;
                if (!section)
                        oobregion->offset = 3;
                else
                        oobregion->offset = 6;
        }

        return 0;
}

const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
        .ecc = nand_ooblayout_ecc_sp,
        .free = nand_ooblayout_free_sp,
};
EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);

static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
                                 struct mtd_oob_region *oobregion)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct nand_ecc_ctrl *ecc = &chip->ecc;

        if (section)
                return -ERANGE;

        oobregion->length = ecc->total;
        oobregion->offset = mtd->oobsize - oobregion->length;

        return 0;
}

static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
                                  struct mtd_oob_region *oobregion)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct nand_ecc_ctrl *ecc = &chip->ecc;

        if (section)
                return -ERANGE;

        oobregion->length = mtd->oobsize - ecc->total - 2;
        oobregion->offset = 2;

        return 0;
}

const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
        .ecc = nand_ooblayout_ecc_lp,
        .free = nand_ooblayout_free_lp,
};
EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);

/*
 * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
 * are placed at a fixed offset.
 */
static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
                                         struct mtd_oob_region *oobregion)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct nand_ecc_ctrl *ecc = &chip->ecc;

        if (section)
                return -ERANGE;

        switch (mtd->oobsize) {
        case 64:
                oobregion->offset = 40;
                break;
        case 128:
                oobregion->offset = 80;
                break;
        default:
                return -EINVAL;
        }

        oobregion->length = ecc->total;
        if (oobregion->offset + oobregion->length > mtd->oobsize)
                return -ERANGE;

        return 0;
}

static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
                                          struct mtd_oob_region *oobregion)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct nand_ecc_ctrl *ecc = &chip->ecc;
        int ecc_offset = 0;

        if (section < 0 || section > 1)
                return -ERANGE;

        switch (mtd->oobsize) {
        case 64:
                ecc_offset = 40;
                break;
        case 128:
                ecc_offset = 80;
                break;
        default:
                return -EINVAL;
        }

        if (section == 0) {
                oobregion->offset = 2;
                oobregion->length = ecc_offset - 2;
        } else {
                oobregion->offset = ecc_offset + ecc->total;
                oobregion->length = mtd->oobsize - oobregion->offset;
        }

        return 0;
}

static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
        .ecc = nand_ooblayout_ecc_lp_hamming,
        .free = nand_ooblayout_free_lp_hamming,
};

static int check_offs_len(struct mtd_info *mtd,
                                        loff_t ofs, uint64_t len)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        int ret = 0;

        /* Start address must align on block boundary */
        if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
                pr_debug("%s: unaligned address\n", __func__);
                ret = -EINVAL;
        }

        /* Length must align on block boundary */
        if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
                pr_debug("%s: length not block aligned\n", __func__);
                ret = -EINVAL;
        }

        return ret;
}

/**
 * nand_release_device - [GENERIC] release chip
 * @mtd: MTD device structure
 *
 * Release chip lock and wake up anyone waiting on the device.
 */
static void nand_release_device(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        /* Release the controller and the chip */
        spin_lock(&chip->controller->lock);
        chip->controller->active = NULL;
        chip->state = FL_READY;
        wake_up(&chip->controller->wq);
        spin_unlock(&chip->controller->lock);
}

/**
 * nand_read_byte - [DEFAULT] read one byte from the chip
 * @mtd: MTD device structure
 *
 * Default read function for 8bit buswidth
 */
static uint8_t nand_read_byte(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        return readb(chip->IO_ADDR_R);
}

/**
 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 * @mtd: MTD device structure
 *
 * Default read function for 16bit buswidth with endianness conversion.
 *
 */
static uint8_t nand_read_byte16(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
}

/**
 * nand_read_word - [DEFAULT] read one word from the chip
 * @mtd: MTD device structure
 *
 * Default read function for 16bit buswidth without endianness conversion.
 */
static u16 nand_read_word(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        return readw(chip->IO_ADDR_R);
}

/**
 * nand_select_chip - [DEFAULT] control CE line
 * @mtd: MTD device structure
 * @chipnr: chipnumber to select, -1 for deselect
 *
 * Default select function for 1 chip devices.
 */
static void nand_select_chip(struct mtd_info *mtd, int chipnr)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        switch (chipnr) {
        case -1:
                chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
                break;
        case 0:
                break;

        default:
                BUG();
        }
}

/**
 * nand_write_byte - [DEFAULT] write single byte to chip
 * @mtd: MTD device structure
 * @byte: value to write
 *
 * Default function to write a byte to I/O[7:0]
 */
static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        chip->write_buf(mtd, &byte, 1);
}

/**
 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 * @mtd: MTD device structure
 * @byte: value to write
 *
 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 */
static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        uint16_t word = byte;

        /*
         * It's not entirely clear what should happen to I/O[15:8] when writing
         * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
         *
         *    When the host supports a 16-bit bus width, only data is
         *    transferred at the 16-bit width. All address and command line
         *    transfers shall use only the lower 8-bits of the data bus. During
         *    command transfers, the host may place any value on the upper
         *    8-bits of the data bus. During address transfers, the host shall
         *    set the upper 8-bits of the data bus to 00h.
         *
         * One user of the write_byte callback is nand_onfi_set_features. The
         * four parameters are specified to be written to I/O[7:0], but this is
         * neither an address nor a command transfer. Let's assume a 0 on the
         * upper I/O lines is OK.
         */
        chip->write_buf(mtd, (uint8_t *)&word, 2);
}

/**
 * nand_write_buf - [DEFAULT] write buffer to chip
 * @mtd: MTD device structure
 * @buf: data buffer
 * @len: number of bytes to write
 *
 * Default write function for 8bit buswidth.
 */
static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        iowrite8_rep(chip->IO_ADDR_W, buf, len);
}

/**
 * nand_read_buf - [DEFAULT] read chip data into buffer
 * @mtd: MTD device structure
 * @buf: buffer to store date
 * @len: number of bytes to read
 *
 * Default read function for 8bit buswidth.
 */
static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        ioread8_rep(chip->IO_ADDR_R, buf, len);
}

/**
 * nand_write_buf16 - [DEFAULT] write buffer to chip
 * @mtd: MTD device structure
 * @buf: data buffer
 * @len: number of bytes to write
 *
 * Default write function for 16bit buswidth.
 */
static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        u16 *p = (u16 *) buf;

        iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
}

/**
 * nand_read_buf16 - [DEFAULT] read chip data into buffer
 * @mtd: MTD device structure
 * @buf: buffer to store date
 * @len: number of bytes to read
 *
 * Default read function for 16bit buswidth.
 */
static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        u16 *p = (u16 *) buf;

        ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
}

/**
 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
 * Check, if the block is bad.
 */
static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
{
        int page, page_end, res;
        struct nand_chip *chip = mtd_to_nand(mtd);
        u8 bad;

        if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
                ofs += mtd->erasesize - mtd->writesize;

        page = (int)(ofs >> chip->page_shift) & chip->pagemask;
        page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1);

        for (; page < page_end; page++) {
                res = chip->ecc.read_oob(mtd, chip, page);
                if (res)
                        return res;

                bad = chip->oob_poi[chip->badblockpos];

                if (likely(chip->badblockbits == 8))
                        res = bad != 0xFF;
                else
                        res = hweight8(bad) < chip->badblockbits;
                if (res)
                        return res;
        }

        return 0;
}

/**
 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
 * This is the default implementation, which can be overridden by a hardware
 * specific driver. It provides the details for writing a bad block marker to a
 * block.
 */
static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct mtd_oob_ops ops;
        uint8_t buf[2] = { 0, 0 };
        int ret = 0, res, i = 0;

        memset(&ops, 0, sizeof(ops));
        ops.oobbuf = buf;
        ops.ooboffs = chip->badblockpos;
        if (chip->options & NAND_BUSWIDTH_16) {
                ops.ooboffs &= ~0x01;
                ops.len = ops.ooblen = 2;
        } else {
                ops.len = ops.ooblen = 1;
        }
        ops.mode = MTD_OPS_PLACE_OOB;

        /* Write to first/last page(s) if necessary */
        if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
                ofs += mtd->erasesize - mtd->writesize;
        do {
                res = nand_do_write_oob(mtd, ofs, &ops);
                if (!ret)
                        ret = res;

                i++;
                ofs += mtd->writesize;
        } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);

        return ret;
}

/**
 * nand_block_markbad_lowlevel - mark a block bad
 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
 * This function performs the generic NAND bad block marking steps (i.e., bad
 * block table(s) and/or marker(s)). We only allow the hardware driver to
 * specify how to write bad block markers to OOB (chip->block_markbad).
 *
 * We try operations in the following order:
 *
 *  (1) erase the affected block, to allow OOB marker to be written cleanly
 *  (2) write bad block marker to OOB area of affected block (unless flag
 *      NAND_BBT_NO_OOB_BBM is present)
 *  (3) update the BBT
 *
 * Note that we retain the first error encountered in (2) or (3), finish the
 * procedures, and dump the error in the end.
*/
static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        int res, ret = 0;

        if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
                struct erase_info einfo;

                /* Attempt erase before marking OOB */
                memset(&einfo, 0, sizeof(einfo));
                einfo.mtd = mtd;
                einfo.addr = ofs;
                einfo.len = 1ULL << chip->phys_erase_shift;
                nand_erase_nand(mtd, &einfo, 0);

                /* Write bad block marker to OOB */
                nand_get_device(mtd, FL_WRITING);
                ret = chip->block_markbad(mtd, ofs);
                nand_release_device(mtd);
        }

        /* Mark block bad in BBT */
        if (chip->bbt) {
                res = nand_markbad_bbt(mtd, ofs);
                if (!ret)
                        ret = res;
        }

        if (!ret)
                mtd->ecc_stats.badblocks++;

        return ret;
}

/**
 * nand_check_wp - [GENERIC] check if the chip is write protected
 * @mtd: MTD device structure
 *
 * Check, if the device is write protected. The function expects, that the
 * device is already selected.
 */
static int nand_check_wp(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        /* Broken xD cards report WP despite being writable */
        if (chip->options & NAND_BROKEN_XD)
                return 0;

        /* Check the WP bit */
        chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
        return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
}

/**
 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
 * Check if the block is marked as reserved.
 */
static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        if (!chip->bbt)
                return 0;
        /* Return info from the table */
        return nand_isreserved_bbt(mtd, ofs);
}

/**
 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 * @mtd: MTD device structure
 * @ofs: offset from device start
 * @allowbbt: 1, if its allowed to access the bbt area
 *
 * Check, if the block is bad. Either by reading the bad block table or
 * calling of the scan function.
 */
static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        if (!chip->bbt)
                return chip->block_bad(mtd, ofs);

        /* Return info from the table */
        return nand_isbad_bbt(mtd, ofs, allowbbt);
}

/**
 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 * @mtd: MTD device structure
 * @timeo: Timeout
 *
 * Helper function for nand_wait_ready used when needing to wait in interrupt
 * context.
 */
static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        int i;

        /* Wait for the device to get ready */
        for (i = 0; i < timeo; i++) {
                if (chip->dev_ready(mtd))
                        break;
                touch_softlockup_watchdog();
                mdelay(1);
        }
}

/**
 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 * @mtd: MTD device structure
 *
 * Wait for the ready pin after a command, and warn if a timeout occurs.
 */
void nand_wait_ready(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        unsigned long timeo = 400;

        if (in_interrupt() || oops_in_progress)
                return panic_nand_wait_ready(mtd, timeo);

        /* Wait until command is processed or timeout occurs */
        timeo = jiffies + msecs_to_jiffies(timeo);
        do {
                if (chip->dev_ready(mtd))
                        return;
                cond_resched();
        } while (time_before(jiffies, timeo));

        if (!chip->dev_ready(mtd))
                pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
}
EXPORT_SYMBOL_GPL(nand_wait_ready);

/**
 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
 * @mtd: MTD device structure
 * @timeo: Timeout in ms
 *
 * Wait for status ready (i.e. command done) or timeout.
 */
static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
{
        register struct nand_chip *chip = mtd_to_nand(mtd);

        timeo = jiffies + msecs_to_jiffies(timeo);
        do {
                if ((chip->read_byte(mtd) & NAND_STATUS_READY))
                        break;
                touch_softlockup_watchdog();
        } while (time_before(jiffies, timeo));
};

/**
 * nand_command - [DEFAULT] Send command to NAND device
 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
 *
 * Send command to NAND device. This function is used for small page devices
 * (512 Bytes per page).
 */
static void nand_command(struct mtd_info *mtd, unsigned int command,
                         int column, int page_addr)
{
        register struct nand_chip *chip = mtd_to_nand(mtd);
        int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;

        /* Write out the command to the device */
        if (command == NAND_CMD_SEQIN) {
                int readcmd;

                if (column >= mtd->writesize) {
                        /* OOB area */
                        column -= mtd->writesize;
                        readcmd = NAND_CMD_READOOB;
                } else if (column < 256) {
                        /* First 256 bytes --> READ0 */
                        readcmd = NAND_CMD_READ0;
                } else {
                        column -= 256;
                        readcmd = NAND_CMD_READ1;
                }
                chip->cmd_ctrl(mtd, readcmd, ctrl);
                ctrl &= ~NAND_CTRL_CHANGE;
        }
        chip->cmd_ctrl(mtd, command, ctrl);

        /* Address cycle, when necessary */
        ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
        /* Serially input address */
        if (column != -1) {
                /* Adjust columns for 16 bit buswidth */
                if (chip->options & NAND_BUSWIDTH_16 &&
                                !nand_opcode_8bits(command))
                        column >>= 1;
                chip->cmd_ctrl(mtd, column, ctrl);
                ctrl &= ~NAND_CTRL_CHANGE;
        }
        if (page_addr != -1) {
                chip->cmd_ctrl(mtd, page_addr, ctrl);
                ctrl &= ~NAND_CTRL_CHANGE;
                chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
                /* One more address cycle for devices > 32MiB */
                if (chip->chipsize > (32 << 20))
                        chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
        }
        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

        /*
         * Program and erase have their own busy handlers status and sequential
         * in needs no delay
         */
        switch (command) {

        case NAND_CMD_PAGEPROG:
        case NAND_CMD_ERASE1:
        case NAND_CMD_ERASE2:
        case NAND_CMD_SEQIN:
        case NAND_CMD_STATUS:
        case NAND_CMD_READID:
        case NAND_CMD_SET_FEATURES:
                return;

        case NAND_CMD_RESET:
                if (chip->dev_ready)
                        break;
                udelay(chip->chip_delay);
                chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
                               NAND_CTRL_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd,
                               NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
                /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
                nand_wait_status_ready(mtd, 250);
                return;

                /* This applies to read commands */
        case NAND_CMD_READ0:
                /*
                 * READ0 is sometimes used to exit GET STATUS mode. When this
                 * is the case no address cycles are requested, and we can use
                 * this information to detect that we should not wait for the
                 * device to be ready.
                 */
                if (column == -1 && page_addr == -1)
                        return;

        default:
                /*
                 * If we don't have access to the busy pin, we apply the given
                 * command delay
                 */
                if (!chip->dev_ready) {
                        udelay(chip->chip_delay);
                        return;
                }
        }
        /*
         * Apply this short delay always to ensure that we do wait tWB in
         * any case on any machine.
         */
        ndelay(100);

        nand_wait_ready(mtd);
}

static void nand_ccs_delay(struct nand_chip *chip)
{
        /*
         * The controller already takes care of waiting for tCCS when the RNDIN
         * or RNDOUT command is sent, return directly.
         */
        if (!(chip->options & NAND_WAIT_TCCS))
                return;

        /*
         * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
         * (which should be safe for all NANDs).
         */
        if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min)
                ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000);
        else
                ndelay(500);
}

/**
 * nand_command_lp - [DEFAULT] Send command to NAND large page device
 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
 *
 * Send command to NAND device. This is the version for the new large page
 * devices. We don't have the separate regions as we have in the small page
 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 */
static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
                            int column, int page_addr)
{
        register struct nand_chip *chip = mtd_to_nand(mtd);

        /* Emulate NAND_CMD_READOOB */
        if (command == NAND_CMD_READOOB) {
                column += mtd->writesize;
                command = NAND_CMD_READ0;
        }

        /* Command latch cycle */
        chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);

        if (column != -1 || page_addr != -1) {
                int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;

                /* Serially input address */
                if (column != -1) {
                        /* Adjust columns for 16 bit buswidth */
                        if (chip->options & NAND_BUSWIDTH_16 &&
                                        !nand_opcode_8bits(command))
                                column >>= 1;
                        chip->cmd_ctrl(mtd, column, ctrl);
                        ctrl &= ~NAND_CTRL_CHANGE;

                        /* Only output a single addr cycle for 8bits opcodes. */
                        if (!nand_opcode_8bits(command))
                                chip->cmd_ctrl(mtd, column >> 8, ctrl);
                }
                if (page_addr != -1) {
                        chip->cmd_ctrl(mtd, page_addr, ctrl);
                        chip->cmd_ctrl(mtd, page_addr >> 8,
                                       NAND_NCE | NAND_ALE);
                        /* One more address cycle for devices > 128MiB */
                        if (chip->chipsize > (128 << 20))
                                chip->cmd_ctrl(mtd, page_addr >> 16,
                                               NAND_NCE | NAND_ALE);
                }
        }
        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

        /*
         * Program and erase have their own busy handlers status, sequential
         * in and status need no delay.
         */
        switch (command) {

        case NAND_CMD_CACHEDPROG:
        case NAND_CMD_PAGEPROG:
        case NAND_CMD_ERASE1:
        case NAND_CMD_ERASE2:
        case NAND_CMD_SEQIN:
        case NAND_CMD_STATUS:
        case NAND_CMD_READID:
        case NAND_CMD_SET_FEATURES:
                return;

        case NAND_CMD_RNDIN:
                nand_ccs_delay(chip);
                return;

        case NAND_CMD_RESET:
                if (chip->dev_ready)
                        break;
                udelay(chip->chip_delay);
                chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
                               NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                               NAND_NCE | NAND_CTRL_CHANGE);
                /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
                nand_wait_status_ready(mtd, 250);
                return;

        case NAND_CMD_RNDOUT:
                /* No ready / busy check necessary */
                chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
                               NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                               NAND_NCE | NAND_CTRL_CHANGE);

                nand_ccs_delay(chip);
                return;

        case NAND_CMD_READ0:
                /*
                 * READ0 is sometimes used to exit GET STATUS mode. When this
                 * is the case no address cycles are requested, and we can use
                 * this information to detect that READSTART should not be
                 * issued.
                 */
                if (column == -1 && page_addr == -1)
                        return;

                chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
                               NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                               NAND_NCE | NAND_CTRL_CHANGE);

                /* This applies to read commands */
        default:
                /*
                 * If we don't have access to the busy pin, we apply the given
                 * command delay.
                 */
                if (!chip->dev_ready) {
                        udelay(chip->chip_delay);
                        return;
                }
        }

        /*
         * Apply this short delay always to ensure that we do wait tWB in
         * any case on any machine.
         */
        ndelay(100);

        nand_wait_ready(mtd);
}

/**
 * panic_nand_get_device - [GENERIC] Get chip for selected access
 * @chip: the nand chip descriptor
 * @mtd: MTD device structure
 * @new_state: the state which is requested
 *
 * Used when in panic, no locks are taken.
 */
static void panic_nand_get_device(struct nand_chip *chip,
                      struct mtd_info *mtd, int new_state)
{
        /* Hardware controller shared among independent devices */
        chip->controller->active = chip;
        chip->state = new_state;
}

/**
 * nand_get_device - [GENERIC] Get chip for selected access
 * @mtd: MTD device structure
 * @new_state: the state which is requested
 *
 * Get the device and lock it for exclusive access
 */
static int
nand_get_device(struct mtd_info *mtd, int new_state)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        spinlock_t *lock = &chip->controller->lock;
        wait_queue_head_t *wq = &chip->controller->wq;
        DECLARE_WAITQUEUE(wait, current);
retry:
        spin_lock(lock);

        /* Hardware controller shared among independent devices */
        if (!chip->controller->active)
                chip->controller->active = chip;

        if (chip->controller->active == chip && chip->state == FL_READY) {
                chip->state = new_state;
                spin_unlock(lock);
                return 0;
        }
        if (new_state == FL_PM_SUSPENDED) {
                if (chip->controller->active->state == FL_PM_SUSPENDED) {
                        chip->state = FL_PM_SUSPENDED;
                        spin_unlock(lock);
                        return 0;
                }
        }
        set_current_state(TASK_UNINTERRUPTIBLE);
        add_wait_queue(wq, &wait);
        spin_unlock(lock);
        schedule();
        remove_wait_queue(wq, &wait);
        goto retry;
}

/**

 * panic_nand_wait - [GENERIC] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
 * @timeo: timeout
 *
 * Wait for command done. This is a helper function for nand_wait used when
 * we are in interrupt context. May happen when in panic and trying to write
 * an oops through mtdoops.
 */
static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
                            unsigned long timeo)
{
        int i;
        for (i = 0; i < timeo; i++) {
                if (chip->dev_ready) {
                        if (chip->dev_ready(mtd))
                                break;
                } else {
                        if (chip->read_byte(mtd) & NAND_STATUS_READY)
                                break;
                }
                mdelay(1);
        }
}

/**
 * nand_wait - [DEFAULT] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
 *
 * Wait for command done. This applies to erase and program only.
 */
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{

        int status;
        unsigned long timeo = 400;

        /*
         * Apply this short delay always to ensure that we do wait tWB in any
         * case on any machine.
         */
        ndelay(100);

        chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);

        if (in_interrupt() || oops_in_progress)
                panic_nand_wait(mtd, chip, timeo);
        else {
                timeo = jiffies + msecs_to_jiffies(timeo);
                do {
                        if (chip->dev_ready) {
                                if (chip->dev_ready(mtd))
                                        break;
                        } else {
                                if (chip->read_byte(mtd) & NAND_STATUS_READY)
                                        break;
                        }
                        cond_resched();
                } while (time_before(jiffies, timeo));
        }

        status = (int)chip->read_byte(mtd);
        /* This can happen if in case of timeout or buggy dev_ready */
        WARN_ON(!(status & NAND_STATUS_READY));
        return status;
}

/**
 * nand_reset_data_interface - Reset data interface and timings
 * @chip: The NAND chip
 * @chipnr: Internal die id
 *
 * Reset the Data interface and timings to ONFI mode 0.
 *
 * Returns 0 for success or negative error code otherwise.
 */
static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
{
        struct mtd_info *mtd = nand_to_mtd(chip);
        const struct nand_data_interface *conf;
        int ret;

        if (!chip->setup_data_interface)
                return 0;

        /*
         * The ONFI specification says:
         * "
         * To transition from NV-DDR or NV-DDR2 to the SDR data
         * interface, the host shall use the Reset (FFh) command
         * using SDR timing mode 0. A device in any timing mode is
         * required to recognize Reset (FFh) command issued in SDR
         * timing mode 0.
         * "
         *
         * Configure the data interface in SDR mode and set the
         * timings to timing mode 0.
         */

        conf = nand_get_default_data_interface();
        ret = chip->setup_data_interface(mtd, chipnr, conf);
        if (ret)
                pr_err("Failed to configure data interface to SDR timing mode 0\n");

        return ret;
}

/**
 * nand_setup_data_interface - Setup the best data interface and timings
 * @chip: The NAND chip
 * @chipnr: Internal die id
 *
 * Find and configure the best data interface and NAND timings supported by
 * the chip and the driver.
 * First tries to retrieve supported timing modes from ONFI information,
 * and if the NAND chip does not support ONFI, relies on the
 * ->onfi_timing_mode_default specified in the nand_ids table.
 *
 * Returns 0 for success or negative error code otherwise.
 */
static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
{
        struct mtd_info *mtd = nand_to_mtd(chip);
        int ret;

        if (!chip->setup_data_interface || !chip->data_interface)
                return 0;

        /*
         * Ensure the timing mode has been changed on the chip side
         * before changing timings on the controller side.
         */
        if (chip->onfi_version &&
            (le16_to_cpu(chip->onfi_params.opt_cmd) &
             ONFI_OPT_CMD_SET_GET_FEATURES)) {
                u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
                        chip->onfi_timing_mode_default,
                };

                ret = chip->onfi_set_features(mtd, chip,
                                ONFI_FEATURE_ADDR_TIMING_MODE,
                                tmode_param);
                if (ret)
                        goto err;
        }

        ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
err:
        return ret;
}

/**
 * nand_init_data_interface - find the best data interface and timings
 * @chip: The NAND chip
 *
 * Find the best data interface and NAND timings supported by the chip
 * and the driver.
 * First tries to retrieve supported timing modes from ONFI information,
 * and if the NAND chip does not support ONFI, relies on the
 * ->onfi_timing_mode_default specified in the nand_ids table. After this
 * function nand_chip->data_interface is initialized with the best timing mode
 * available.
 *
 * Returns 0 for success or negative error code otherwise.
 */
static int nand_init_data_interface(struct nand_chip *chip)
{
        struct mtd_info *mtd = nand_to_mtd(chip);
        int modes, mode, ret;

        if (!chip->setup_data_interface)
                return 0;

        /*
         * First try to identify the best timings from ONFI parameters and
         * if the NAND does not support ONFI, fallback to the default ONFI
         * timing mode.
         */
        modes = onfi_get_async_timing_mode(chip);
        if (modes == ONFI_TIMING_MODE_UNKNOWN) {
                if (!chip->onfi_timing_mode_default)
                        return 0;

                modes = GENMASK(chip->onfi_timing_mode_default, 0);
        }

        chip->data_interface = kzalloc(sizeof(*chip->data_interface),
                                       GFP_KERNEL);
        if (!chip->data_interface)
                return -ENOMEM;

        for (mode = fls(modes) - 1; mode >= 0; mode--) {
                ret = onfi_init_data_interface(chip, chip->data_interface,
                                               NAND_SDR_IFACE, mode);
                if (ret)
                        continue;

                /* Pass -1 to only */
                ret = chip->setup_data_interface(mtd,
                                                 NAND_DATA_IFACE_CHECK_ONLY,
                                                 chip->data_interface);
                if (!ret) {
                        chip->onfi_timing_mode_default = mode;
                        break;
                }
        }

        return 0;
}

static void nand_release_data_interface(struct nand_chip *chip)
{
        kfree(chip->data_interface);
}

/**
 * nand_reset - Reset and initialize a NAND device
 * @chip: The NAND chip
 * @chipnr: Internal die id
 *
 * Returns 0 for success or negative error code otherwise
 */
int nand_reset(struct nand_chip *chip, int chipnr)
{
        struct mtd_info *mtd = nand_to_mtd(chip);
        int ret;

        ret = nand_reset_data_interface(chip, chipnr);
        if (ret)
                return ret;

        /*
         * The CS line has to be released before we can apply the new NAND
         * interface settings, hence this weird ->select_chip() dance.
         */
        chip->select_chip(mtd, chipnr);
        chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
        chip->select_chip(mtd, -1);

        chip->select_chip(mtd, chipnr);
        ret = nand_setup_data_interface(chip, chipnr);
        chip->select_chip(mtd, -1);
        if (ret)
                return ret;

        return 0;
}

/**
 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 * @mtd: mtd info
 * @ofs: offset to start unlock from
 * @len: length to unlock
 * @invert:
 *        - when = 0, unlock the range of blocks within the lower and
 *                    upper boundary address
 *        - when = 1, unlock the range of blocks outside the boundaries
 *                    of the lower and upper boundary address
 *
 * Returs unlock status.
 */
static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
                                        uint64_t len, int invert)
{
        int ret = 0;
        int status, page;
        struct nand_chip *chip = mtd_to_nand(mtd);

        /* Submit address of first page to unlock */
        page = ofs >> chip->page_shift;
        chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);

        /* Submit address of last page to unlock */
        page = (ofs + len) >> chip->page_shift;
        chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
                                (page | invert) & chip->pagemask);

        /* Call wait ready function */
        status = chip->waitfunc(mtd, chip);
        /* See if device thinks it succeeded */
        if (status & NAND_STATUS_FAIL) {
                pr_debug("%s: error status = 0x%08x\n",
                                        __func__, status);
                ret = -EIO;
        }

        return ret;
}

/**
 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 * @mtd: mtd info
 * @ofs: offset to start unlock from
 * @len: length to unlock
 *
 * Returns unlock status.
 */
int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
        int ret = 0;
        int chipnr;
        struct nand_chip *chip = mtd_to_nand(mtd);

        pr_debug("%s: start = 0x%012llx, len = %llu\n",
                        __func__, (unsigned long long)ofs, len);

        if (check_offs_len(mtd, ofs, len))
                return -EINVAL;

        /* Align to last block address if size addresses end of the device */
        if (ofs + len == mtd->size)
                len -= mtd->erasesize;

        nand_get_device(mtd, FL_UNLOCKING);

        /* Shift to get chip number */
        chipnr = ofs >> chip->chip_shift;

        /*
         * Reset the chip.
         * If we want to check the WP through READ STATUS and check the bit 7
         * we must reset the chip
         * some operation can also clear the bit 7 of status register
         * eg. erase/program a locked block
         */
        nand_reset(chip, chipnr);

        chip->select_chip(mtd, chipnr);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd)) {
                pr_debug("%s: device is write protected!\n",
                                        __func__);
                ret = -EIO;
                goto out;
        }

        ret = __nand_unlock(mtd, ofs, len, 0);

out:
        chip->select_chip(mtd, -1);
        nand_release_device(mtd);

        return ret;
}
EXPORT_SYMBOL(nand_unlock);

/**
 * nand_lock - [REPLACEABLE] locks all blocks present in the device
 * @mtd: mtd info
 * @ofs: offset to start unlock from
 * @len: length to unlock
 *
 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 * have this feature, but it allows only to lock all blocks, not for specified
 * range for block. Implementing 'lock' feature by making use of 'unlock', for
 * now.
 *
 * Returns lock status.
 */
int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
        int ret = 0;
        int chipnr, status, page;
        struct nand_chip *chip = mtd_to_nand(mtd);

        pr_debug("%s: start = 0x%012llx, len = %llu\n",
                        __func__, (unsigned long long)ofs, len);

        if (check_offs_len(mtd, ofs, len))
                return -EINVAL;

        nand_get_device(mtd, FL_LOCKING);

        /* Shift to get chip number */
        chipnr = ofs >> chip->chip_shift;

        /*
         * Reset the chip.
         * If we want to check the WP through READ STATUS and check the bit 7
         * we must reset the chip
         * some operation can also clear the bit 7 of status register
         * eg. erase/program a locked block
         */
        nand_reset(chip, chipnr);

        chip->select_chip(mtd, chipnr);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd)) {
                pr_debug("%s: device is write protected!\n",
                                        __func__);
                status = MTD_ERASE_FAILED;
                ret = -EIO;
                goto out;
        }

        /* Submit address of first page to lock */
        page = ofs >> chip->page_shift;
        chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);

        /* Call wait ready function */
        status = chip->waitfunc(mtd, chip);
        /* See if device thinks it succeeded */
        if (status & NAND_STATUS_FAIL) {
                pr_debug("%s: error status = 0x%08x\n",
                                        __func__, status);
                ret = -EIO;
                goto out;
        }

        ret = __nand_unlock(mtd, ofs, len, 0x1);

out:
        chip->select_chip(mtd, -1);
        nand_release_device(mtd);

        return ret;
}
EXPORT_SYMBOL(nand_lock);

/**
 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
 * @buf: buffer to test
 * @len: buffer length
 * @bitflips_threshold: maximum number of bitflips
 *
 * Check if a buffer contains only 0xff, which means the underlying region
 * has been erased and is ready to be programmed.
 * The bitflips_threshold specify the maximum number of bitflips before
 * considering the region is not erased.
 * Note: The logic of this function has been extracted from the memweight
 * implementation, except that nand_check_erased_buf function exit before
 * testing the whole buffer if the number of bitflips exceed the
 * bitflips_threshold value.
 *
 * Returns a positive number of bitflips less than or equal to
 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
 * threshold.
 */
static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
{
        const unsigned char *bitmap = buf;
        int bitflips = 0;
        int weight;

        for (; len && ((uintptr_t)bitmap) % sizeof(long);
             len--, bitmap++) {
                weight = hweight8(*bitmap);
                bitflips += BITS_PER_BYTE - weight;
                if (unlikely(bitflips > bitflips_threshold))
                        return -EBADMSG;
        }

        for (; len >= sizeof(long);
             len -= sizeof(long), bitmap += sizeof(long)) {
                unsigned long d = *((unsigned long *)bitmap);
                if (d == ~0UL)
                        continue;
                weight = hweight_long(d);
                bitflips += BITS_PER_LONG - weight;
                if (unlikely(bitflips > bitflips_threshold))
                        return -EBADMSG;
        }

        for (; len > 0; len--, bitmap++) {
                weight = hweight8(*bitmap);
                bitflips += BITS_PER_BYTE - weight;
                if (unlikely(bitflips > bitflips_threshold))
                        return -EBADMSG;
        }

        return bitflips;
}

/**
 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
 *                               0xff data
 * @data: data buffer to test
 * @datalen: data length
 * @ecc: ECC buffer
 * @ecclen: ECC length
 * @extraoob: extra OOB buffer
 * @extraooblen: extra OOB length
 * @bitflips_threshold: maximum number of bitflips
 *
 * Check if a data buffer and its associated ECC and OOB data contains only
 * 0xff pattern, which means the underlying region has been erased and is
 * ready to be programmed.
 * The bitflips_threshold specify the maximum number of bitflips before
 * considering the region as not erased.
 *
 * Note:
 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
 *    different from the NAND page size. When fixing bitflips, ECC engines will
 *    report the number of errors per chunk, and the NAND core infrastructure
 *    expect you to return the maximum number of bitflips for the whole page.
 *    This is why you should always use this function on a single chunk and
 *    not on the whole page. After checking each chunk you should update your
 *    max_bitflips value accordingly.
 * 2/ When checking for bitflips in erased pages you should not only check
 *    the payload data but also their associated ECC data, because a user might
 *    have programmed almost all bits to 1 but a few. In this case, we
 *    shouldn't consider the chunk as erased, and checking ECC bytes prevent
 *    this case.
 * 3/ The extraoob argument is optional, and should be used if some of your OOB
 *    data are protected by the ECC engine.
 *    It could also be used if you support subpages and want to attach some
 *    extra OOB data to an ECC chunk.
 *
 * Returns a positive number of bitflips less than or equal to
 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
 * threshold. In case of success, the passed buffers are filled with 0xff.
 */
int nand_check_erased_ecc_chunk(void *data, int datalen,
                                void *ecc, int ecclen,
                                void *extraoob, int extraooblen,
                                int bitflips_threshold)
{
        int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;

        data_bitflips = nand_check_erased_buf(data, datalen,
                                              bitflips_threshold);
        if (data_bitflips < 0)
                return data_bitflips;

        bitflips_threshold -= data_bitflips;

        ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
        if (ecc_bitflips < 0)
                return ecc_bitflips;

        bitflips_threshold -= ecc_bitflips;

        extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
                                                  bitflips_threshold);
        if (extraoob_bitflips < 0)
                return extraoob_bitflips;

        if (data_bitflips)
                memset(data, 0xff, datalen);

        if (ecc_bitflips)
                memset(ecc, 0xff, ecclen);

        if (extraoob_bitflips)
                memset(extraoob, 0xff, extraooblen);

        return data_bitflips + ecc_bitflips + extraoob_bitflips;
}
EXPORT_SYMBOL(nand_check_erased_ecc_chunk);

/**
 * nand_read_page_raw - [INTERN] read raw page data without ecc
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @oob_required: caller requires OOB data read to chip->oob_poi
 * @page: page number to read
 *
 * Not for syndrome calculating ECC controllers, which use a special oob layout.
 */
int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
                       uint8_t *buf, int oob_required, int page)
{
        chip->read_buf(mtd, buf, mtd->writesize);
        if (oob_required)
                chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        return 0;
}
EXPORT_SYMBOL(nand_read_page_raw);

/**
 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @oob_required: caller requires OOB data read to chip->oob_poi
 * @page: page number to read
 *
 * We need a special oob layout and handling even when OOB isn't used.
 */
static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
                                       struct nand_chip *chip, uint8_t *buf,
                                       int oob_required, int page)
{
        int eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        uint8_t *oob = chip->oob_poi;
        int steps, size;

        for (steps = chip->ecc.steps; steps > 0; steps--) {
                chip->read_buf(mtd, buf, eccsize);
                buf += eccsize;

                if (chip->ecc.prepad) {
                        chip->read_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->read_buf(mtd, oob, eccbytes);
                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->read_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }
        }

        size = mtd->oobsize - (oob - chip->oob_poi);
        if (size)
                chip->read_buf(mtd, oob, size);

        return 0;
}

/**
 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @oob_required: caller requires OOB data read to chip->oob_poi
 * @page: page number to read
 */
static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
                                uint8_t *buf, int oob_required, int page)
{
        int i, eccsize = chip->ecc.size, ret;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *p = buf;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        uint8_t *ecc_code = chip->buffers->ecccode;
        unsigned int max_bitflips = 0;

        chip->ecc.read_page_raw(mtd, chip, buf, 1, page);

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);

        ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
                                         chip->ecc.total);
        if (ret)
                return ret;

        eccsteps = chip->ecc.steps;
        p = buf;

        for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
                if (stat < 0) {
                        mtd->ecc_stats.failed++;
                } else {
                        mtd->ecc_stats.corrected += stat;
                        max_bitflips = max_t(unsigned int, max_bitflips, stat);
                }
        }
        return max_bitflips;
}

/**
 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @data_offs: offset of requested data within the page
 * @readlen: data length
 * @bufpoi: buffer to store read data
 * @page: page number to read
 */
static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
                        uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
                        int page)
{
        int start_step, end_step, num_steps, ret;
        uint8_t *p;
        int data_col_addr, i, gaps = 0;
        int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
        int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
        int index, section = 0;
        unsigned int max_bitflips = 0;
        struct mtd_oob_region oobregion = { };

        /* Column address within the page aligned to ECC size (256bytes) */
        start_step = data_offs / chip->ecc.size;
        end_step = (data_offs + readlen - 1) / chip->ecc.size;
        num_steps = end_step - start_step + 1;
        index = start_step * chip->ecc.bytes;

        /* Data size aligned to ECC ecc.size */
        datafrag_len = num_steps * chip->ecc.size;
        eccfrag_len = num_steps * chip->ecc.bytes;

        data_col_addr = start_step * chip->ecc.size;
        /* If we read not a page aligned data */
        if (data_col_addr != 0)
                chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);

        p = bufpoi + data_col_addr;
        chip->read_buf(mtd, p, datafrag_len);

        /* Calculate ECC */
        for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
                chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);

        /*
         * The performance is faster if we position offsets according to
         * ecc.pos. Let's make sure that there are no gaps in ECC positions.
         */
        ret = mtd_ooblayout_find_eccregion(mtd, index, &section, &oobregion);
        if (ret)
                return ret;

        if (oobregion.length < eccfrag_len)
                gaps = 1;

        if (gaps) {
                chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
                chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        } else {
                /*
                 * Send the command to read the particular ECC bytes take care
                 * about buswidth alignment in read_buf.
                 */
                aligned_pos = oobregion.offset & ~(busw - 1);
                aligned_len = eccfrag_len;
                if (oobregion.offset & (busw - 1))
                        aligned_len++;
                if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
                    (busw - 1))
                        aligned_len++;

                chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
                              mtd->writesize + aligned_pos, -1);
                chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
        }

        ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode,
                                         chip->oob_poi, index, eccfrag_len);
        if (ret)
                return ret;

        p = bufpoi + data_col_addr;
        for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
                int stat;

                stat = chip->ecc.correct(mtd, p,
                        &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
                if (stat == -EBADMSG &&
                    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
                        /* check for empty pages with bitflips */
                        stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
                                                &chip->buffers->ecccode[i],
                                                chip->ecc.bytes,
                                                NULL, 0,
                                                chip->ecc.strength);
                }

                if (stat < 0) {
                        mtd->ecc_stats.failed++;
                } else {
                        mtd->ecc_stats.corrected += stat;
                        max_bitflips = max_t(unsigned int, max_bitflips, stat);
                }
        }
        return max_bitflips;
}

/**
 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @oob_required: caller requires OOB data read to chip->oob_poi
 * @page: page number to read
 *
 * Not for syndrome calculating ECC controllers which need a special oob layout.
 */
static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
                                uint8_t *buf, int oob_required, int page)
{
        int i, eccsize = chip->ecc.size, ret;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *p = buf;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        uint8_t *ecc_code = chip->buffers->ecccode;
        unsigned int max_bitflips = 0;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                chip->ecc.hwctl(mtd, NAND_ECC_READ);
                chip->read_buf(mtd, p, eccsize);
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);
        }
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);

        ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
                                         chip->ecc.total);
        if (ret)
                return ret;

        eccsteps = chip->ecc.steps;
        p = buf;

        for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
                if (stat == -EBADMSG &&
                    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
                        /* check for empty pages with bitflips */
                        stat = nand_check_erased_ecc_chunk(p, eccsize,
                                                &ecc_code[i], eccbytes,
                                                NULL, 0,
                                                chip->ecc.strength);
                }

                if (stat < 0) {
                        mtd->ecc_stats.failed++;
                } else {
                        mtd->ecc_stats.corrected += stat;
                        max_bitflips = max_t(unsigned int, max_bitflips, stat);
                }
        }
        return max_bitflips;
}

/**
 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @oob_required: caller requires OOB data read to chip->oob_poi
 * @page: page number to read
 *
 * Hardware ECC for large page chips, require OOB to be read first. For this
 * ECC mode, the write_page method is re-used from ECC_HW. These methods
 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
 * the data area, by overwriting the NAND manufacturer bad block markings.
 */
static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
        struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
{
        int i, eccsize = chip->ecc.size, ret;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *p = buf;
        uint8_t *ecc_code = chip->buffers->ecccode;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        unsigned int max_bitflips = 0;

        /* Read the OOB area first */
        chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);

        ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
                                         chip->ecc.total);
        if (ret)
                return ret;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                chip->ecc.hwctl(mtd, NAND_ECC_READ);
                chip->read_buf(mtd, p, eccsize);
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);

                stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
                if (stat == -EBADMSG &&
                    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
                        /* check for empty pages with bitflips */
                        stat = nand_check_erased_ecc_chunk(p, eccsize,
                                                &ecc_code[i], eccbytes,
                                                NULL, 0,
                                                chip->ecc.strength);
                }

                if (stat < 0) {
                        mtd->ecc_stats.failed++;
                } else {
                        mtd->ecc_stats.corrected += stat;
                        max_bitflips = max_t(unsigned int, max_bitflips, stat);
                }
        }
        return max_bitflips;
}

/**
 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @oob_required: caller requires OOB data read to chip->oob_poi
 * @page: page number to read
 *
 * The hw generator calculates the error syndrome automatically. Therefore we
 * need a special oob layout and handling.
 */
static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
                                   uint8_t *buf, int oob_required, int page)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
        uint8_t *p = buf;
        uint8_t *oob = chip->oob_poi;
        unsigned int max_bitflips = 0;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                chip->ecc.hwctl(mtd, NAND_ECC_READ);
                chip->read_buf(mtd, p, eccsize);

                if (chip->ecc.prepad) {
                        chip->read_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
                chip->read_buf(mtd, oob, eccbytes);
                stat = chip->ecc.correct(mtd, p, oob, NULL);

                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->read_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }

                if (stat == -EBADMSG &&
                    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
                        /* check for empty pages with bitflips */
                        stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
                                                           oob - eccpadbytes,
                                                           eccpadbytes,
                                                           NULL, 0,
                                                           chip->ecc.strength);
                }

                if (stat < 0) {
                        mtd->ecc_stats.failed++;
                } else {
                        mtd->ecc_stats.corrected += stat;
                        max_bitflips = max_t(unsigned int, max_bitflips, stat);
                }
        }

        /* Calculate remaining oob bytes */
        i = mtd->oobsize - (oob - chip->oob_poi);
        if (i)
                chip->read_buf(mtd, oob, i);

        return max_bitflips;
}

/**
 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
 * @mtd: mtd info structure
 * @oob: oob destination address
 * @ops: oob ops structure
 * @len: size of oob to transfer
 */
static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
                                  struct mtd_oob_ops *ops, size_t len)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        int ret;

        switch (ops->mode) {

        case MTD_OPS_PLACE_OOB:
        case MTD_OPS_RAW:
                memcpy(oob, chip->oob_poi + ops->ooboffs, len);
                return oob + len;

        case MTD_OPS_AUTO_OOB:
                ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
                                                  ops->ooboffs, len);
                BUG_ON(ret);
                return oob + len;

        default:
                BUG();
        }
        return NULL;
}

/**
 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
 * @mtd: MTD device structure
 * @retry_mode: the retry mode to use
 *
 * Some vendors supply a special command to shift the Vt threshold, to be used
 * when there are too many bitflips in a page (i.e., ECC error). After setting

 * a new threshold, the host should retry reading the page.
 */
static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
{
        struct nand_chip *chip = mtd_to_nand(mtd);

        pr_debug("setting READ RETRY mode %d\n", retry_mode);

        if (retry_mode >= chip->read_retries)
                return -EINVAL;

        if (!chip->setup_read_retry)
                return -EOPNOTSUPP;

        return chip->setup_read_retry(mtd, retry_mode);
}

/**
 * nand_do_read_ops - [INTERN] Read data with ECC
 * @mtd: MTD device structure
 * @from: offset to read from
 * @ops: oob ops structure
 *
 * Internal function. Called with chip held.
 */
static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
                            struct mtd_oob_ops *ops)
{
        int chipnr, page, realpage, col, bytes, aligned, oob_required;
        struct nand_chip *chip = mtd_to_nand(mtd);
        int ret = 0;
        uint32_t readlen = ops->len;
        uint32_t oobreadlen = ops->ooblen;
        uint32_t max_oobsize = mtd_oobavail(mtd, ops);

        uint8_t *bufpoi, *oob, *buf;
        int use_bufpoi;
        unsigned int max_bitflips = 0;
        int retry_mode = 0;
        bool ecc_fail = false;

        chipnr = (int)(from >> chip->chip_shift);
        chip->select_chip(mtd, chipnr);

        realpage = (int)(from >> chip->page_shift);
        page = realpage & chip->pagemask;

        col = (int)(from & (mtd->writesize - 1));

        buf = ops->datbuf;
        oob = ops->oobbuf;
        oob_required = oob ? 1 : 0;

        while (1) {
                unsigned int ecc_failures = mtd->ecc_stats.failed;

                bytes = min(mtd->writesize - col, readlen);
                aligned = (bytes == mtd->writesize);

                if (!aligned)
                        use_bufpoi = 1;
                else if (chip->options & NAND_USE_BOUNCE_BUFFER)
                        use_bufpoi = !virt_addr_valid(buf) ||
                                     !IS_ALIGNED((unsigned long)buf,
                                                 chip->buf_align);
                else
                        use_bufpoi = 0;

                /* Is the current page in the buffer? */
                if (realpage != chip->pagebuf || oob) {
                        bufpoi = use_bufpoi ? chip->buffers->databuf : buf;

                        if (use_bufpoi && aligned)
                                pr_debug("%s: using read bounce buffer for buf@%p\n",
                                                 __func__, buf);

read_retry:
                        if (nand_standard_page_accessors(&chip->ecc))
                                chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);

                        /*
                         * Now read the page into the buffer.  Absent an error,
                         * the read methods return max bitflips per ecc step.
                         */
                        if (unlikely(ops->mode == MTD_OPS_RAW))
                                ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
                                                              oob_required,
                                                              page);
                        else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
                                 !oob)
                                ret = chip->ecc.read_subpage(mtd, chip,
                                                        col, bytes, bufpoi,
                                                        page);
                        else
                                ret = chip->ecc.read_page(mtd, chip, bufpoi,
                                                          oob_required, page);
                        if (ret < 0) {
                                if (use_bufpoi)
                                        /* Invalidate page cache */
                                        chip->pagebuf = -1;
                                break;
                        }

                        /* Transfer not aligned data */
                        if (use_bufpoi) {
                                if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
                                    !(mtd->ecc_stats.failed - ecc_failures) &&
                                    (ops->mode != MTD_OPS_RAW)) {
                                        chip->pagebuf = realpage;
                                        chip->pagebuf_bitflips = ret;
                                } else {
                                        /* Invalidate page cache */
                                        chip->pagebuf = -1;
                                }
                                memcpy(buf, chip->buffers->databuf + col, bytes);
                        }

                        if (unlikely(oob)) {
                                int toread = min(oobreadlen, max_oobsize);

                                if (toread) {
                                        oob = nand_transfer_oob(mtd,
                                                oob, ops, toread);
                                        oobreadlen -= toread;
                                }
                        }

                        if (chip->options & NAND_NEED_READRDY) {
                                /* Apply delay or wait for ready/busy pin */
                                if (!chip->dev_ready)
                                        udelay(chip->chip_delay);
                                else
                                        nand_wait_ready(mtd);
                        }

                        if (mtd->ecc_stats.failed - ecc_failures) {
                                if (retry_mode + 1 < chip->read_retries) {
                                        retry_mode++;
                                        ret = nand_setup_read_retry(mtd,
                                                        retry_mode);
                                        if (ret < 0)
                                                break;

                                        /* Reset failures; retry */
                                        mtd->ecc_stats.failed = ecc_failures;
                                        goto read_retry;
                                } else {
                                        /* No more retry modes; real failure */
                                        ecc_fail = true;
                                }
                        }

                        buf += bytes;
                        max_bitflips = max_t(unsigned int, max_bitflips, ret);
                } else {
                        memcpy(buf, chip->buffers->databuf + col, bytes);
                        buf += bytes;
                        max_bitflips = max_t(unsigned int, max_bitflips,
                                             chip->pagebuf_bitflips);
                }

                readlen -= bytes;

                /* Reset to retry mode 0 */
                if (retry_mode) {
                        ret = nand_setup_read_retry(mtd, 0);
                        if (ret < 0)
                                break;
                        retry_mode = 0;
                }

                if (!readlen)
                        break;

                /* For subsequent reads align to page boundary */
                col = 0;
                /* Increment page address */
                realpage++;

                page = realpage & chip->pagemask;
                /* Check, if we cross a chip boundary */
                if (!page) {
                        chipnr++;
                        chip->select_chip(mtd, -1);
                        chip->select_chip(mtd, chipnr);
                }
        }
        chip->select_chip(mtd, -1);

        ops->retlen = ops->len - (size_t) readlen;
        if (oob)
                ops->oobretlen = ops->ooblen - oobreadlen;

        if (ret < 0)
                return ret;

        if (ecc_fail)
                return -EBADMSG;

        return max_bitflips;
}

/**
 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
 * @mtd: MTD device structure
 * @from: offset to read from
 * @len: number of bytes to read
 * @retlen: pointer to variable to store the number of read bytes
 * @buf: the databuffer to put data
 *
 * Get hold of the chip and call nand_do_read.
 */
static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
                     size_t *retlen, uint8_t *buf)
{
        struct mtd_oob_ops ops;
        int ret;

        nand_get_device(mtd, FL_READING);
        memset(&ops, 0, sizeof(ops));
        ops.len = len;
        ops.datbuf = buf;
        ops.mode = MTD_OPS_PLACE_OOB;
        ret = nand_do_read_ops(mtd, from, &ops);
        *retlen = ops.retlen;
        nand_release_device(mtd);
        return ret;
}

/**
 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to read
 */
int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
{
        chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        return 0;
}
EXPORT_SYMBOL(nand_read_oob_std);

/**
 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
 *                          with syndromes
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to read
 */
int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
                           int page)
{
        int length = mtd->oobsize;
        int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
        int eccsize = chip->ecc.size;
        uint8_t *bufpoi = chip->oob_poi;
        int i, toread, sndrnd = 0, pos;

        chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
        for (i = 0; i < chip->ecc.steps; i++) {
                if (sndrnd) {
                        pos = eccsize + i * (eccsize + chunk);
                        if (mtd->writesize > 512)
                                chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
                        else
                                chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
                } else
                        sndrnd = 1;
                toread = min_t(int, length, chunk);
                chip->read_buf(mtd, bufpoi, toread);
                bufpoi += toread;
                length -= toread;
        }
        if (length > 0)
                chip->read_buf(mtd, bufpoi, length);

        return 0;
}
EXPORT_SYMBOL(nand_read_oob_syndrome);

/**
 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to write
 */
int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
{
        int status = 0;
        const uint8_t *buf = chip->oob_poi;
        int length = mtd->oobsize;

        chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
        chip->write_buf(mtd, buf, length);
        /* Send command to program the OOB data */
        chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);

        status = chip->waitfunc(mtd, chip);

        return status & NAND_STATUS_FAIL ? -EIO : 0;
}
EXPORT_SYMBOL(nand_write_oob_std);

/**
 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
 *                           with syndrome - only for large page flash
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to write
 */
int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
                            int page)
{
        int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
        int eccsize = chip->ecc.size, length = mtd->oobsize;
        int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
        const uint8_t *bufpoi = chip->oob_poi;

        /*
         * data-ecc-data-ecc ... ecc-oob
         * or
         * data-pad-ecc-pad-data-pad .... ecc-pad-oob
         */
        if (!chip->ecc.prepad && !chip->ecc.postpad) {
                pos = steps * (eccsize + chunk);
                steps = 0;
        } else
                pos = eccsize;

        chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
        for (i = 0; i < steps; i++) {
                if (sndcmd) {
                        if (mtd->writesize <= 512) {
                                uint32_t fill = 0xFFFFFFFF;

                                len = eccsize;
                                while (len > 0) {
                                        int num = min_t(int, len, 4);
                                        chip->write_buf(mtd, (uint8_t *)&fill,
                                                        num);
                                        len -= num;
                                }
                        } else {
                                pos = eccsize + i * (eccsize + chunk);
                                chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
                        }
                } else
                        sndcmd = 1;
                len = min_t(int, length, chunk);
                chip->write_buf(mtd, bufpoi, len);
                bufpoi += len;
                length -= len;
        }
        if (length > 0)
                chip->write_buf(mtd, bufpoi, length);

        chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
        status = chip->waitfunc(mtd, chip);

        return status & NAND_STATUS_FAIL ? -EIO : 0;
}
EXPORT_SYMBOL(nand_write_oob_syndrome);

/**
 * nand_do_read_oob - [INTERN] NAND read out-of-band
 * @mtd: MTD device structure
 * @from: offset to read from
 * @ops: oob operations description structure
 *
 * NAND read out-of-band data from the spare area.
 */
static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
                            struct mtd_oob_ops *ops)
{
        int page, realpage, chipnr;
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct mtd_ecc_stats stats;
        int readlen = ops->ooblen;
        int len;
        uint8_t *buf = ops->oobbuf;
        int ret = 0;

        pr_debug("%s: from = 0x%08Lx, len = %i\n",
                        __func__, (unsigned long long)from, readlen);

        stats = mtd->ecc_stats;

        len = mtd_oobavail(mtd, ops);

        if (unlikely(ops->ooboffs >= len)) {
                pr_debug("%s: attempt to start read outside oob\n",
                                __func__);
                return -EINVAL;
        }

        /* Do not allow reads past end of device */
        if (unlikely(from >= mtd->size ||
                     ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
                                        (from >> chip->page_shift)) * len)) {
                pr_debug("%s: attempt to read beyond end of device\n",
                                __func__);
                return -EINVAL;
        }

        chipnr = (int)(from >> chip->chip_shift);
        chip->select_chip(mtd, chipnr);

        /* Shift to get page */
        realpage = (int)(from >> chip->page_shift);
        page = realpage & chip->pagemask;

        while (1) {
                if (ops->mode == MTD_OPS_RAW)
                        ret = chip->ecc.read_oob_raw(mtd, chip, page);
                else
                        ret = chip->ecc.read_oob(mtd, chip, page);

                if (ret < 0)
                        break;

                len = min(len, readlen);
                buf = nand_transfer_oob(mtd, buf, ops, len);

                if (chip->options & NAND_NEED_READRDY) {
                        /* Apply delay or wait for ready/busy pin */
                        if (!chip->dev_ready)
                                udelay(chip->chip_delay);
                        else
                                nand_wait_ready(mtd);
                }

                readlen -= len;
                if (!readlen)
                        break;

                /* Increment page address */
                realpage++;

                page = realpage & chip->pagemask;
                /* Check, if we cross a chip boundary */
                if (!page) {
                        chipnr++;
                        chip->select_chip(mtd, -1);
                        chip->select_chip(mtd, chipnr);
                }
        }
        chip->select_chip(mtd, -1);

        ops->oobretlen = ops->ooblen - readlen;

        if (ret < 0)
                return ret;

        if (mtd->ecc_stats.failed - stats.failed)
                return -EBADMSG;

        return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
}

/**
 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
 * @mtd: MTD device structure
 * @from: offset to read from
 * @ops: oob operation description structure
 *
 * NAND read data and/or out-of-band data.
 */
static int nand_read_oob(struct mtd_info *mtd, loff_t from,
                         struct mtd_oob_ops *ops)
{
        int ret;

        ops->retlen = 0;

        /* Do not allow reads past end of device */
        if (ops->datbuf && (from + ops->len) > mtd->size) {
                pr_debug("%s: attempt to read beyond end of device\n",
                                __func__);
                return -EINVAL;
        }

        if (ops->mode != MTD_OPS_PLACE_OOB &&
            ops->mode != MTD_OPS_AUTO_OOB &&
            ops->mode != MTD_OPS_RAW)
                return -ENOTSUPP;

        nand_get_device(mtd, FL_READING);

        if (!ops->datbuf)
                ret = nand_do_read_oob(mtd, from, ops);
        else
                ret = nand_do_read_ops(mtd, from, ops);

        nand_release_device(mtd);
        return ret;
}


/**
 * nand_write_page_raw - [INTERN] raw page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 * @oob_required: must write chip->oob_poi to OOB
 * @page: page number to write
 *
 * Not for syndrome calculating ECC controllers, which use a special oob layout.
 */
int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
                        const uint8_t *buf, int oob_required, int page)
{
        chip->write_buf(mtd, buf, mtd->writesize);
        if (oob_required)
                chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);

        return 0;
}
EXPORT_SYMBOL(nand_write_page_raw);

/**
 * nand_write_page_raw_syndrome - [INTERN] raw page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 * @oob_required: must write chip->oob_poi to OOB
 * @page: page number to write
 *
 * We need a special oob layout and handling even when ECC isn't checked.
 */
static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
                                        struct nand_chip *chip,
                                        const uint8_t *buf, int oob_required,
                                        int page)
{
        int eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        uint8_t *oob = chip->oob_poi;
        int steps, size;

        for (steps = chip->ecc.steps; steps > 0; steps--) {
                chip->write_buf(mtd, buf, eccsize);
                buf += eccsize;

                if (chip->ecc.prepad) {
                        chip->write_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->write_buf(mtd, oob, eccbytes);
                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->write_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }
        }

        size = mtd->oobsize - (oob - chip->oob_poi);
        if (size)
                chip->write_buf(mtd, oob, size);

        return 0;
}
/**
 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 * @oob_required: must write chip->oob_poi to OOB
 * @page: page number to write
 */
static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
                                 const uint8_t *buf, int oob_required,
                                 int page)
{
        int i, eccsize = chip->ecc.size, ret;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        const uint8_t *p = buf;

        /* Software ECC calculation */
        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);

        ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
                                         chip->ecc.total);
        if (ret)
                return ret;

        return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
}

/**
 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 * @oob_required: must write chip->oob_poi to OOB
 * @page: page number to write
 */
static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
                                  const uint8_t *buf, int oob_required,
                                  int page)
{
        int i, eccsize = chip->ecc.size, ret;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        const uint8_t *p = buf;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
                chip->write_buf(mtd, p, eccsize);
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);
        }

        ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
                                         chip->ecc.total);
        if (ret)
                return ret;

        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);

        return 0;
}


/**
 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
 * @mtd:        mtd info structure
 * @chip:       nand chip info structure
 * @offset:     column address of subpage within the page
 * @data_len:   data length
 * @buf:        data buffer
 * @oob_required: must write chip->oob_poi to OOB
 * @page: page number to write
 */
static int nand_write_subpage_hwecc(struct mtd_info *mtd,
                                struct nand_chip *chip, uint32_t offset,
                                uint32_t data_len, const uint8_t *buf,
                                int oob_required, int page)
{
        uint8_t *oob_buf  = chip->oob_poi;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        int ecc_size      = chip->ecc.size;
        int ecc_bytes     = chip->ecc.bytes;
        int ecc_steps     = chip->ecc.steps;
        uint32_t start_step = offset / ecc_size;
        uint32_t end_step   = (offset + data_len - 1) / ecc_size;
        int oob_bytes       = mtd->oobsize / ecc_steps;
        int step, ret;

        for (step = 0; step < ecc_steps; step++) {
                /* configure controller for WRITE access */
                chip->ecc.hwctl(mtd, NAND_ECC_WRITE);

                /* write data (untouched subpages already masked by 0xFF) */
                chip->write_buf(mtd, buf, ecc_size);

                /* mask ECC of un-touched subpages by padding 0xFF */
                if ((step < start_step) || (step > end_step))
                        memset(ecc_calc, 0xff, ecc_bytes);
                else
                        chip->ecc.calculate(mtd, buf, ecc_calc);

                /* mask OOB of un-touched subpages by padding 0xFF */
                /* if oob_required, preserve OOB metadata of written subpage */
                if (!oob_required || (step < start_step) || (step > end_step))
                        memset(oob_buf, 0xff, oob_bytes);

                buf += ecc_size;
                ecc_calc += ecc_bytes;
                oob_buf  += oob_bytes;
        }

        /* copy calculated ECC for whole page to chip->buffer->oob */
        /* this include masked-value(0xFF) for unwritten subpages */
        ecc_calc = chip->buffers->ecccalc;
        ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
                                         chip->ecc.total);
        if (ret)
                return ret;

        /* write OOB buffer to NAND device */
        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);

        return 0;
}


/**
 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 * @oob_required: must write chip->oob_poi to OOB
 * @page: page number to write
 *
 * The hw generator calculates the error syndrome automatically. Therefore we
 * need a special oob layout and handling.
 */
static int nand_write_page_syndrome(struct mtd_info *mtd,
                                    struct nand_chip *chip,
                                    const uint8_t *buf, int oob_required,
                                    int page)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        const uint8_t *p = buf;
        uint8_t *oob = chip->oob_poi;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {

                chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
                chip->write_buf(mtd, p, eccsize);

                if (chip->ecc.prepad) {
                        chip->write_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->ecc.calculate(mtd, p, oob);
                chip->write_buf(mtd, oob, eccbytes);
                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->write_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }
        }

        /* Calculate remaining oob bytes */
        i = mtd->oobsize - (oob - chip->oob_poi);
        if (i)
                chip->write_buf(mtd, oob, i);

        return 0;
}

/**
 * nand_write_page - write one page
 * @mtd: MTD device structure
 * @chip: NAND chip descriptor
 * @offset: address offset within the page
 * @data_len: length of actual data to be written
 * @buf: the data to write
 * @oob_required: must write chip->oob_poi to OOB
 * @page: page number to write
 * @raw: use _raw version of write_page
 */
static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
                uint32_t offset, int data_len, const uint8_t *buf,
                int oob_required, int page, int raw)
{
        int status, subpage;

        if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
                chip->ecc.write_subpage)
                subpage = offset || (data_len < mtd->writesize);
        else
                subpage = 0;

        if (nand_standard_page_accessors(&chip->ecc))
                chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);

        if (unlikely(raw))
                status = chip->ecc.write_page_raw(mtd, chip, buf,
                                                  oob_required, page);
        else if (subpage)
                status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
                                                 buf, oob_required, page);
        else
                status = chip->ecc.write_page(mtd, chip, buf, oob_required,
                                              page);

        if (status < 0)
                return status;

        if (nand_standard_page_accessors(&chip->ecc)) {
                chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);

                status = chip->waitfunc(mtd, chip);
                if (status & NAND_STATUS_FAIL)
                        return -EIO;
        }

        return 0;
}

/**
 * nand_fill_oob - [INTERN] Transfer client buffer to oob
 * @mtd: MTD device structure
 * @oob: oob data buffer
 * @len: oob data write length
 * @ops: oob ops structure
 */
static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
                              struct mtd_oob_ops *ops)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        int ret;

        /*
         * Initialise to all 0xFF, to avoid the possibility of left over OOB
         * data from a previous OOB read.
         */
        memset(chip->oob_poi, 0xff, mtd->oobsize);

        switch (ops->mode) {

        case MTD_OPS_PLACE_OOB:
        case MTD_OPS_RAW:
                memcpy(chip->oob_poi + ops->ooboffs, oob, len);
                return oob + len;

        case MTD_OPS_AUTO_OOB:
                ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
                                                  ops->ooboffs, len);
                BUG_ON(ret);
                return oob + len;

        default:
                BUG();
        }
        return NULL;
}

#define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)

/**
 * nand_do_write_ops - [INTERN] NAND write with ECC
 * @mtd: MTD device structure
 * @to: offset to write to
 * @ops: oob operations description structure
 *
 * NAND write with ECC.
 */
static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
                             struct mtd_oob_ops *ops)
{
        int chipnr, realpage, page, blockmask, column;
        struct nand_chip *chip = mtd_to_nand(mtd);
        uint32_t writelen = ops->len;

        uint32_t oobwritelen = ops->ooblen;
        uint32_t oobmaxlen = mtd_oobavail(mtd, ops);

        uint8_t *oob = ops->oobbuf;
        uint8_t *buf = ops->datbuf;
        int ret;
        int oob_required = oob ? 1 : 0;

        ops->retlen = 0;
        if (!writelen)
                return 0;

        /* Reject writes, which are not page aligned */
        if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
                pr_notice("%s: attempt to write non page aligned data\n",
                           __func__);
                return -EINVAL;
        }

        column = to & (mtd->writesize - 1);

        chipnr = (int)(to >> chip->chip_shift);
        chip->select_chip(mtd, chipnr);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd)) {
                ret = -EIO;
                goto err_out;
        }

        realpage = (int)(to >> chip->page_shift);
        page = realpage & chip->pagemask;
        blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;

        /* Invalidate the page cache, when we write to the cached page */
        if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
            ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
                chip->pagebuf = -1;

        /* Don't allow multipage oob writes with offset */
        if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
                ret = -EINVAL;
                goto err_out;
        }

        while (1) {
                int bytes = mtd->writesize;
                uint8_t *wbuf = buf;
                int use_bufpoi;
                int part_pagewr = (column || writelen < mtd->writesize);

                if (part_pagewr)
                        use_bufpoi = 1;
                else if (chip->options & NAND_USE_BOUNCE_BUFFER)
                        use_bufpoi = !virt_addr_valid(buf) ||
                                     !IS_ALIGNED((unsigned long)buf,
                                                 chip->buf_align);
                else
                        use_bufpoi = 0;

                /* Partial page write?, or need to use bounce buffer */
                if (use_bufpoi) {
                        pr_debug("%s: using write bounce buffer for buf@%p\n",
                                         __func__, buf);
                        if (part_pagewr)
                                bytes = min_t(int, bytes - column, writelen);
                        chip->pagebuf = -1;
                        memset(chip->buffers->databuf, 0xff, mtd->writesize);
                        memcpy(&chip->buffers->databuf[column], buf, bytes);
                        wbuf = chip->buffers->databuf;
                }

                if (unlikely(oob)) {
                        size_t len = min(oobwritelen, oobmaxlen);
                        oob = nand_fill_oob(mtd, oob, len, ops);
                        oobwritelen -= len;
                } else {
                        /* We still need to erase leftover OOB data */
                        memset(chip->oob_poi, 0xff, mtd->oobsize);
                }

                ret = nand_write_page(mtd, chip, column, bytes, wbuf,
                                      oob_required, page,
                                      (ops->mode == MTD_OPS_RAW));
                if (ret)
                        break;

                writelen -= bytes;
                if (!writelen)
                        break;

                column = 0;
                buf += bytes;
                realpage++;

                page = realpage & chip->pagemask;
                /* Check, if we cross a chip boundary */
                if (!page) {
                        chipnr++;
                        chip->select_chip(mtd, -1);
                        chip->select_chip(mtd, chipnr);
                }
        }

        ops->retlen = ops->len - writelen;
        if (unlikely(oob))
                ops->oobretlen = ops->ooblen;

err_out:
        chip->select_chip(mtd, -1);
        return ret;
}

/**
 * panic_nand_write - [MTD Interface] NAND write with ECC
 * @mtd: MTD device structure
 * @to: offset to write to
 * @len: number of bytes to write
 * @retlen: pointer to variable to store the number of written bytes
 * @buf: the data to write
 *
 * NAND write with ECC. Used when performing writes in interrupt context, this
 * may for example be called by mtdoops when writing an oops while in panic.
 */
static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
                            size_t *retlen, const uint8_t *buf)
{
        struct nand_chip *chip = mtd_to_nand(mtd);
        struct mtd_oob_ops ops;
        int ret;

        /* Wait for the device to get ready */
        panic_nand_wait(mtd, chip, 400);

        /* Grab the device */
        panic_nand_get_device(chip, mtd, FL_WRITING);

        memset(&ops, 0, sizeof(ops));
        ops.len = len;
        ops.datbuf = (uint8_t *)buf;
        ops.mode = MTD_OPS_PLACE_OOB;

        ret = nand_do_write_ops(mtd, to, &ops);

        *retlen = ops.retlen;
        return ret;
}

/**
 * nand_write - [MTD Interface] NAND write with ECC
 * @mtd: MTD device structure
 * @to: offset to write to
 * @len: number of bytes to write