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35#ifndef __T4_REGS_H
36#define __T4_REGS_H
37
38#define MYPF_BASE 0x1b000
39#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
40
41#define PF0_BASE 0x1e000
42#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
43
44#define PF_STRIDE 0x400
45#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
47
48#define MYPORT_BASE 0x1c000
49#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
50
51#define PORT0_BASE 0x20000
52#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
53
54#define PORT_STRIDE 0x2000
55#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
57
58#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
60
61#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
65
66#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
67
68#define SGE_PF_KDOORBELL_A 0x0
69
70#define QID_S 15
71#define QID_V(x) ((x) << QID_S)
72
73#define DBPRIO_S 14
74#define DBPRIO_V(x) ((x) << DBPRIO_S)
75#define DBPRIO_F DBPRIO_V(1U)
76
77#define PIDX_S 0
78#define PIDX_V(x) ((x) << PIDX_S)
79
80#define SGE_VF_KDOORBELL_A 0x0
81
82#define DBTYPE_S 13
83#define DBTYPE_V(x) ((x) << DBTYPE_S)
84#define DBTYPE_F DBTYPE_V(1U)
85
86#define PIDX_T5_S 0
87#define PIDX_T5_M 0x1fffU
88#define PIDX_T5_V(x) ((x) << PIDX_T5_S)
89#define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
90
91#define SGE_PF_GTS_A 0x4
92
93#define INGRESSQID_S 16
94#define INGRESSQID_V(x) ((x) << INGRESSQID_S)
95
96#define TIMERREG_S 13
97#define TIMERREG_V(x) ((x) << TIMERREG_S)
98
99#define SEINTARM_S 12
100#define SEINTARM_V(x) ((x) << SEINTARM_S)
101
102#define CIDXINC_S 0
103#define CIDXINC_M 0xfffU
104#define CIDXINC_V(x) ((x) << CIDXINC_S)
105
106#define SGE_CONTROL_A 0x1008
107#define SGE_CONTROL2_A 0x1124
108
109#define RXPKTCPLMODE_S 18
110#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
111#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)
112
113#define EGRSTATUSPAGESIZE_S 17
114#define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
115#define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U)
116
117#define PKTSHIFT_S 10
118#define PKTSHIFT_M 0x7U
119#define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)
120#define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)
121
122#define INGPCIEBOUNDARY_S 7
123#define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)
124
125#define INGPADBOUNDARY_S 4
126#define INGPADBOUNDARY_M 0x7U
127#define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)
128#define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)
129
130#define EGRPCIEBOUNDARY_S 1
131#define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)
132
133#define INGPACKBOUNDARY_S 16
134#define INGPACKBOUNDARY_M 0x7U
135#define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S)
136#define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \
137 & INGPACKBOUNDARY_M)
138
139#define VFIFO_ENABLE_S 10
140#define VFIFO_ENABLE_V(x) ((x) << VFIFO_ENABLE_S)
141#define VFIFO_ENABLE_F VFIFO_ENABLE_V(1U)
142
143#define SGE_DBVFIFO_BADDR_A 0x1138
144
145#define DBVFIFO_SIZE_S 6
146#define DBVFIFO_SIZE_M 0xfffU
147#define DBVFIFO_SIZE_G(x) (((x) >> DBVFIFO_SIZE_S) & DBVFIFO_SIZE_M)
148
149#define T6_DBVFIFO_SIZE_S 0
150#define T6_DBVFIFO_SIZE_M 0x1fffU
151#define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M)
152
153#define GLOBALENABLE_S 0
154#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
155#define GLOBALENABLE_F GLOBALENABLE_V(1U)
156
157#define SGE_HOST_PAGE_SIZE_A 0x100c
158
159#define HOSTPAGESIZEPF7_S 28
160#define HOSTPAGESIZEPF7_M 0xfU
161#define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)
162#define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)
163
164#define HOSTPAGESIZEPF6_S 24
165#define HOSTPAGESIZEPF6_M 0xfU
166#define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)
167#define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)
168
169#define HOSTPAGESIZEPF5_S 20
170#define HOSTPAGESIZEPF5_M 0xfU
171#define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)
172#define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)
173
174#define HOSTPAGESIZEPF4_S 16
175#define HOSTPAGESIZEPF4_M 0xfU
176#define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)
177#define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)
178
179#define HOSTPAGESIZEPF3_S 12
180#define HOSTPAGESIZEPF3_M 0xfU
181#define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)
182#define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)
183
184#define HOSTPAGESIZEPF2_S 8
185#define HOSTPAGESIZEPF2_M 0xfU
186#define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)
187#define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)
188
189#define HOSTPAGESIZEPF1_S 4
190#define HOSTPAGESIZEPF1_M 0xfU
191#define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)
192#define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)
193
194#define HOSTPAGESIZEPF0_S 0
195#define HOSTPAGESIZEPF0_M 0xfU
196#define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)
197#define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)
198
199#define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
200#define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
201
202#define QUEUESPERPAGEPF1_S 4
203
204#define QUEUESPERPAGEPF0_S 0
205#define QUEUESPERPAGEPF0_M 0xfU
206#define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
207#define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
208
209#define SGE_INT_CAUSE1_A 0x1024
210#define SGE_INT_CAUSE2_A 0x1030
211#define SGE_INT_CAUSE3_A 0x103c
212
213#define ERR_FLM_DBP_S 31
214#define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
215#define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U)
216
217#define ERR_FLM_IDMA1_S 30
218#define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)
219#define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U)
220
221#define ERR_FLM_IDMA0_S 29
222#define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)
223#define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U)
224
225#define ERR_FLM_HINT_S 28
226#define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)
227#define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U)
228
229#define ERR_PCIE_ERROR3_S 27
230#define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)
231#define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U)
232
233#define ERR_PCIE_ERROR2_S 26
234#define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)
235#define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U)
236
237#define ERR_PCIE_ERROR1_S 25
238#define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)
239#define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U)
240
241#define ERR_PCIE_ERROR0_S 24
242#define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
243#define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U)
244
245#define ERR_CPL_EXCEED_IQE_SIZE_S 22
246#define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
247#define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U)
248
249#define ERR_INVALID_CIDX_INC_S 21
250#define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
251#define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U)
252
253#define ERR_CPL_OPCODE_0_S 19
254#define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
255#define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U)
256
257#define ERR_DROPPED_DB_S 18
258#define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)
259#define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U)
260
261#define ERR_DATA_CPL_ON_HIGH_QID1_S 17
262#define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)
263#define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U)
264
265#define ERR_DATA_CPL_ON_HIGH_QID0_S 16
266#define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)
267#define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U)
268
269#define ERR_BAD_DB_PIDX3_S 15
270#define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)
271#define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U)
272
273#define ERR_BAD_DB_PIDX2_S 14
274#define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)
275#define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U)
276
277#define ERR_BAD_DB_PIDX1_S 13
278#define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)
279#define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U)
280
281#define ERR_BAD_DB_PIDX0_S 12
282#define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
283#define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U)
284
285#define ERR_ING_CTXT_PRIO_S 10
286#define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
287#define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U)
288
289#define ERR_EGR_CTXT_PRIO_S 9
290#define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)
291#define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U)
292
293#define DBFIFO_HP_INT_S 8
294#define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)
295#define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U)
296
297#define DBFIFO_LP_INT_S 7
298#define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
299#define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U)
300
301#define INGRESS_SIZE_ERR_S 5
302#define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
303#define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U)
304
305#define EGRESS_SIZE_ERR_S 4
306#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
307#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)
308
309#define SGE_INT_ENABLE3_A 0x1040
310#define SGE_FL_BUFFER_SIZE0_A 0x1044
311#define SGE_FL_BUFFER_SIZE1_A 0x1048
312#define SGE_FL_BUFFER_SIZE2_A 0x104c
313#define SGE_FL_BUFFER_SIZE3_A 0x1050
314#define SGE_FL_BUFFER_SIZE4_A 0x1054
315#define SGE_FL_BUFFER_SIZE5_A 0x1058
316#define SGE_FL_BUFFER_SIZE6_A 0x105c
317#define SGE_FL_BUFFER_SIZE7_A 0x1060
318#define SGE_FL_BUFFER_SIZE8_A 0x1064
319
320#define SGE_IMSG_CTXT_BADDR_A 0x1088
321#define SGE_FLM_CACHE_BADDR_A 0x108c
322#define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
323
324#define THRESHOLD_0_S 24
325#define THRESHOLD_0_M 0x3fU
326#define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)
327#define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)
328
329#define THRESHOLD_1_S 16
330#define THRESHOLD_1_M 0x3fU
331#define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)
332#define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)
333
334#define THRESHOLD_2_S 8
335#define THRESHOLD_2_M 0x3fU
336#define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)
337#define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)
338
339#define THRESHOLD_3_S 0
340#define THRESHOLD_3_M 0x3fU
341#define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)
342#define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)
343
344#define SGE_CONM_CTRL_A 0x1094
345
346#define EGRTHRESHOLD_S 8
347#define EGRTHRESHOLD_M 0x3fU
348#define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
349#define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
350
351#define EGRTHRESHOLDPACKING_S 14
352#define EGRTHRESHOLDPACKING_M 0x3fU
353#define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
354#define EGRTHRESHOLDPACKING_G(x) \
355 (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
356
357#define T6_EGRTHRESHOLDPACKING_S 16
358#define T6_EGRTHRESHOLDPACKING_M 0xffU
359#define T6_EGRTHRESHOLDPACKING_G(x) \
360 (((x) >> T6_EGRTHRESHOLDPACKING_S) & T6_EGRTHRESHOLDPACKING_M)
361
362#define SGE_TIMESTAMP_LO_A 0x1098
363#define SGE_TIMESTAMP_HI_A 0x109c
364
365#define TSOP_S 28
366#define TSOP_M 0x3U
367#define TSOP_V(x) ((x) << TSOP_S)
368#define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
369
370#define TSVAL_S 0
371#define TSVAL_M 0xfffffffU
372#define TSVAL_V(x) ((x) << TSVAL_S)
373#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
374
375#define SGE_DBFIFO_STATUS_A 0x10a4
376#define SGE_DBVFIFO_SIZE_A 0x113c
377
378#define HP_INT_THRESH_S 28
379#define HP_INT_THRESH_M 0xfU
380#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
381
382#define LP_INT_THRESH_S 12
383#define LP_INT_THRESH_M 0xfU
384#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
385
386#define SGE_DOORBELL_CONTROL_A 0x10a8
387
388#define NOCOALESCE_S 26
389#define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
390#define NOCOALESCE_F NOCOALESCE_V(1U)
391
392#define ENABLE_DROP_S 13
393#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
394#define ENABLE_DROP_F ENABLE_DROP_V(1U)
395
396#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
397
398#define TIMERVALUE0_S 16
399#define TIMERVALUE0_M 0xffffU
400#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
401#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
402
403#define TIMERVALUE1_S 0
404#define TIMERVALUE1_M 0xffffU
405#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
406#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
407
408#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
409
410#define TIMERVALUE2_S 16
411#define TIMERVALUE2_M 0xffffU
412#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
413#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
414
415#define TIMERVALUE3_S 0
416#define TIMERVALUE3_M 0xffffU
417#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
418#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
419
420#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
421
422#define TIMERVALUE4_S 16
423#define TIMERVALUE4_M 0xffffU
424#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
425#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
426
427#define TIMERVALUE5_S 0
428#define TIMERVALUE5_M 0xffffU
429#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
430#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
431
432#define SGE_DEBUG_INDEX_A 0x10cc
433#define SGE_DEBUG_DATA_HIGH_A 0x10d0
434#define SGE_DEBUG_DATA_LOW_A 0x10d4
435
436#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
437#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
438#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
439
440#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
441#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
442
443#define SGE_ERROR_STATS_A 0x1100
444
445#define UNCAPTURED_ERROR_S 18
446#define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S)
447#define UNCAPTURED_ERROR_F UNCAPTURED_ERROR_V(1U)
448
449#define ERROR_QID_VALID_S 17
450#define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S)
451#define ERROR_QID_VALID_F ERROR_QID_VALID_V(1U)
452
453#define ERROR_QID_S 0
454#define ERROR_QID_M 0x1ffffU
455#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
456
457#define HP_INT_THRESH_S 28
458#define HP_INT_THRESH_M 0xfU
459#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
460
461#define HP_COUNT_S 16
462#define HP_COUNT_M 0x7ffU
463#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
464
465#define LP_INT_THRESH_S 12
466#define LP_INT_THRESH_M 0xfU
467#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
468
469#define LP_COUNT_S 0
470#define LP_COUNT_M 0x7ffU
471#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
472
473#define LP_INT_THRESH_T5_S 18
474#define LP_INT_THRESH_T5_M 0xfffU
475#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
476
477#define LP_COUNT_T5_S 0
478#define LP_COUNT_T5_M 0x3ffffU
479#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
480
481#define SGE_DOORBELL_CONTROL_A 0x10a8
482
483#define SGE_STAT_TOTAL_A 0x10e4
484#define SGE_STAT_MATCH_A 0x10e8
485#define SGE_STAT_CFG_A 0x10ec
486
487#define STATMODE_S 2
488#define STATMODE_V(x) ((x) << STATMODE_S)
489
490#define STATSOURCE_T5_S 9
491#define STATSOURCE_T5_M 0xfU
492#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
493#define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M)
494
495#define T6_STATMODE_S 0
496#define T6_STATMODE_V(x) ((x) << T6_STATMODE_S)
497
498#define SGE_DBFIFO_STATUS2_A 0x1118
499
500#define HP_INT_THRESH_T5_S 10
501#define HP_INT_THRESH_T5_M 0xfU
502#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
503
504#define HP_COUNT_T5_S 0
505#define HP_COUNT_T5_M 0x3ffU
506#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
507
508#define ENABLE_DROP_S 13
509#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
510#define ENABLE_DROP_F ENABLE_DROP_V(1U)
511
512#define DROPPED_DB_S 0
513#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
514#define DROPPED_DB_F DROPPED_DB_V(1U)
515
516#define SGE_CTXT_CMD_A 0x11fc
517#define SGE_DBQ_CTXT_BADDR_A 0x1084
518
519
520#define PCIE_PF_CFG_A 0x40
521
522#define AIVEC_S 4
523#define AIVEC_M 0x3ffU
524#define AIVEC_V(x) ((x) << AIVEC_S)
525
526#define PCIE_PF_CLI_A 0x44
527#define PCIE_INT_CAUSE_A 0x3004
528
529#define UNXSPLCPLERR_S 29
530#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
531#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
532
533#define PCIEPINT_S 28
534#define PCIEPINT_V(x) ((x) << PCIEPINT_S)
535#define PCIEPINT_F PCIEPINT_V(1U)
536
537#define PCIESINT_S 27
538#define PCIESINT_V(x) ((x) << PCIESINT_S)
539#define PCIESINT_F PCIESINT_V(1U)
540
541#define RPLPERR_S 26
542#define RPLPERR_V(x) ((x) << RPLPERR_S)
543#define RPLPERR_F RPLPERR_V(1U)
544
545#define RXWRPERR_S 25
546#define RXWRPERR_V(x) ((x) << RXWRPERR_S)
547#define RXWRPERR_F RXWRPERR_V(1U)
548
549#define RXCPLPERR_S 24
550#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
551#define RXCPLPERR_F RXCPLPERR_V(1U)
552
553#define PIOTAGPERR_S 23
554#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
555#define PIOTAGPERR_F PIOTAGPERR_V(1U)
556
557#define MATAGPERR_S 22
558#define MATAGPERR_V(x) ((x) << MATAGPERR_S)
559#define MATAGPERR_F MATAGPERR_V(1U)
560
561#define INTXCLRPERR_S 21
562#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
563#define INTXCLRPERR_F INTXCLRPERR_V(1U)
564
565#define FIDPERR_S 20
566#define FIDPERR_V(x) ((x) << FIDPERR_S)
567#define FIDPERR_F FIDPERR_V(1U)
568
569#define CFGSNPPERR_S 19
570#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
571#define CFGSNPPERR_F CFGSNPPERR_V(1U)
572
573#define HRSPPERR_S 18
574#define HRSPPERR_V(x) ((x) << HRSPPERR_S)
575#define HRSPPERR_F HRSPPERR_V(1U)
576
577#define HREQPERR_S 17
578#define HREQPERR_V(x) ((x) << HREQPERR_S)
579#define HREQPERR_F HREQPERR_V(1U)
580
581#define HCNTPERR_S 16
582#define HCNTPERR_V(x) ((x) << HCNTPERR_S)
583#define HCNTPERR_F HCNTPERR_V(1U)
584
585#define DRSPPERR_S 15
586#define DRSPPERR_V(x) ((x) << DRSPPERR_S)
587#define DRSPPERR_F DRSPPERR_V(1U)
588
589#define DREQPERR_S 14
590#define DREQPERR_V(x) ((x) << DREQPERR_S)
591#define DREQPERR_F DREQPERR_V(1U)
592
593#define DCNTPERR_S 13
594#define DCNTPERR_V(x) ((x) << DCNTPERR_S)
595#define DCNTPERR_F DCNTPERR_V(1U)
596
597#define CRSPPERR_S 12
598#define CRSPPERR_V(x) ((x) << CRSPPERR_S)
599#define CRSPPERR_F CRSPPERR_V(1U)
600
601#define CREQPERR_S 11
602#define CREQPERR_V(x) ((x) << CREQPERR_S)
603#define CREQPERR_F CREQPERR_V(1U)
604
605#define CCNTPERR_S 10
606#define CCNTPERR_V(x) ((x) << CCNTPERR_S)
607#define CCNTPERR_F CCNTPERR_V(1U)
608
609#define TARTAGPERR_S 9
610#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
611#define TARTAGPERR_F TARTAGPERR_V(1U)
612
613#define PIOREQPERR_S 8
614#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
615#define PIOREQPERR_F PIOREQPERR_V(1U)
616
617#define PIOCPLPERR_S 7
618#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
619#define PIOCPLPERR_F PIOCPLPERR_V(1U)
620
621#define MSIXDIPERR_S 6
622#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
623#define MSIXDIPERR_F MSIXDIPERR_V(1U)
624
625#define MSIXDATAPERR_S 5
626#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
627#define MSIXDATAPERR_F MSIXDATAPERR_V(1U)
628
629#define MSIXADDRHPERR_S 4
630#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
631#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)
632
633#define MSIXADDRLPERR_S 3
634#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
635#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)
636
637#define MSIDATAPERR_S 2
638#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
639#define MSIDATAPERR_F MSIDATAPERR_V(1U)
640
641#define MSIADDRHPERR_S 1
642#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
643#define MSIADDRHPERR_F MSIADDRHPERR_V(1U)
644
645#define MSIADDRLPERR_S 0
646#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
647#define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
648
649#define READRSPERR_S 29
650#define READRSPERR_V(x) ((x) << READRSPERR_S)
651#define READRSPERR_F READRSPERR_V(1U)
652
653#define TRGT1GRPPERR_S 28
654#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
655#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)
656
657#define IPSOTPERR_S 27
658#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
659#define IPSOTPERR_F IPSOTPERR_V(1U)
660
661#define IPRETRYPERR_S 26
662#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
663#define IPRETRYPERR_F IPRETRYPERR_V(1U)
664
665#define IPRXDATAGRPPERR_S 25
666#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
667#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)
668
669#define IPRXHDRGRPPERR_S 24
670#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
671#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
672
673#define MAGRPPERR_S 22
674#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
675#define MAGRPPERR_F MAGRPPERR_V(1U)
676
677#define VFIDPERR_S 21
678#define VFIDPERR_V(x) ((x) << VFIDPERR_S)
679#define VFIDPERR_F VFIDPERR_V(1U)
680
681#define HREQWRPERR_S 16
682#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
683#define HREQWRPERR_F HREQWRPERR_V(1U)
684
685#define DREQWRPERR_S 13
686#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
687#define DREQWRPERR_F DREQWRPERR_V(1U)
688
689#define CREQRDPERR_S 11
690#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
691#define CREQRDPERR_F CREQRDPERR_V(1U)
692
693#define MSTTAGQPERR_S 10
694#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
695#define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
696
697#define PIOREQGRPPERR_S 8
698#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
699#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
700
701#define PIOCPLGRPPERR_S 7
702#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
703#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)
704
705#define MSIXSTIPERR_S 2
706#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
707#define MSIXSTIPERR_F MSIXSTIPERR_V(1U)
708
709#define MSTTIMEOUTPERR_S 1
710#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
711#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)
712
713#define MSTGRPPERR_S 0
714#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
715#define MSTGRPPERR_F MSTGRPPERR_V(1U)
716
717#define PCIE_NONFAT_ERR_A 0x3010
718#define PCIE_CFG_SPACE_REQ_A 0x3060
719#define PCIE_CFG_SPACE_DATA_A 0x3064
720#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
721
722#define PCIEOFST_S 10
723#define PCIEOFST_M 0x3fffffU
724#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
725
726#define BIR_S 8
727#define BIR_M 0x3U
728#define BIR_V(x) ((x) << BIR_S)
729#define BIR_G(x) (((x) >> BIR_S) & BIR_M)
730
731#define WINDOW_S 0
732#define WINDOW_M 0xffU
733#define WINDOW_V(x) ((x) << WINDOW_S)
734#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
735
736#define PCIE_MEM_ACCESS_OFFSET_A 0x306c
737
738#define ENABLE_S 30
739#define ENABLE_V(x) ((x) << ENABLE_S)
740#define ENABLE_F ENABLE_V(1U)
741
742#define LOCALCFG_S 28
743#define LOCALCFG_V(x) ((x) << LOCALCFG_S)
744#define LOCALCFG_F LOCALCFG_V(1U)
745
746#define FUNCTION_S 12
747#define FUNCTION_V(x) ((x) << FUNCTION_S)
748
749#define REGISTER_S 0
750#define REGISTER_V(x) ((x) << REGISTER_S)
751
752#define T6_ENABLE_S 31
753#define T6_ENABLE_V(x) ((x) << T6_ENABLE_S)
754#define T6_ENABLE_F T6_ENABLE_V(1U)
755
756#define PFNUM_S 0
757#define PFNUM_V(x) ((x) << PFNUM_S)
758
759#define PCIE_FW_A 0x30b8
760#define PCIE_FW_PF_A 0x30bc
761
762#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
763
764#define RNPP_S 31
765#define RNPP_V(x) ((x) << RNPP_S)
766#define RNPP_F RNPP_V(1U)
767
768#define RPCP_S 29
769#define RPCP_V(x) ((x) << RPCP_S)
770#define RPCP_F RPCP_V(1U)
771
772#define RCIP_S 27
773#define RCIP_V(x) ((x) << RCIP_S)
774#define RCIP_F RCIP_V(1U)
775
776#define RCCP_S 26
777#define RCCP_V(x) ((x) << RCCP_S)
778#define RCCP_F RCCP_V(1U)
779
780#define RFTP_S 23
781#define RFTP_V(x) ((x) << RFTP_S)
782#define RFTP_F RFTP_V(1U)
783
784#define PTRP_S 20
785#define PTRP_V(x) ((x) << PTRP_S)
786#define PTRP_F PTRP_V(1U)
787
788#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
789
790#define TPCP_S 30
791#define TPCP_V(x) ((x) << TPCP_S)
792#define TPCP_F TPCP_V(1U)
793
794#define TNPP_S 29
795#define TNPP_V(x) ((x) << TNPP_S)
796#define TNPP_F TNPP_V(1U)
797
798#define TFTP_S 28
799#define TFTP_V(x) ((x) << TFTP_S)
800#define TFTP_F TFTP_V(1U)
801
802#define TCAP_S 27
803#define TCAP_V(x) ((x) << TCAP_S)
804#define TCAP_F TCAP_V(1U)
805
806#define TCIP_S 26
807#define TCIP_V(x) ((x) << TCIP_S)
808#define TCIP_F TCIP_V(1U)
809
810#define RCAP_S 25
811#define RCAP_V(x) ((x) << RCAP_S)
812#define RCAP_F RCAP_V(1U)
813
814#define PLUP_S 23
815#define PLUP_V(x) ((x) << PLUP_S)
816#define PLUP_F PLUP_V(1U)
817
818#define PLDN_S 22
819#define PLDN_V(x) ((x) << PLDN_S)
820#define PLDN_F PLDN_V(1U)
821
822#define OTDD_S 21
823#define OTDD_V(x) ((x) << OTDD_S)
824#define OTDD_F OTDD_V(1U)
825
826#define GTRP_S 20
827#define GTRP_V(x) ((x) << GTRP_S)
828#define GTRP_F GTRP_V(1U)
829
830#define RDPE_S 18
831#define RDPE_V(x) ((x) << RDPE_S)
832#define RDPE_F RDPE_V(1U)
833
834#define TDCE_S 17
835#define TDCE_V(x) ((x) << TDCE_S)
836#define TDCE_F TDCE_V(1U)
837
838#define TDUE_S 16
839#define TDUE_V(x) ((x) << TDUE_S)
840#define TDUE_F TDUE_V(1U)
841
842
843#define MC_INT_CAUSE_A 0x7518
844#define MC_P_INT_CAUSE_A 0x41318
845
846#define ECC_UE_INT_CAUSE_S 2
847#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
848#define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U)
849
850#define ECC_CE_INT_CAUSE_S 1
851#define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)
852#define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U)
853
854#define PERR_INT_CAUSE_S 0
855#define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)
856#define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U)
857
858#define DBG_GPIO_EN_A 0x6010
859#define XGMAC_PORT_CFG_A 0x1000
860#define MAC_PORT_CFG_A 0x800
861
862#define SIGNAL_DET_S 14
863#define SIGNAL_DET_V(x) ((x) << SIGNAL_DET_S)
864#define SIGNAL_DET_F SIGNAL_DET_V(1U)
865
866#define MC_ECC_STATUS_A 0x751c
867#define MC_P_ECC_STATUS_A 0x4131c
868
869#define ECC_CECNT_S 16
870#define ECC_CECNT_M 0xffffU
871#define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)
872#define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)
873
874#define ECC_UECNT_S 0
875#define ECC_UECNT_M 0xffffU
876#define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
877#define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
878
879#define MC_BIST_CMD_A 0x7600
880
881#define START_BIST_S 31
882#define START_BIST_V(x) ((x) << START_BIST_S)
883#define START_BIST_F START_BIST_V(1U)
884
885#define BIST_CMD_GAP_S 8
886#define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)
887
888#define BIST_OPCODE_S 0
889#define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
890
891#define MC_BIST_CMD_ADDR_A 0x7604
892#define MC_BIST_CMD_LEN_A 0x7608
893#define MC_BIST_DATA_PATTERN_A 0x760c
894
895#define MC_BIST_STATUS_RDATA_A 0x7688
896
897
898#define MA_EDRAM0_BAR_A 0x77c0
899
900#define EDRAM0_BASE_S 16
901#define EDRAM0_BASE_M 0xfffU
902#define EDRAM0_BASE_G(x) (((x) >> EDRAM0_BASE_S) & EDRAM0_BASE_M)
903
904#define EDRAM0_SIZE_S 0
905#define EDRAM0_SIZE_M 0xfffU
906#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
907#define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
908
909#define MA_EDRAM1_BAR_A 0x77c4
910
911#define EDRAM1_BASE_S 16
912#define EDRAM1_BASE_M 0xfffU
913#define EDRAM1_BASE_G(x) (((x) >> EDRAM1_BASE_S) & EDRAM1_BASE_M)
914
915#define EDRAM1_SIZE_S 0
916#define EDRAM1_SIZE_M 0xfffU
917#define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
918#define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
919
920#define MA_EXT_MEMORY_BAR_A 0x77c8
921
922#define EXT_MEM_BASE_S 16
923#define EXT_MEM_BASE_M 0xfffU
924#define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S)
925#define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M)
926
927#define EXT_MEM_SIZE_S 0
928#define EXT_MEM_SIZE_M 0xfffU
929#define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
930#define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
931
932#define MA_EXT_MEMORY1_BAR_A 0x7808
933
934#define EXT_MEM1_BASE_S 16
935#define EXT_MEM1_BASE_M 0xfffU
936#define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)
937
938#define EXT_MEM1_SIZE_S 0
939#define EXT_MEM1_SIZE_M 0xfffU
940#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
941#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
942
943#define MA_EXT_MEMORY0_BAR_A 0x77c8
944
945#define EXT_MEM0_BASE_S 16
946#define EXT_MEM0_BASE_M 0xfffU
947#define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M)
948
949#define EXT_MEM0_SIZE_S 0
950#define EXT_MEM0_SIZE_M 0xfffU
951#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
952#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
953
954#define MA_TARGET_MEM_ENABLE_A 0x77d8
955
956#define EXT_MEM_ENABLE_S 2
957#define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
958#define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)
959
960#define EDRAM1_ENABLE_S 1
961#define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
962#define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)
963
964#define EDRAM0_ENABLE_S 0
965#define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
966#define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)
967
968#define EXT_MEM1_ENABLE_S 4
969#define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
970#define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)
971
972#define EXT_MEM0_ENABLE_S 2
973#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
974#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
975
976#define MA_INT_CAUSE_A 0x77e0
977
978#define MEM_PERR_INT_CAUSE_S 1
979#define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)
980#define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U)
981
982#define MEM_WRAP_INT_CAUSE_S 0
983#define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
984#define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U)
985
986#define MA_INT_WRAP_STATUS_A 0x77e4
987
988#define MEM_WRAP_ADDRESS_S 4
989#define MEM_WRAP_ADDRESS_M 0xfffffffU
990#define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)
991
992#define MEM_WRAP_CLIENT_NUM_S 0
993#define MEM_WRAP_CLIENT_NUM_M 0xfU
994#define MEM_WRAP_CLIENT_NUM_G(x) \
995 (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
996
997#define MA_PARITY_ERROR_STATUS_A 0x77f4
998#define MA_PARITY_ERROR_STATUS1_A 0x77f4
999#define MA_PARITY_ERROR_STATUS2_A 0x7804
1000
1001
1002#define EDC_0_BASE_ADDR 0x7900
1003
1004#define EDC_BIST_CMD_A 0x7904
1005#define EDC_BIST_CMD_ADDR_A 0x7908
1006#define EDC_BIST_CMD_LEN_A 0x790c
1007#define EDC_BIST_DATA_PATTERN_A 0x7910
1008#define EDC_BIST_STATUS_RDATA_A 0x7928
1009#define EDC_INT_CAUSE_A 0x7978
1010
1011#define ECC_UE_PAR_S 5
1012#define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
1013#define ECC_UE_PAR_F ECC_UE_PAR_V(1U)
1014
1015#define ECC_CE_PAR_S 4
1016#define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
1017#define ECC_CE_PAR_F ECC_CE_PAR_V(1U)
1018
1019#define PERR_PAR_CAUSE_S 3
1020#define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
1021#define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U)
1022
1023#define EDC_ECC_STATUS_A 0x797c
1024
1025
1026#define EDC_1_BASE_ADDR 0x7980
1027
1028
1029#define CIM_BOOT_CFG_A 0x7b00
1030#define CIM_SDRAM_BASE_ADDR_A 0x7b14
1031#define CIM_SDRAM_ADDR_SIZE_A 0x7b18
1032#define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c
1033#define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
1034#define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
1035
1036#define BOOTADDR_M 0xffffff00U
1037
1038#define UPCRST_S 0
1039#define UPCRST_V(x) ((x) << UPCRST_S)
1040#define UPCRST_F UPCRST_V(1U)
1041
1042#define CIM_PF_MAILBOX_DATA_A 0x240
1043#define CIM_PF_MAILBOX_CTRL_A 0x280
1044
1045#define MBMSGVALID_S 3
1046#define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
1047#define MBMSGVALID_F MBMSGVALID_V(1U)
1048
1049#define MBINTREQ_S 2
1050#define MBINTREQ_V(x) ((x) << MBINTREQ_S)
1051#define MBINTREQ_F MBINTREQ_V(1U)
1052
1053#define MBOWNER_S 0
1054#define MBOWNER_M 0x3U
1055#define MBOWNER_V(x) ((x) << MBOWNER_S)
1056#define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)
1057
1058#define CIM_PF_HOST_INT_ENABLE_A 0x288
1059
1060#define MBMSGRDYINTEN_S 19
1061#define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)
1062#define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U)
1063
1064#define CIM_PF_HOST_INT_CAUSE_A 0x28c
1065
1066#define MBMSGRDYINT_S 19
1067#define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
1068#define MBMSGRDYINT_F MBMSGRDYINT_V(1U)
1069
1070#define CIM_HOST_INT_CAUSE_A 0x7b2c
1071
1072#define TIEQOUTPARERRINT_S 20
1073#define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)
1074#define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U)
1075
1076#define TIEQINPARERRINT_S 19
1077#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
1078#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
1079
1080#define TIMER0INT_S 2
1081#define TIMER0INT_V(x) ((x) << TIMER0INT_S)
1082#define TIMER0INT_F TIMER0INT_V(1U)
1083
1084#define PREFDROPINT_S 1
1085#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
1086#define PREFDROPINT_F PREFDROPINT_V(1U)
1087
1088#define UPACCNONZERO_S 0
1089#define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
1090#define UPACCNONZERO_F UPACCNONZERO_V(1U)
1091
1092#define MBHOSTPARERR_S 18
1093#define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
1094#define MBHOSTPARERR_F MBHOSTPARERR_V(1U)
1095
1096#define MBUPPARERR_S 17
1097#define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)
1098#define MBUPPARERR_F MBUPPARERR_V(1U)
1099
1100#define IBQTP0PARERR_S 16
1101#define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)
1102#define IBQTP0PARERR_F IBQTP0PARERR_V(1U)
1103
1104#define IBQTP1PARERR_S 15
1105#define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)
1106#define IBQTP1PARERR_F IBQTP1PARERR_V(1U)
1107
1108#define IBQULPPARERR_S 14
1109#define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)
1110#define IBQULPPARERR_F IBQULPPARERR_V(1U)
1111
1112#define IBQSGELOPARERR_S 13
1113#define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)
1114#define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U)
1115
1116#define IBQSGEHIPARERR_S 12
1117#define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)
1118#define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U)
1119
1120#define IBQNCSIPARERR_S 11
1121#define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)
1122#define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U)
1123
1124#define OBQULP0PARERR_S 10
1125#define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)
1126#define OBQULP0PARERR_F OBQULP0PARERR_V(1U)
1127
1128#define OBQULP1PARERR_S 9
1129#define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)
1130#define OBQULP1PARERR_F OBQULP1PARERR_V(1U)
1131
1132#define OBQULP2PARERR_S 8
1133#define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)
1134#define OBQULP2PARERR_F OBQULP2PARERR_V(1U)
1135
1136#define OBQULP3PARERR_S 7
1137#define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)
1138#define OBQULP3PARERR_F OBQULP3PARERR_V(1U)
1139
1140#define OBQSGEPARERR_S 6
1141#define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)
1142#define OBQSGEPARERR_F OBQSGEPARERR_V(1U)
1143
1144#define OBQNCSIPARERR_S 5
1145#define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
1146#define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U)
1147
1148#define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1149
1150#define EEPROMWRINT_S 30
1151#define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)
1152#define EEPROMWRINT_F EEPROMWRINT_V(1U)
1153
1154#define TIMEOUTMAINT_S 29
1155#define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)
1156#define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U)
1157
1158#define TIMEOUTINT_S 28
1159#define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)
1160#define TIMEOUTINT_F TIMEOUTINT_V(1U)
1161
1162#define RSPOVRLOOKUPINT_S 27
1163#define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)
1164#define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U)
1165
1166#define REQOVRLOOKUPINT_S 26
1167#define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)
1168#define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U)
1169
1170#define BLKWRPLINT_S 25
1171#define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)
1172#define BLKWRPLINT_F BLKWRPLINT_V(1U)
1173
1174#define BLKRDPLINT_S 24
1175#define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)
1176#define BLKRDPLINT_F BLKRDPLINT_V(1U)
1177
1178#define SGLWRPLINT_S 23
1179#define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)
1180#define SGLWRPLINT_F SGLWRPLINT_V(1U)
1181
1182#define SGLRDPLINT_S 22
1183#define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)
1184#define SGLRDPLINT_F SGLRDPLINT_V(1U)
1185
1186#define BLKWRCTLINT_S 21
1187#define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)
1188#define BLKWRCTLINT_F BLKWRCTLINT_V(1U)
1189
1190#define BLKRDCTLINT_S 20
1191#define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)
1192#define BLKRDCTLINT_F BLKRDCTLINT_V(1U)
1193
1194#define SGLWRCTLINT_S 19
1195#define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)
1196#define SGLWRCTLINT_F SGLWRCTLINT_V(1U)
1197
1198#define SGLRDCTLINT_S 18
1199#define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)
1200#define SGLRDCTLINT_F SGLRDCTLINT_V(1U)
1201
1202#define BLKWREEPROMINT_S 17
1203#define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)
1204#define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U)
1205
1206#define BLKRDEEPROMINT_S 16
1207#define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)
1208#define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U)
1209
1210#define SGLWREEPROMINT_S 15
1211#define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)
1212#define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U)
1213
1214#define SGLRDEEPROMINT_S 14
1215#define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)
1216#define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U)
1217
1218#define BLKWRFLASHINT_S 13
1219#define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)
1220#define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U)
1221
1222#define BLKRDFLASHINT_S 12
1223#define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)
1224#define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U)
1225
1226#define SGLWRFLASHINT_S 11
1227#define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)
1228#define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U)
1229
1230#define SGLRDFLASHINT_S 10
1231#define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)
1232#define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U)
1233
1234#define BLKWRBOOTINT_S 9
1235#define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)
1236#define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U)
1237
1238#define BLKRDBOOTINT_S 8
1239#define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)
1240#define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U)
1241
1242#define SGLWRBOOTINT_S 7
1243#define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)
1244#define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U)
1245
1246#define SGLRDBOOTINT_S 6
1247#define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)
1248#define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U)
1249
1250#define ILLWRBEINT_S 5
1251#define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)
1252#define ILLWRBEINT_F ILLWRBEINT_V(1U)
1253
1254#define ILLRDBEINT_S 4
1255#define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)
1256#define ILLRDBEINT_F ILLRDBEINT_V(1U)
1257
1258#define ILLRDINT_S 3
1259#define ILLRDINT_V(x) ((x) << ILLRDINT_S)
1260#define ILLRDINT_F ILLRDINT_V(1U)
1261
1262#define ILLWRINT_S 2
1263#define ILLWRINT_V(x) ((x) << ILLWRINT_S)
1264#define ILLWRINT_F ILLWRINT_V(1U)
1265
1266#define ILLTRANSINT_S 1
1267#define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)
1268#define ILLTRANSINT_F ILLTRANSINT_V(1U)
1269
1270#define RSVDSPACEINT_S 0
1271#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
1272#define RSVDSPACEINT_F RSVDSPACEINT_V(1U)
1273
1274
1275#define DBGLAWHLF_S 23
1276#define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)
1277#define DBGLAWHLF_F DBGLAWHLF_V(1U)
1278
1279#define DBGLAWPTR_S 16
1280#define DBGLAWPTR_M 0x7fU
1281#define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M)
1282
1283#define DBGLAENABLE_S 12
1284#define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S)
1285#define DBGLAENABLE_F DBGLAENABLE_V(1U)
1286
1287#define DBGLARPTR_S 0
1288#define DBGLARPTR_M 0x7fU
1289#define DBGLARPTR_V(x) ((x) << DBGLARPTR_S)
1290
1291#define CRXPKTENC_S 3
1292#define CRXPKTENC_V(x) ((x) << CRXPKTENC_S)
1293#define CRXPKTENC_F CRXPKTENC_V(1U)
1294
1295#define TP_DBG_LA_DATAL_A 0x7ed8
1296#define TP_DBG_LA_CONFIG_A 0x7ed4
1297#define TP_OUT_CONFIG_A 0x7d04
1298#define TP_GLOBAL_CONFIG_A 0x7d08
1299
1300#define TP_CMM_TCB_BASE_A 0x7d10
1301#define TP_CMM_MM_BASE_A 0x7d14
1302#define TP_CMM_TIMER_BASE_A 0x7d18
1303#define TP_PMM_TX_BASE_A 0x7d20
1304#define TP_PMM_RX_BASE_A 0x7d28
1305#define TP_PMM_RX_PAGE_SIZE_A 0x7d2c
1306#define TP_PMM_RX_MAX_PAGE_A 0x7d30
1307#define TP_PMM_TX_PAGE_SIZE_A 0x7d34
1308#define TP_PMM_TX_MAX_PAGE_A 0x7d38
1309#define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c
1310
1311#define PMRXNUMCHN_S 31
1312#define PMRXNUMCHN_V(x) ((x) << PMRXNUMCHN_S)
1313#define PMRXNUMCHN_F PMRXNUMCHN_V(1U)
1314
1315#define PMTXNUMCHN_S 30
1316#define PMTXNUMCHN_M 0x3U
1317#define PMTXNUMCHN_G(x) (((x) >> PMTXNUMCHN_S) & PMTXNUMCHN_M)
1318
1319#define PMTXMAXPAGE_S 0
1320#define PMTXMAXPAGE_M 0x1fffffU
1321#define PMTXMAXPAGE_G(x) (((x) >> PMTXMAXPAGE_S) & PMTXMAXPAGE_M)
1322
1323#define PMRXMAXPAGE_S 0
1324#define PMRXMAXPAGE_M 0x1fffffU
1325#define PMRXMAXPAGE_G(x) (((x) >> PMRXMAXPAGE_S) & PMRXMAXPAGE_M)
1326
1327#define DBGLAMODE_S 14
1328#define DBGLAMODE_M 0x3U
1329#define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M)
1330
1331#define FIVETUPLELOOKUP_S 17
1332#define FIVETUPLELOOKUP_M 0x3U
1333#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
1334#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
1335
1336#define TP_PARA_REG2_A 0x7d68
1337
1338#define MAXRXDATA_S 16
1339#define MAXRXDATA_M 0xffffU
1340#define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
1341
1342#define TP_TIMER_RESOLUTION_A 0x7d90
1343
1344#define TIMERRESOLUTION_S 16
1345#define TIMERRESOLUTION_M 0xffU
1346#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
1347
1348#define TIMESTAMPRESOLUTION_S 8
1349#define TIMESTAMPRESOLUTION_M 0xffU
1350#define TIMESTAMPRESOLUTION_G(x) \
1351 (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)
1352
1353#define DELAYEDACKRESOLUTION_S 0
1354#define DELAYEDACKRESOLUTION_M 0xffU
1355#define DELAYEDACKRESOLUTION_G(x) \
1356 (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
1357
1358#define TP_SHIFT_CNT_A 0x7dc0
1359#define TP_RXT_MIN_A 0x7d98
1360#define TP_RXT_MAX_A 0x7d9c
1361#define TP_PERS_MIN_A 0x7da0
1362#define TP_PERS_MAX_A 0x7da4
1363#define TP_KEEP_IDLE_A 0x7da8
1364#define TP_KEEP_INTVL_A 0x7dac
1365#define TP_INIT_SRTT_A 0x7db0
1366#define TP_DACK_TIMER_A 0x7db4
1367#define TP_FINWAIT2_TIMER_A 0x7db8
1368
1369#define INITSRTT_S 0
1370#define INITSRTT_M 0xffffU
1371#define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
1372
1373#define PERSMAX_S 0
1374#define PERSMAX_M 0x3fffffffU
1375#define PERSMAX_V(x) ((x) << PERSMAX_S)
1376#define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
1377
1378#define SYNSHIFTMAX_S 24
1379#define SYNSHIFTMAX_M 0xffU
1380#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
1381#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
1382
1383#define RXTSHIFTMAXR1_S 20
1384#define RXTSHIFTMAXR1_M 0xfU
1385#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
1386#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
1387
1388#define RXTSHIFTMAXR2_S 16
1389#define RXTSHIFTMAXR2_M 0xfU
1390#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
1391#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
1392
1393#define PERSHIFTBACKOFFMAX_S 12
1394#define PERSHIFTBACKOFFMAX_M 0xfU
1395#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
1396#define PERSHIFTBACKOFFMAX_G(x) \
1397 (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
1398
1399#define PERSHIFTMAX_S 8
1400#define PERSHIFTMAX_M 0xfU
1401#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
1402#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
1403
1404#define KEEPALIVEMAXR1_S 4
1405#define KEEPALIVEMAXR1_M 0xfU
1406#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
1407#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
1408
1409#define KEEPALIVEMAXR2_S 0
1410#define KEEPALIVEMAXR2_M 0xfU
1411#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
1412#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
1413
1414#define ROWINDEX_S 16
1415#define ROWINDEX_V(x) ((x) << ROWINDEX_S)
1416
1417#define TP_CCTRL_TABLE_A 0x7ddc
1418#define TP_MTU_TABLE_A 0x7de4
1419
1420#define MTUINDEX_S 24
1421#define MTUINDEX_V(x) ((x) << MTUINDEX_S)
1422
1423#define MTUWIDTH_S 16
1424#define MTUWIDTH_M 0xfU
1425#define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
1426#define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
1427
1428#define MTUVALUE_S 0
1429#define MTUVALUE_M 0x3fffU
1430#define MTUVALUE_V(x) ((x) << MTUVALUE_S)
1431#define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
1432
1433#define TP_RSS_LKP_TABLE_A 0x7dec
1434#define TP_CMM_MM_RX_FLST_BASE_A 0x7e60
1435#define TP_CMM_MM_TX_FLST_BASE_A 0x7e64
1436#define TP_CMM_MM_PS_FLST_BASE_A 0x7e68
1437
1438#define LKPTBLROWVLD_S 31
1439#define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
1440#define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U)
1441
1442#define LKPTBLQUEUE1_S 10
1443#define LKPTBLQUEUE1_M 0x3ffU
1444#define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
1445
1446#define LKPTBLQUEUE0_S 0
1447#define LKPTBLQUEUE0_M 0x3ffU
1448#define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
1449
1450#define TP_PIO_ADDR_A 0x7e40
1451#define TP_PIO_DATA_A 0x7e44
1452#define TP_MIB_INDEX_A 0x7e50
1453#define TP_MIB_DATA_A 0x7e54
1454#define TP_INT_CAUSE_A 0x7e74
1455
1456#define FLMTXFLSTEMPTY_S 30
1457#define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
1458#define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U)
1459
1460#define TP_TX_ORATE_A 0x7ebc
1461
1462#define OFDRATE3_S 24
1463#define OFDRATE3_M 0xffU
1464#define OFDRATE3_G(x) (((x) >> OFDRATE3_S) & OFDRATE3_M)
1465
1466#define OFDRATE2_S 16
1467#define OFDRATE2_M 0xffU
1468#define OFDRATE2_G(x) (((x) >> OFDRATE2_S) & OFDRATE2_M)
1469
1470#define OFDRATE1_S 8
1471#define OFDRATE1_M 0xffU
1472#define OFDRATE1_G(x) (((x) >> OFDRATE1_S) & OFDRATE1_M)
1473
1474#define OFDRATE0_S 0
1475#define OFDRATE0_M 0xffU
1476#define OFDRATE0_G(x) (((x) >> OFDRATE0_S) & OFDRATE0_M)
1477
1478#define TP_TX_TRATE_A 0x7ed0
1479
1480#define TNLRATE3_S 24
1481#define TNLRATE3_M 0xffU
1482#define TNLRATE3_G(x) (((x) >> TNLRATE3_S) & TNLRATE3_M)
1483
1484#define TNLRATE2_S 16
1485#define TNLRATE2_M 0xffU
1486#define TNLRATE2_G(x) (((x) >> TNLRATE2_S) & TNLRATE2_M)
1487
1488#define TNLRATE1_S 8
1489#define TNLRATE1_M 0xffU
1490#define TNLRATE1_G(x) (((x) >> TNLRATE1_S) & TNLRATE1_M)
1491
1492#define TNLRATE0_S 0
1493#define TNLRATE0_M 0xffU
1494#define TNLRATE0_G(x) (((x) >> TNLRATE0_S) & TNLRATE0_M)
1495
1496#define TP_VLAN_PRI_MAP_A 0x140
1497
1498#define FRAGMENTATION_S 9
1499#define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
1500#define FRAGMENTATION_F FRAGMENTATION_V(1U)
1501
1502#define MPSHITTYPE_S 8
1503#define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
1504#define MPSHITTYPE_F MPSHITTYPE_V(1U)
1505
1506#define MACMATCH_S 7
1507#define MACMATCH_V(x) ((x) << MACMATCH_S)
1508#define MACMATCH_F MACMATCH_V(1U)
1509
1510#define ETHERTYPE_S 6
1511#define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
1512#define ETHERTYPE_F ETHERTYPE_V(1U)
1513
1514#define PROTOCOL_S 5
1515#define PROTOCOL_V(x) ((x) << PROTOCOL_S)
1516#define PROTOCOL_F PROTOCOL_V(1U)
1517
1518#define TOS_S 4
1519#define TOS_V(x) ((x) << TOS_S)
1520#define TOS_F TOS_V(1U)
1521
1522#define VLAN_S 3
1523#define VLAN_V(x) ((x) << VLAN_S)
1524#define VLAN_F VLAN_V(1U)
1525
1526#define VNIC_ID_S 2
1527#define VNIC_ID_V(x) ((x) << VNIC_ID_S)
1528#define VNIC_ID_F VNIC_ID_V(1U)
1529
1530#define PORT_S 1
1531#define PORT_V(x) ((x) << PORT_S)
1532#define PORT_F PORT_V(1U)
1533
1534#define FCOE_S 0
1535#define FCOE_V(x) ((x) << FCOE_S)
1536#define FCOE_F FCOE_V(1U)
1537
1538#define FILTERMODE_S 15
1539#define FILTERMODE_V(x) ((x) << FILTERMODE_S)
1540#define FILTERMODE_F FILTERMODE_V(1U)
1541
1542#define FCOEMASK_S 14
1543#define FCOEMASK_V(x) ((x) << FCOEMASK_S)
1544#define FCOEMASK_F FCOEMASK_V(1U)
1545
1546#define TP_INGRESS_CONFIG_A 0x141
1547
1548#define VNIC_S 11
1549#define VNIC_V(x) ((x) << VNIC_S)
1550#define VNIC_F VNIC_V(1U)
1551
1552#define CSUM_HAS_PSEUDO_HDR_S 10
1553#define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
1554#define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U)
1555
1556#define TP_MIB_MAC_IN_ERR_0_A 0x0
1557#define TP_MIB_HDR_IN_ERR_0_A 0x4
1558#define TP_MIB_TCP_IN_ERR_0_A 0x8
1559#define TP_MIB_TCP_OUT_RST_A 0xc
1560#define TP_MIB_TCP_IN_SEG_HI_A 0x10
1561#define TP_MIB_TCP_IN_SEG_LO_A 0x11
1562#define TP_MIB_TCP_OUT_SEG_HI_A 0x12
1563#define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1564#define TP_MIB_TCP_RXT_SEG_HI_A 0x14
1565#define TP_MIB_TCP_RXT_SEG_LO_A 0x15
1566#define TP_MIB_TNL_CNG_DROP_0_A 0x18
1567#define TP_MIB_OFD_CHN_DROP_0_A 0x1c
1568#define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1569#define TP_MIB_TCP_V6OUT_RST_A 0x2c
1570#define TP_MIB_OFD_ARP_DROP_A 0x36
1571#define TP_MIB_CPL_IN_REQ_0_A 0x38
1572#define TP_MIB_CPL_OUT_RSP_0_A 0x3c
1573#define TP_MIB_TNL_DROP_0_A 0x44
1574#define TP_MIB_FCOE_DDP_0_A 0x48
1575#define TP_MIB_FCOE_DROP_0_A 0x4c
1576#define TP_MIB_FCOE_BYTE_0_HI_A 0x50
1577#define TP_MIB_OFD_VLN_DROP_0_A 0x58
1578#define TP_MIB_USM_PKTS_A 0x5c
1579#define TP_MIB_RQE_DFR_PKT_A 0x64
1580
1581#define ULP_TX_INT_CAUSE_A 0x8dcc
1582#define ULP_TX_TPT_LLIMIT_A 0x8dd4
1583#define ULP_TX_TPT_ULIMIT_A 0x8dd8
1584#define ULP_TX_PBL_LLIMIT_A 0x8ddc
1585#define ULP_TX_PBL_ULIMIT_A 0x8de0
1586#define ULP_TX_ERR_TABLE_BASE_A 0x8e04
1587
1588#define PBL_BOUND_ERR_CH3_S 31
1589#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
1590#define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U)
1591
1592#define PBL_BOUND_ERR_CH2_S 30
1593#define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
1594#define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U)
1595
1596#define PBL_BOUND_ERR_CH1_S 29
1597#define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
1598#define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U)
1599
1600#define PBL_BOUND_ERR_CH0_S 28
1601#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
1602#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
1603
1604#define PM_RX_INT_CAUSE_A 0x8fdc
1605#define PM_RX_STAT_CONFIG_A 0x8fc8
1606#define PM_RX_STAT_COUNT_A 0x8fcc
1607#define PM_RX_STAT_LSB_A 0x8fd0
1608#define PM_RX_DBG_CTRL_A 0x8fd0
1609#define PM_RX_DBG_DATA_A 0x8fd4
1610#define PM_RX_DBG_STAT_MSB_A 0x10013
1611
1612#define PMRX_FRAMING_ERROR_F 0x003ffff0U
1613
1614#define ZERO_E_CMD_ERROR_S 22
1615#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
1616#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
1617
1618#define OCSPI_PAR_ERROR_S 3
1619#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
1620#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
1621
1622#define DB_OPTIONS_PAR_ERROR_S 2
1623#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
1624#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
1625
1626#define IESPI_PAR_ERROR_S 1
1627#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
1628#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
1629
1630#define PMRX_E_PCMD_PAR_ERROR_S 0
1631#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
1632#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
1633
1634#define PM_TX_INT_CAUSE_A 0x8ffc
1635#define PM_TX_STAT_CONFIG_A 0x8fe8
1636#define PM_TX_STAT_COUNT_A 0x8fec
1637#define PM_TX_STAT_LSB_A 0x8ff0
1638#define PM_TX_DBG_CTRL_A 0x8ff0
1639#define PM_TX_DBG_DATA_A 0x8ff4
1640#define PM_TX_DBG_STAT_MSB_A 0x1001a
1641
1642#define PCMD_LEN_OVFL0_S 31
1643#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
1644#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
1645
1646#define PCMD_LEN_OVFL1_S 30
1647#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
1648#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
1649
1650#define PCMD_LEN_OVFL2_S 29
1651#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
1652#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
1653
1654#define ZERO_C_CMD_ERROR_S 28
1655#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
1656#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
1657
1658#define PMTX_FRAMING_ERROR_F 0x0ffffff0U
1659
1660#define OESPI_PAR_ERROR_S 3
1661#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
1662#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
1663
1664#define ICSPI_PAR_ERROR_S 1
1665#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
1666#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
1667
1668#define PMTX_C_PCMD_PAR_ERROR_S 0
1669#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
1670#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
1671
1672#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1673#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1674#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1675#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1676#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1677#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1678#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1679#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1680#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1681#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1682#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1683#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1684#define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1685#define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1686#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1687#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1688#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1689#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1690#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1691#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1692#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1693#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1694#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1695#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1696#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1697#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1698#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1699#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1700#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1701#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1702#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1703#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1704#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1705#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1706#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1707#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1708#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1709#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1710#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1711#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1712#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1713#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1714#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1715#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1716#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1717#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1718#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1719#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1720#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1721#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1722#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1723#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1724#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1725#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1726#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1727#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1728#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1729#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1730#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1731#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1732#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1733#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1734#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1735#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1736#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1737#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1738#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1739#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1740#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1741#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1742#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1743#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1744#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1745#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
1746#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1747#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1748#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1749#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1750#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1751#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1752#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1753#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1754#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1755#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1756#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1757#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1758#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1759#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1760#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1761#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1762#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1763#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1764#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1765#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1766#define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1767#define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1768#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1769#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1770#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1771#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1772#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1773#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1774#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1775#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1776#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1777#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1778#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1779#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1780#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1781#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1782#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1783#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1784#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1785#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1786#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1787#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1788#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1789#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1790#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1791#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1792#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1793#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1794#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1795#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1796#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1797#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1798#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1799#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1800#define MAC_PORT_MAGIC_MACID_LO 0x824
1801#define MAC_PORT_MAGIC_MACID_HI 0x828
1802#define MAC_PORT_TX_TS_VAL_LO 0x928
1803#define MAC_PORT_TX_TS_VAL_HI 0x92c
1804
1805#define MAC_PORT_EPIO_DATA0_A 0x8c0
1806#define MAC_PORT_EPIO_DATA1_A 0x8c4
1807#define MAC_PORT_EPIO_DATA2_A 0x8c8
1808#define MAC_PORT_EPIO_DATA3_A 0x8cc
1809#define MAC_PORT_EPIO_OP_A 0x8d0
1810
1811#define MAC_PORT_CFG2_A 0x818
1812
1813#define MPS_CMN_CTL_A 0x9000
1814
1815#define COUNTPAUSEMCRX_S 5
1816#define COUNTPAUSEMCRX_V(x) ((x) << COUNTPAUSEMCRX_S)
1817#define COUNTPAUSEMCRX_F COUNTPAUSEMCRX_V(1U)
1818
1819#define COUNTPAUSESTATRX_S 4
1820#define COUNTPAUSESTATRX_V(x) ((x) << COUNTPAUSESTATRX_S)
1821#define COUNTPAUSESTATRX_F COUNTPAUSESTATRX_V(1U)
1822
1823#define COUNTPAUSEMCTX_S 3
1824#define COUNTPAUSEMCTX_V(x) ((x) << COUNTPAUSEMCTX_S)
1825#define COUNTPAUSEMCTX_F COUNTPAUSEMCTX_V(1U)
1826
1827#define COUNTPAUSESTATTX_S 2
1828#define COUNTPAUSESTATTX_V(x) ((x) << COUNTPAUSESTATTX_S)
1829#define COUNTPAUSESTATTX_F COUNTPAUSESTATTX_V(1U)
1830
1831#define NUMPORTS_S 0
1832#define NUMPORTS_M 0x3U
1833#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
1834
1835#define MPS_INT_CAUSE_A 0x9008
1836#define MPS_TX_INT_CAUSE_A 0x9408
1837#define MPS_STAT_CTL_A 0x9600
1838
1839#define FRMERR_S 15
1840#define FRMERR_V(x) ((x) << FRMERR_S)
1841#define FRMERR_F FRMERR_V(1U)
1842
1843#define SECNTERR_S 14
1844#define SECNTERR_V(x) ((x) << SECNTERR_S)
1845#define SECNTERR_F SECNTERR_V(1U)
1846
1847#define BUBBLE_S 13
1848#define BUBBLE_V(x) ((x) << BUBBLE_S)
1849#define BUBBLE_F BUBBLE_V(1U)
1850
1851#define TXDESCFIFO_S 9
1852#define TXDESCFIFO_M 0xfU
1853#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
1854
1855#define TXDATAFIFO_S 5
1856#define TXDATAFIFO_M 0xfU
1857#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
1858
1859#define NCSIFIFO_S 4
1860#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
1861#define NCSIFIFO_F NCSIFIFO_V(1U)
1862
1863#define TPFIFO_S 0
1864#define TPFIFO_M 0xfU
1865#define TPFIFO_V(x) ((x) << TPFIFO_S)
1866
1867#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
1868#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
1869#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
1870
1871#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1872#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1873#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1874#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1875#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1876#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1877#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1878#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1879#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1880#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1881#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1882#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1883#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1884#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1885#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1886#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1887#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1888#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1889#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1890#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1891#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1892#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1893#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1894#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1895#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1896#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1897#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1898#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1899#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1900#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1901#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1902#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1903
1904#define MPS_TRC_CFG_A 0x9800
1905
1906#define TRCFIFOEMPTY_S 4
1907#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
1908#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
1909
1910#define TRCIGNOREDROPINPUT_S 3
1911#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
1912#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
1913
1914#define TRCKEEPDUPLICATES_S 2
1915#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
1916#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
1917
1918#define TRCEN_S 1
1919#define TRCEN_V(x) ((x) << TRCEN_S)
1920#define TRCEN_F TRCEN_V(1U)
1921
1922#define TRCMULTIFILTER_S 0
1923#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
1924#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
1925
1926#define MPS_TRC_RSS_CONTROL_A 0x9808
1927#define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4
1928#define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc
1929#define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004
1930#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
1931
1932#define RSSCONTROL_S 16
1933#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
1934
1935#define QUEUENUMBER_S 0
1936#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
1937
1938#define TFINVERTMATCH_S 24
1939#define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)
1940#define TFINVERTMATCH_F TFINVERTMATCH_V(1U)
1941
1942#define TFEN_S 22
1943#define TFEN_V(x) ((x) << TFEN_S)
1944#define TFEN_F TFEN_V(1U)
1945
1946#define TFPORT_S 18
1947#define TFPORT_M 0xfU
1948#define TFPORT_V(x) ((x) << TFPORT_S)
1949#define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)
1950
1951#define TFLENGTH_S 8
1952#define TFLENGTH_M 0x1fU
1953#define TFLENGTH_V(x) ((x) << TFLENGTH_S)
1954#define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)
1955
1956#define TFOFFSET_S 0
1957#define TFOFFSET_M 0x1fU
1958#define TFOFFSET_V(x) ((x) << TFOFFSET_S)
1959#define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)
1960
1961#define T5_TFINVERTMATCH_S 25
1962#define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)
1963#define T5_TFINVERTMATCH_F T5_TFINVERTMATCH_V(1U)
1964
1965#define T5_TFEN_S 23
1966#define T5_TFEN_V(x) ((x) << T5_TFEN_S)
1967#define T5_TFEN_F T5_TFEN_V(1U)
1968
1969#define T5_TFPORT_S 18
1970#define T5_TFPORT_M 0x1fU
1971#define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)
1972#define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)
1973
1974#define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
1975#define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
1976
1977#define TFMINPKTSIZE_S 16
1978#define TFMINPKTSIZE_M 0x1ffU
1979#define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)
1980#define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)
1981
1982#define TFCAPTUREMAX_S 0
1983#define TFCAPTUREMAX_M 0x3fffU
1984#define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)
1985#define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)
1986
1987#define MPS_TRC_FILTER0_MATCH_A 0x9c00
1988#define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
1989#define MPS_TRC_FILTER1_MATCH_A 0x9d00
1990
1991#define TP_RSS_CONFIG_A 0x7df0
1992
1993#define TNL4TUPENIPV6_S 31
1994#define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
1995#define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U)
1996
1997#define TNL2TUPENIPV6_S 30
1998#define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
1999#define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U)
2000
2001#define TNL4TUPENIPV4_S 29
2002#define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
2003#define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U)
2004
2005#define TNL2TUPENIPV4_S 28
2006#define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
2007#define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U)
2008
2009#define TNLTCPSEL_S 27
2010#define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
2011#define TNLTCPSEL_F TNLTCPSEL_V(1U)
2012
2013#define TNLIP6SEL_S 26
2014#define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
2015#define TNLIP6SEL_F TNLIP6SEL_V(1U)
2016
2017#define TNLVRTSEL_S 25
2018#define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
2019#define TNLVRTSEL_F TNLVRTSEL_V(1U)
2020
2021#define TNLMAPEN_S 24
2022#define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
2023#define TNLMAPEN_F TNLMAPEN_V(1U)
2024
2025#define OFDHASHSAVE_S 19
2026#define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
2027#define OFDHASHSAVE_F OFDHASHSAVE_V(1U)
2028
2029#define OFDVRTSEL_S 18
2030#define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
2031#define OFDVRTSEL_F OFDVRTSEL_V(1U)
2032
2033#define OFDMAPEN_S 17
2034#define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
2035#define OFDMAPEN_F OFDMAPEN_V(1U)
2036
2037#define OFDLKPEN_S 16
2038#define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
2039#define OFDLKPEN_F OFDLKPEN_V(1U)
2040
2041#define SYN4TUPENIPV6_S 15
2042#define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
2043#define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U)
2044
2045#define SYN2TUPENIPV6_S 14
2046#define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
2047#define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U)
2048
2049#define SYN4TUPENIPV4_S 13
2050#define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
2051#define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U)
2052
2053#define SYN2TUPENIPV4_S 12
2054#define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
2055#define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U)
2056
2057#define SYNIP6SEL_S 11
2058#define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
2059#define SYNIP6SEL_F SYNIP6SEL_V(1U)
2060
2061#define SYNVRTSEL_S 10
2062#define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
2063#define SYNVRTSEL_F SYNVRTSEL_V(1U)
2064
2065#define SYNMAPEN_S 9
2066#define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
2067#define SYNMAPEN_F SYNMAPEN_V(1U)
2068
2069#define SYNLKPEN_S 8
2070#define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
2071#define SYNLKPEN_F SYNLKPEN_V(1U)
2072
2073#define CHANNELENABLE_S 7
2074#define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
2075#define CHANNELENABLE_F CHANNELENABLE_V(1U)
2076
2077#define PORTENABLE_S 6
2078#define PORTENABLE_V(x) ((x) << PORTENABLE_S)
2079#define PORTENABLE_F PORTENABLE_V(1U)
2080
2081#define TNLALLLOOKUP_S 5
2082#define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
2083#define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U)
2084
2085#define VIRTENABLE_S 4
2086#define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
2087#define VIRTENABLE_F VIRTENABLE_V(1U)
2088
2089#define CONGESTIONENABLE_S 3
2090#define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
2091#define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U)
2092
2093#define HASHTOEPLITZ_S 2
2094#define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
2095#define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U)
2096
2097#define UDPENABLE_S 1
2098#define UDPENABLE_V(x) ((x) << UDPENABLE_S)
2099#define UDPENABLE_F UDPENABLE_V(1U)
2100
2101#define DISABLE_S 0
2102#define DISABLE_V(x) ((x) << DISABLE_S)
2103#define DISABLE_F DISABLE_V(1U)
2104
2105#define TP_RSS_CONFIG_TNL_A 0x7df4
2106
2107#define MASKSIZE_S 28
2108#define MASKSIZE_M 0xfU
2109#define MASKSIZE_V(x) ((x) << MASKSIZE_S)
2110#define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
2111
2112#define MASKFILTER_S 16
2113#define MASKFILTER_M 0x7ffU
2114#define MASKFILTER_V(x) ((x) << MASKFILTER_S)
2115#define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
2116
2117#define USEWIRECH_S 0
2118#define USEWIRECH_V(x) ((x) << USEWIRECH_S)
2119#define USEWIRECH_F USEWIRECH_V(1U)
2120
2121#define HASHALL_S 2
2122#define HASHALL_V(x) ((x) << HASHALL_S)
2123#define HASHALL_F HASHALL_V(1U)
2124
2125#define HASHETH_S 1
2126#define HASHETH_V(x) ((x) << HASHETH_S)
2127#define HASHETH_F HASHETH_V(1U)
2128
2129#define TP_RSS_CONFIG_OFD_A 0x7df8
2130
2131#define RRCPLMAPEN_S 20
2132#define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
2133#define RRCPLMAPEN_F RRCPLMAPEN_V(1U)
2134
2135#define RRCPLQUEWIDTH_S 16
2136#define RRCPLQUEWIDTH_M 0xfU
2137#define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
2138#define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
2139
2140#define TP_RSS_CONFIG_SYN_A 0x7dfc
2141#define TP_RSS_CONFIG_VRT_A 0x7e00
2142
2143#define VFRDRG_S 25
2144#define VFRDRG_V(x) ((x) << VFRDRG_S)
2145#define VFRDRG_F VFRDRG_V(1U)
2146
2147#define VFRDEN_S 24
2148#define VFRDEN_V(x) ((x) << VFRDEN_S)
2149#define VFRDEN_F VFRDEN_V(1U)
2150
2151#define VFPERREN_S 23
2152#define VFPERREN_V(x) ((x) << VFPERREN_S)
2153#define VFPERREN_F VFPERREN_V(1U)
2154
2155#define KEYPERREN_S 22
2156#define KEYPERREN_V(x) ((x) << KEYPERREN_S)
2157#define KEYPERREN_F KEYPERREN_V(1U)
2158
2159#define DISABLEVLAN_S 21
2160#define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
2161#define DISABLEVLAN_F DISABLEVLAN_V(1U)
2162
2163#define ENABLEUP0_S 20
2164#define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
2165#define ENABLEUP0_F ENABLEUP0_V(1U)
2166
2167#define HASHDELAY_S 16
2168#define HASHDELAY_M 0xfU
2169#define HASHDELAY_V(x) ((x) << HASHDELAY_S)
2170#define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
2171
2172#define VFWRADDR_S 8
2173#define VFWRADDR_M 0x7fU
2174#define VFWRADDR_V(x) ((x) << VFWRADDR_S)
2175#define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
2176
2177#define KEYMODE_S 6
2178#define KEYMODE_M 0x3U
2179#define KEYMODE_V(x) ((x) << KEYMODE_S)
2180#define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
2181
2182#define VFWREN_S 5
2183#define VFWREN_V(x) ((x) << VFWREN_S)
2184#define VFWREN_F VFWREN_V(1U)
2185
2186#define KEYWREN_S 4
2187#define KEYWREN_V(x) ((x) << KEYWREN_S)
2188#define KEYWREN_F KEYWREN_V(1U)
2189
2190#define KEYWRADDR_S 0
2191#define KEYWRADDR_M 0xfU
2192#define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
2193#define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
2194
2195#define KEYWRADDRX_S 30
2196#define KEYWRADDRX_M 0x3U
2197#define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
2198#define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
2199
2200#define KEYEXTEND_S 26
2201#define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
2202#define KEYEXTEND_F KEYEXTEND_V(1U)
2203
2204#define LKPIDXSIZE_S 24
2205#define LKPIDXSIZE_M 0x3U
2206#define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
2207#define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
2208
2209#define TP_RSS_VFL_CONFIG_A 0x3a
2210#define TP_RSS_VFH_CONFIG_A 0x3b
2211
2212#define ENABLEUDPHASH_S 31
2213#define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
2214#define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U)
2215
2216#define VFUPEN_S 30
2217#define VFUPEN_V(x) ((x) << VFUPEN_S)
2218#define VFUPEN_F VFUPEN_V(1U)
2219
2220#define VFVLNEX_S 28
2221#define VFVLNEX_V(x) ((x) << VFVLNEX_S)
2222#define VFVLNEX_F VFVLNEX_V(1U)
2223
2224#define VFPRTEN_S 27
2225#define VFPRTEN_V(x) ((x) << VFPRTEN_S)
2226#define VFPRTEN_F VFPRTEN_V(1U)
2227
2228#define VFCHNEN_S 26
2229#define VFCHNEN_V(x) ((x) << VFCHNEN_S)
2230#define VFCHNEN_F VFCHNEN_V(1U)
2231
2232#define DEFAULTQUEUE_S 16
2233#define DEFAULTQUEUE_M 0x3ffU
2234#define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
2235
2236#define VFIP6TWOTUPEN_S 6
2237#define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
2238#define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U)
2239
2240#define VFIP4FOURTUPEN_S 5
2241#define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
2242#define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U)
2243
2244#define VFIP4TWOTUPEN_S 4
2245#define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
2246#define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U)
2247
2248#define KEYINDEX_S 0
2249#define KEYINDEX_M 0xfU
2250#define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
2251
2252#define MAPENABLE_S 31
2253#define MAPENABLE_V(x) ((x) << MAPENABLE_S)
2254#define MAPENABLE_F MAPENABLE_V(1U)
2255
2256#define CHNENABLE_S 30
2257#define CHNENABLE_V(x) ((x) << CHNENABLE_S)
2258#define CHNENABLE_F CHNENABLE_V(1U)
2259
2260#define PRTENABLE_S 29
2261#define PRTENABLE_V(x) ((x) << PRTENABLE_S)
2262#define PRTENABLE_F PRTENABLE_V(1U)
2263
2264#define UDPFOURTUPEN_S 28
2265#define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
2266#define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U)
2267
2268#define IP6FOURTUPEN_S 27
2269#define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
2270#define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U)
2271
2272#define IP6TWOTUPEN_S 26
2273#define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
2274#define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U)
2275
2276#define IP4FOURTUPEN_S 25
2277#define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
2278#define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U)
2279
2280#define IP4TWOTUPEN_S 24
2281#define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
2282#define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U)
2283
2284#define IVFWIDTH_S 20
2285#define IVFWIDTH_M 0xfU
2286#define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
2287#define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
2288
2289#define CH1DEFAULTQUEUE_S 10
2290#define CH1DEFAULTQUEUE_M 0x3ffU
2291#define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
2292#define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
2293
2294#define CH0DEFAULTQUEUE_S 0
2295#define CH0DEFAULTQUEUE_M 0x3ffU
2296#define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
2297#define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
2298
2299#define VFLKPIDX_S 8
2300#define VFLKPIDX_M 0xffU
2301#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
2302
2303#define T6_VFWRADDR_S 8
2304#define T6_VFWRADDR_M 0xffU
2305#define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
2306#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
2307
2308#define TP_RSS_CONFIG_CNG_A 0x7e04
2309#define TP_RSS_SECRET_KEY0_A 0x40
2310#define TP_RSS_PF0_CONFIG_A 0x30
2311#define TP_RSS_PF_MAP_A 0x38
2312#define TP_RSS_PF_MSK_A 0x39
2313
2314#define PF1LKPIDX_S 3
2315
2316#define PF0LKPIDX_M 0x7U
2317
2318#define PF1MSKSIZE_S 4
2319#define PF1MSKSIZE_M 0xfU
2320
2321#define CHNCOUNT3_S 31
2322#define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
2323#define CHNCOUNT3_F CHNCOUNT3_V(1U)
2324
2325#define CHNCOUNT2_S 30
2326#define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
2327#define CHNCOUNT2_F CHNCOUNT2_V(1U)
2328
2329#define CHNCOUNT1_S 29
2330#define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
2331#define CHNCOUNT1_F CHNCOUNT1_V(1U)
2332
2333#define CHNCOUNT0_S 28
2334#define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
2335#define CHNCOUNT0_F CHNCOUNT0_V(1U)
2336
2337#define CHNUNDFLOW3_S 27
2338#define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
2339#define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U)
2340
2341#define CHNUNDFLOW2_S 26
2342#define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
2343#define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U)
2344
2345#define CHNUNDFLOW1_S 25
2346#define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
2347#define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U)
2348
2349#define CHNUNDFLOW0_S 24
2350#define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
2351#define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U)
2352
2353#define RSTCHN3_S 19
2354#define RSTCHN3_V(x) ((x) << RSTCHN3_S)
2355#define RSTCHN3_F RSTCHN3_V(1U)
2356
2357#define RSTCHN2_S 18
2358#define RSTCHN2_V(x) ((x) << RSTCHN2_S)
2359#define RSTCHN2_F RSTCHN2_V(1U)
2360
2361#define RSTCHN1_S 17
2362#define RSTCHN1_V(x) ((x) << RSTCHN1_S)
2363#define RSTCHN1_F RSTCHN1_V(1U)
2364
2365#define RSTCHN0_S 16
2366#define RSTCHN0_V(x) ((x) << RSTCHN0_S)
2367#define RSTCHN0_F RSTCHN0_V(1U)
2368
2369#define UPDVLD_S 15
2370#define UPDVLD_V(x) ((x) << UPDVLD_S)
2371#define UPDVLD_F UPDVLD_V(1U)
2372
2373#define XOFF_S 14
2374#define XOFF_V(x) ((x) << XOFF_S)
2375#define XOFF_F XOFF_V(1U)
2376
2377#define UPDCHN3_S 13
2378#define UPDCHN3_V(x) ((x) << UPDCHN3_S)
2379#define UPDCHN3_F UPDCHN3_V(1U)
2380
2381#define UPDCHN2_S 12
2382#define UPDCHN2_V(x) ((x) << UPDCHN2_S)
2383#define UPDCHN2_F UPDCHN2_V(1U)
2384
2385#define UPDCHN1_S 11
2386#define UPDCHN1_V(x) ((x) << UPDCHN1_S)
2387#define UPDCHN1_F UPDCHN1_V(1U)
2388
2389#define UPDCHN0_S 10
2390#define UPDCHN0_V(x) ((x) << UPDCHN0_S)
2391#define UPDCHN0_F UPDCHN0_V(1U)
2392
2393#define QUEUE_S 0
2394#define QUEUE_M 0x3ffU
2395#define QUEUE_V(x) ((x) << QUEUE_S)
2396#define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
2397
2398#define MPS_TRC_INT_CAUSE_A 0x985c
2399
2400#define MISCPERR_S 8
2401#define MISCPERR_V(x) ((x) << MISCPERR_S)
2402#define MISCPERR_F MISCPERR_V(1U)
2403
2404#define PKTFIFO_S 4
2405#define PKTFIFO_M 0xfU
2406#define PKTFIFO_V(x) ((x) << PKTFIFO_S)
2407
2408#define FILTMEM_S 0
2409#define FILTMEM_M 0xfU
2410#define FILTMEM_V(x) ((x) << FILTMEM_S)
2411
2412#define MPS_CLS_INT_CAUSE_A 0xd028
2413
2414#define HASHSRAM_S 2
2415#define HASHSRAM_V(x) ((x) << HASHSRAM_S)
2416#define HASHSRAM_F HASHSRAM_V(1U)
2417
2418#define MATCHTCAM_S 1
2419#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
2420#define MATCHTCAM_F MATCHTCAM_V(1U)
2421
2422#define MATCHSRAM_S 0
2423#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
2424#define MATCHSRAM_F MATCHSRAM_V(1U)
2425
2426#define MPS_RX_PG_RSV0_A 0x11010
2427#define MPS_RX_PG_RSV4_A 0x11020
2428#define MPS_RX_PERR_INT_CAUSE_A 0x11074
2429#define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
2430#define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
2431
2432#define MPS_CLS_TCAM_Y_L_A 0xf000
2433#define MPS_CLS_TCAM_DATA0_A 0xf000
2434#define MPS_CLS_TCAM_DATA1_A 0xf004
2435
2436#define VIDL_S 16
2437#define VIDL_M 0xffffU
2438#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
2439
2440#define DATALKPTYPE_S 10
2441#define DATALKPTYPE_M 0x3U
2442#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
2443
2444#define DATAPORTNUM_S 12
2445#define DATAPORTNUM_M 0xfU
2446#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)
2447
2448#define DATADIPHIT_S 8
2449#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
2450#define DATADIPHIT_F DATADIPHIT_V(1U)
2451
2452#define DATAVIDH2_S 7
2453#define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)
2454#define DATAVIDH2_F DATAVIDH2_V(1U)
2455
2456#define DATAVIDH1_S 0
2457#define DATAVIDH1_M 0x7fU
2458#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
2459
2460#define USED_S 16
2461#define USED_M 0x7ffU
2462#define USED_G(x) (((x) >> USED_S) & USED_M)
2463
2464#define ALLOC_S 0
2465#define ALLOC_M 0x7ffU
2466#define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)
2467
2468#define T5_USED_S 16
2469#define T5_USED_M 0xfffU
2470#define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)
2471
2472#define T5_ALLOC_S 0
2473#define T5_ALLOC_M 0xfffU
2474#define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)
2475
2476#define DMACH_S 0
2477#define DMACH_M 0xffffU
2478#define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
2479
2480#define MPS_CLS_TCAM_X_L_A 0xf008
2481#define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2482
2483#define CTLCMDTYPE_S 31
2484#define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
2485#define CTLCMDTYPE_F CTLCMDTYPE_V(1U)
2486
2487#define CTLTCAMSEL_S 25
2488#define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
2489
2490#define CTLTCAMINDEX_S 17
2491#define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
2492
2493#define CTLXYBITSEL_S 16
2494#define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
2495
2496#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
2497#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
2498
2499#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
2500#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
2501
2502#define MPS_CLS_SRAM_L_A 0xe000
2503
2504#define T6_MULTILISTEN0_S 26
2505
2506#define T6_SRAM_PRIO3_S 23
2507#define T6_SRAM_PRIO3_M 0x7U
2508#define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
2509
2510#define T6_SRAM_PRIO2_S 20
2511#define T6_SRAM_PRIO2_M 0x7U
2512#define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
2513
2514#define T6_SRAM_PRIO1_S 17
2515#define T6_SRAM_PRIO1_M 0x7U
2516#define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
2517
2518#define T6_SRAM_PRIO0_S 14
2519#define T6_SRAM_PRIO0_M 0x7U
2520#define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
2521
2522#define T6_SRAM_VLD_S 13
2523#define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
2524#define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U)
2525
2526#define T6_REPLICATE_S 12
2527#define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
2528#define T6_REPLICATE_F T6_REPLICATE_V(1U)
2529
2530#define T6_PF_S 9
2531#define T6_PF_M 0x7U
2532#define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
2533
2534#define T6_VF_VALID_S 8
2535#define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
2536#define T6_VF_VALID_F T6_VF_VALID_V(1U)
2537
2538#define T6_VF_S 0
2539#define T6_VF_M 0xffU
2540#define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
2541
2542#define MPS_CLS_SRAM_H_A 0xe004
2543
2544#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
2545#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2546
2547#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
2548#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
2549
2550#define MULTILISTEN0_S 25
2551
2552#define REPLICATE_S 11
2553#define REPLICATE_V(x) ((x) << REPLICATE_S)
2554#define REPLICATE_F REPLICATE_V(1U)
2555
2556#define PF_S 8
2557#define PF_M 0x7U
2558#define PF_G(x) (((x) >> PF_S) & PF_M)
2559
2560#define VF_VALID_S 7
2561#define VF_VALID_V(x) ((x) << VF_VALID_S)
2562#define VF_VALID_F VF_VALID_V(1U)
2563
2564#define VF_S 0
2565#define VF_M 0x7fU
2566#define VF_G(x) (((x) >> VF_S) & VF_M)
2567
2568#define SRAM_PRIO3_S 22
2569#define SRAM_PRIO3_M 0x7U
2570#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
2571
2572#define SRAM_PRIO2_S 19
2573#define SRAM_PRIO2_M 0x7U
2574#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
2575
2576#define SRAM_PRIO1_S 16
2577#define SRAM_PRIO1_M 0x7U
2578#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
2579
2580#define SRAM_PRIO0_S 13
2581#define SRAM_PRIO0_M 0x7U
2582#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
2583
2584#define SRAM_VLD_S 12
2585#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
2586#define SRAM_VLD_F SRAM_VLD_V(1U)
2587
2588#define PORTMAP_S 0
2589#define PORTMAP_M 0xfU
2590#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
2591
2592#define CPL_INTR_CAUSE_A 0x19054
2593
2594#define CIM_OP_MAP_PERR_S 5
2595#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
2596#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
2597
2598#define CIM_OVFL_ERROR_S 4
2599#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
2600#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
2601
2602#define TP_FRAMING_ERROR_S 3
2603#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
2604#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
2605
2606#define SGE_FRAMING_ERROR_S 2
2607#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
2608#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
2609
2610#define CIM_FRAMING_ERROR_S 1
2611#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
2612#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
2613
2614#define ZERO_SWITCH_ERROR_S 0
2615#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
2616#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
2617
2618#define SMB_INT_CAUSE_A 0x19090
2619
2620#define MSTTXFIFOPARINT_S 21
2621#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
2622#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
2623
2624#define MSTRXFIFOPARINT_S 20
2625#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
2626#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
2627
2628#define SLVFIFOPARINT_S 19
2629#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
2630#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
2631
2632#define ULP_RX_INT_CAUSE_A 0x19158
2633#define ULP_RX_ISCSI_LLIMIT_A 0x1915c
2634#define ULP_RX_ISCSI_ULIMIT_A 0x19160
2635#define ULP_RX_ISCSI_TAGMASK_A 0x19164
2636#define ULP_RX_ISCSI_PSZ_A 0x19168
2637#define ULP_RX_TDDP_LLIMIT_A 0x1916c
2638#define ULP_RX_TDDP_ULIMIT_A 0x19170
2639#define ULP_RX_STAG_LLIMIT_A 0x1917c
2640#define ULP_RX_STAG_ULIMIT_A 0x19180
2641#define ULP_RX_RQ_LLIMIT_A 0x19184
2642#define ULP_RX_RQ_ULIMIT_A 0x19188
2643#define ULP_RX_PBL_LLIMIT_A 0x1918c
2644#define ULP_RX_PBL_ULIMIT_A 0x19190
2645#define ULP_RX_CTX_BASE_A 0x19194
2646#define ULP_RX_RQUDP_LLIMIT_A 0x191a4
2647#define ULP_RX_RQUDP_ULIMIT_A 0x191a8
2648#define ULP_RX_LA_CTL_A 0x1923c
2649#define ULP_RX_LA_RDPTR_A 0x19240
2650#define ULP_RX_LA_RDDATA_A 0x19244
2651#define ULP_RX_LA_WRPTR_A 0x19248
2652
2653#define HPZ3_S 24
2654#define HPZ3_V(x) ((x) << HPZ3_S)
2655
2656#define HPZ2_S 16
2657#define HPZ2_V(x) ((x) << HPZ2_S)
2658
2659#define HPZ1_S 8
2660#define HPZ1_V(x) ((x) << HPZ1_S)
2661
2662#define HPZ0_S 0
2663#define HPZ0_V(x) ((x) << HPZ0_S)
2664
2665#define ULP_RX_TDDP_PSZ_A 0x19178
2666
2667
2668#define SF_DATA_A 0x193f8
2669#define SF_OP_A 0x193fc
2670
2671#define SF_BUSY_S 31
2672#define SF_BUSY_V(x) ((x) << SF_BUSY_S)
2673#define SF_BUSY_F SF_BUSY_V(1U)
2674
2675#define SF_LOCK_S 4
2676#define SF_LOCK_V(x) ((x) << SF_LOCK_S)
2677#define SF_LOCK_F SF_LOCK_V(1U)
2678
2679#define SF_CONT_S 3
2680#define SF_CONT_V(x) ((x) << SF_CONT_S)
2681#define SF_CONT_F SF_CONT_V(1U)
2682
2683#define BYTECNT_S 1
2684#define BYTECNT_V(x) ((x) << BYTECNT_S)
2685
2686#define OP_S 0
2687#define OP_V(x) ((x) << OP_S)
2688#define OP_F OP_V(1U)
2689
2690#define PL_PF_INT_CAUSE_A 0x3c0
2691
2692#define PFSW_S 3
2693#define PFSW_V(x) ((x) << PFSW_S)
2694#define PFSW_F PFSW_V(1U)
2695
2696#define PFCIM_S 1
2697#define PFCIM_V(x) ((x) << PFCIM_S)
2698#define PFCIM_F PFCIM_V(1U)
2699
2700#define PL_PF_INT_ENABLE_A 0x3c4
2701#define PL_PF_CTL_A 0x3c8
2702
2703#define PL_WHOAMI_A 0x19400
2704
2705#define SOURCEPF_S 8
2706#define SOURCEPF_M 0x7U
2707#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
2708
2709#define T6_SOURCEPF_S 9
2710#define T6_SOURCEPF_M 0x7U
2711#define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)
2712
2713#define PL_INT_CAUSE_A 0x1940c
2714
2715#define ULP_TX_S 27
2716#define ULP_TX_V(x) ((x) << ULP_TX_S)
2717#define ULP_TX_F ULP_TX_V(1U)
2718
2719#define SGE_S 26
2720#define SGE_V(x) ((x) << SGE_S)
2721#define SGE_F SGE_V(1U)
2722
2723#define CPL_SWITCH_S 24
2724#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
2725#define CPL_SWITCH_F CPL_SWITCH_V(1U)
2726
2727#define ULP_RX_S 23
2728#define ULP_RX_V(x) ((x) << ULP_RX_S)
2729#define ULP_RX_F ULP_RX_V(1U)
2730
2731#define PM_RX_S 22
2732#define PM_RX_V(x) ((x) << PM_RX_S)
2733#define PM_RX_F PM_RX_V(1U)
2734
2735#define PM_TX_S 21
2736#define PM_TX_V(x) ((x) << PM_TX_S)
2737#define PM_TX_F PM_TX_V(1U)
2738
2739#define MA_S 20
2740#define MA_V(x) ((x) << MA_S)
2741#define MA_F MA_V(1U)
2742
2743#define TP_S 19
2744#define TP_V(x) ((x) << TP_S)
2745#define TP_F TP_V(1U)
2746
2747#define LE_S 18
2748#define LE_V(x) ((x) << LE_S)
2749#define LE_F LE_V(1U)
2750
2751#define EDC1_S 17
2752#define EDC1_V(x) ((x) << EDC1_S)
2753#define EDC1_F EDC1_V(1U)
2754
2755#define EDC0_S 16
2756#define EDC0_V(x) ((x) << EDC0_S)
2757#define EDC0_F EDC0_V(1U)
2758
2759#define MC_S 15
2760#define MC_V(x) ((x) << MC_S)
2761#define MC_F MC_V(1U)
2762
2763#define PCIE_S 14
2764#define PCIE_V(x) ((x) << PCIE_S)
2765#define PCIE_F PCIE_V(1U)
2766
2767#define XGMAC_KR1_S 12
2768#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
2769#define XGMAC_KR1_F XGMAC_KR1_V(1U)
2770
2771#define XGMAC_KR0_S 11
2772#define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
2773#define XGMAC_KR0_F XGMAC_KR0_V(1U)
2774
2775#define XGMAC1_S 10
2776#define XGMAC1_V(x) ((x) << XGMAC1_S)
2777#define XGMAC1_F XGMAC1_V(1U)
2778
2779#define XGMAC0_S 9
2780#define XGMAC0_V(x) ((x) << XGMAC0_S)
2781#define XGMAC0_F XGMAC0_V(1U)
2782
2783#define SMB_S 8
2784#define SMB_V(x) ((x) << SMB_S)
2785#define SMB_F SMB_V(1U)
2786
2787#define SF_S 7
2788#define SF_V(x) ((x) << SF_S)
2789#define SF_F SF_V(1U)
2790
2791#define PL_S 6
2792#define PL_V(x) ((x) << PL_S)
2793#define PL_F PL_V(1U)
2794
2795#define NCSI_S 5
2796#define NCSI_V(x) ((x) << NCSI_S)
2797#define NCSI_F NCSI_V(1U)
2798
2799#define MPS_S 4
2800#define MPS_V(x) ((x) << MPS_S)
2801#define MPS_F MPS_V(1U)
2802
2803#define CIM_S 0
2804#define CIM_V(x) ((x) << CIM_S)
2805#define CIM_F CIM_V(1U)
2806
2807#define MC1_S 31
2808#define MC1_V(x) ((x) << MC1_S)
2809#define MC1_F MC1_V(1U)
2810
2811#define PL_INT_ENABLE_A 0x19410
2812#define PL_INT_MAP0_A 0x19414
2813#define PL_RST_A 0x19428
2814
2815#define PIORST_S 1
2816#define PIORST_V(x) ((x) << PIORST_S)
2817#define PIORST_F PIORST_V(1U)
2818
2819#define PIORSTMODE_S 0
2820#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
2821#define PIORSTMODE_F PIORSTMODE_V(1U)
2822
2823#define PL_PL_INT_CAUSE_A 0x19430
2824
2825#define FATALPERR_S 4
2826#define FATALPERR_V(x) ((x) << FATALPERR_S)
2827#define FATALPERR_F FATALPERR_V(1U)
2828
2829#define PERRVFID_S 0
2830#define PERRVFID_V(x) ((x) << PERRVFID_S)
2831#define PERRVFID_F PERRVFID_V(1U)
2832
2833#define PL_REV_A 0x1943c
2834
2835#define REV_S 0
2836#define REV_M 0xfU
2837#define REV_V(x) ((x) << REV_S)
2838#define REV_G(x) (((x) >> REV_S) & REV_M)
2839
2840#define T6_UNKNOWNCMD_S 3
2841#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
2842#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
2843
2844#define T6_LIP0_S 2
2845#define T6_LIP0_V(x) ((x) << T6_LIP0_S)
2846#define T6_LIP0_F T6_LIP0_V(1U)
2847
2848#define T6_LIPMISS_S 1
2849#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
2850#define T6_LIPMISS_F T6_LIPMISS_V(1U)
2851
2852#define LE_DB_CONFIG_A 0x19c04
2853#define LE_DB_SERVER_INDEX_A 0x19c18
2854#define LE_DB_SRVR_START_INDEX_A 0x19c18
2855#define LE_DB_ACT_CNT_IPV4_A 0x19c20
2856#define LE_DB_ACT_CNT_IPV6_A 0x19c24
2857#define LE_DB_HASH_TID_BASE_A 0x19c30
2858#define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
2859#define LE_DB_INT_CAUSE_A 0x19c3c
2860#define LE_DB_TID_HASHBASE_A 0x19df8
2861#define T6_LE_DB_HASH_TID_BASE_A 0x19df8
2862
2863#define HASHEN_S 20
2864#define HASHEN_V(x) ((x) << HASHEN_S)
2865#define HASHEN_F HASHEN_V(1U)
2866
2867#define ASLIPCOMPEN_S 17
2868#define ASLIPCOMPEN_V(x) ((x) << ASLIPCOMPEN_S)
2869#define ASLIPCOMPEN_F ASLIPCOMPEN_V(1U)
2870
2871#define REQQPARERR_S 16
2872#define REQQPARERR_V(x) ((x) << REQQPARERR_S)
2873#define REQQPARERR_F REQQPARERR_V(1U)
2874
2875#define UNKNOWNCMD_S 15
2876#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
2877#define UNKNOWNCMD_F UNKNOWNCMD_V(1U)
2878
2879#define PARITYERR_S 6
2880#define PARITYERR_V(x) ((x) << PARITYERR_S)
2881#define PARITYERR_F PARITYERR_V(1U)
2882
2883#define LIPMISS_S 5
2884#define LIPMISS_V(x) ((x) << LIPMISS_S)
2885#define LIPMISS_F LIPMISS_V(1U)
2886
2887#define LIP0_S 4
2888#define LIP0_V(x) ((x) << LIP0_S)
2889#define LIP0_F LIP0_V(1U)
2890
2891#define BASEADDR_S 3
2892#define BASEADDR_M 0x1fffffffU
2893#define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M)
2894
2895#define TCAMINTPERR_S 13
2896#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
2897#define TCAMINTPERR_F TCAMINTPERR_V(1U)
2898
2899#define SSRAMINTPERR_S 10
2900#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
2901#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
2902
2903#define NCSI_INT_CAUSE_A 0x1a0d8
2904
2905#define CIM_DM_PRTY_ERR_S 8
2906#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
2907#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)
2908
2909#define MPS_DM_PRTY_ERR_S 7
2910#define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
2911#define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U)
2912
2913#define TXFIFO_PRTY_ERR_S 1
2914#define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
2915#define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U)
2916
2917#define RXFIFO_PRTY_ERR_S 0
2918#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
2919#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)
2920
2921#define XGMAC_PORT_CFG2_A 0x1018
2922
2923#define PATEN_S 18
2924#define PATEN_V(x) ((x) << PATEN_S)
2925#define PATEN_F PATEN_V(1U)
2926
2927#define MAGICEN_S 17
2928#define MAGICEN_V(x) ((x) << MAGICEN_S)
2929#define MAGICEN_F MAGICEN_V(1U)
2930
2931#define XGMAC_PORT_MAGIC_MACID_LO 0x1024
2932#define XGMAC_PORT_MAGIC_MACID_HI 0x1028
2933
2934#define XGMAC_PORT_EPIO_DATA0_A 0x10c0
2935#define XGMAC_PORT_EPIO_DATA1_A 0x10c4
2936#define XGMAC_PORT_EPIO_DATA2_A 0x10c8
2937#define XGMAC_PORT_EPIO_DATA3_A 0x10cc
2938#define XGMAC_PORT_EPIO_OP_A 0x10d0
2939
2940#define EPIOWR_S 8
2941#define EPIOWR_V(x) ((x) << EPIOWR_S)
2942#define EPIOWR_F EPIOWR_V(1U)
2943
2944#define ADDRESS_S 0
2945#define ADDRESS_V(x) ((x) << ADDRESS_S)
2946
2947#define MAC_PORT_INT_CAUSE_A 0x8dc
2948#define XGMAC_PORT_INT_CAUSE_A 0x10dc
2949
2950#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
2951
2952#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
2953#define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
2954
2955#define TX_MOD_QUEUE_REQ_MAP_S 0
2956#define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
2957
2958#define TX_MODQ_WEIGHT3_S 24
2959#define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
2960
2961#define TX_MODQ_WEIGHT2_S 16
2962#define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
2963
2964#define TX_MODQ_WEIGHT1_S 8
2965#define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
2966
2967#define TX_MODQ_WEIGHT0_S 0
2968#define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
2969
2970#define TP_TX_SCHED_HDR_A 0x23
2971#define TP_TX_SCHED_FIFO_A 0x24
2972#define TP_TX_SCHED_PCMD_A 0x25
2973
2974#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2975#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
2976
2977#define T5_PORT0_BASE 0x30000
2978#define T5_PORT_STRIDE 0x4000
2979#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
2980#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
2981
2982#define MC_0_BASE_ADDR 0x40000
2983#define MC_1_BASE_ADDR 0x48000
2984#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
2985#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
2986
2987#define MC_P_BIST_CMD_A 0x41400
2988#define MC_P_BIST_CMD_ADDR_A 0x41404
2989#define MC_P_BIST_CMD_LEN_A 0x41408
2990#define MC_P_BIST_DATA_PATTERN_A 0x4140c
2991#define MC_P_BIST_STATUS_RDATA_A 0x41488
2992
2993#define EDC_T50_BASE_ADDR 0x50000
2994
2995#define EDC_H_BIST_CMD_A 0x50004
2996#define EDC_H_BIST_CMD_ADDR_A 0x50008
2997#define EDC_H_BIST_CMD_LEN_A 0x5000c
2998#define EDC_H_BIST_DATA_PATTERN_A 0x50010
2999#define EDC_H_BIST_STATUS_RDATA_A 0x50028
3000
3001#define EDC_H_ECC_ERR_ADDR_A 0x50084
3002#define EDC_T51_BASE_ADDR 0x50800
3003
3004#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
3005#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
3006
3007#define PL_VF_REV_A 0x4
3008#define PL_VF_WHOAMI_A 0x0
3009#define PL_VF_REVISION_A 0x8
3010
3011
3012#define CIM_HOST_ACC_CTRL_A 0x7b50
3013#define CIM_HOST_ACC_DATA_A 0x7b54
3014#define UP_UP_DBG_LA_CFG_A 0x140
3015#define UP_UP_DBG_LA_DATA_A 0x144
3016
3017#define HOSTBUSY_S 17
3018#define HOSTBUSY_V(x) ((x) << HOSTBUSY_S)
3019#define HOSTBUSY_F HOSTBUSY_V(1U)
3020
3021#define HOSTWRITE_S 16
3022#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
3023#define HOSTWRITE_F HOSTWRITE_V(1U)
3024
3025#define CIM_IBQ_DBG_CFG_A 0x7b60
3026
3027#define IBQDBGADDR_S 16
3028#define IBQDBGADDR_M 0xfffU
3029#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
3030#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
3031
3032#define IBQDBGBUSY_S 1
3033#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
3034#define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
3035
3036#define IBQDBGEN_S 0
3037#define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
3038#define IBQDBGEN_F IBQDBGEN_V(1U)
3039
3040#define CIM_OBQ_DBG_CFG_A 0x7b64
3041
3042#define OBQDBGADDR_S 16
3043#define OBQDBGADDR_M 0xfffU
3044#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
3045#define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)
3046
3047#define OBQDBGBUSY_S 1
3048#define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)
3049#define OBQDBGBUSY_F OBQDBGBUSY_V(1U)
3050
3051#define OBQDBGEN_S 0
3052#define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)
3053#define OBQDBGEN_F OBQDBGEN_V(1U)
3054
3055#define CIM_IBQ_DBG_DATA_A 0x7b68
3056#define CIM_OBQ_DBG_DATA_A 0x7b6c
3057#define CIM_DEBUGCFG_A 0x7b70
3058#define CIM_DEBUGSTS_A 0x7b74
3059
3060#define POLADBGRDPTR_S 23
3061#define POLADBGRDPTR_M 0x1ffU
3062#define POLADBGRDPTR_V(x) ((x) << POLADBGRDPTR_S)
3063
3064#define POLADBGWRPTR_S 16
3065#define POLADBGWRPTR_M 0x1ffU
3066#define POLADBGWRPTR_G(x) (((x) >> POLADBGWRPTR_S) & POLADBGWRPTR_M)
3067
3068#define PILADBGRDPTR_S 14
3069#define PILADBGRDPTR_M 0x1ffU
3070#define PILADBGRDPTR_V(x) ((x) << PILADBGRDPTR_S)
3071
3072#define PILADBGWRPTR_S 0
3073#define PILADBGWRPTR_M 0x1ffU
3074#define PILADBGWRPTR_G(x) (((x) >> PILADBGWRPTR_S) & PILADBGWRPTR_M)
3075
3076#define LADBGEN_S 12
3077#define LADBGEN_V(x) ((x) << LADBGEN_S)
3078#define LADBGEN_F LADBGEN_V(1U)
3079
3080#define CIM_PO_LA_DEBUGDATA_A 0x7b78
3081#define CIM_PI_LA_DEBUGDATA_A 0x7b7c
3082#define CIM_PO_LA_MADEBUGDATA_A 0x7b80
3083#define CIM_PI_LA_MADEBUGDATA_A 0x7b84
3084
3085#define UPDBGLARDEN_S 1
3086#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
3087#define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
3088
3089#define UPDBGLAEN_S 0
3090#define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S)
3091#define UPDBGLAEN_F UPDBGLAEN_V(1U)
3092
3093#define UPDBGLARDPTR_S 2
3094#define UPDBGLARDPTR_M 0xfffU
3095#define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S)
3096
3097#define UPDBGLAWRPTR_S 16
3098#define UPDBGLAWRPTR_M 0xfffU
3099#define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
3100
3101#define UPDBGLACAPTPCONLY_S 30
3102#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)
3103#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
3104
3105#define CIM_QUEUE_CONFIG_REF_A 0x7b48
3106#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
3107
3108#define CIMQSIZE_S 24
3109#define CIMQSIZE_M 0x3fU
3110#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
3111
3112#define CIMQBASE_S 16
3113#define CIMQBASE_M 0x3fU
3114#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
3115
3116#define QUEFULLTHRSH_S 0
3117#define QUEFULLTHRSH_M 0x1ffU
3118#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
3119
3120#define UP_IBQ_0_RDADDR_A 0x10
3121#define UP_IBQ_0_SHADOW_RDADDR_A 0x280
3122#define UP_OBQ_0_REALADDR_A 0x104
3123#define UP_OBQ_0_SHADOW_REALADDR_A 0x394
3124
3125#define IBQRDADDR_S 0
3126#define IBQRDADDR_M 0x1fffU
3127#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
3128
3129#define IBQWRADDR_S 0
3130#define IBQWRADDR_M 0x1fffU
3131#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
3132
3133#define QUERDADDR_S 0
3134#define QUERDADDR_M 0x7fffU
3135#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
3136
3137#define QUEREMFLITS_S 0
3138#define QUEREMFLITS_M 0x7ffU
3139#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
3140
3141#define QUEEOPCNT_S 16
3142#define QUEEOPCNT_M 0xfffU
3143#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
3144
3145#define QUESOPCNT_S 0
3146#define QUESOPCNT_M 0xfffU
3147#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
3148
3149#define OBQSELECT_S 4
3150#define OBQSELECT_V(x) ((x) << OBQSELECT_S)
3151#define OBQSELECT_F OBQSELECT_V(1U)
3152
3153#define IBQSELECT_S 3
3154#define IBQSELECT_V(x) ((x) << IBQSELECT_S)
3155#define IBQSELECT_F IBQSELECT_V(1U)
3156
3157#define QUENUMSELECT_S 0
3158#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
3159
3160#endif
3161