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33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
38
39
40struct e1000_hw;
41struct e1000_hw_stats;
42
43
44
45typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_ce4100,
56 e1000_82546_rev_3,
57 e1000_82541,
58 e1000_82541_rev_2,
59 e1000_82547,
60 e1000_82547_rev_2,
61 e1000_num_macs
62} e1000_mac_type;
63
64typedef enum {
65 e1000_eeprom_uninitialized = 0,
66 e1000_eeprom_spi,
67 e1000_eeprom_microwire,
68 e1000_eeprom_flash,
69 e1000_eeprom_none,
70 e1000_num_eeprom_types
71} e1000_eeprom_type;
72
73
74typedef enum {
75 e1000_media_type_copper = 0,
76 e1000_media_type_fiber = 1,
77 e1000_media_type_internal_serdes = 2,
78 e1000_num_media_types
79} e1000_media_type;
80
81typedef enum {
82 e1000_10_half = 0,
83 e1000_10_full = 1,
84 e1000_100_half = 2,
85 e1000_100_full = 3
86} e1000_speed_duplex_type;
87
88
89typedef enum {
90 E1000_FC_NONE = 0,
91 E1000_FC_RX_PAUSE = 1,
92 E1000_FC_TX_PAUSE = 2,
93 E1000_FC_FULL = 3,
94 E1000_FC_DEFAULT = 0xFF
95} e1000_fc_type;
96
97struct e1000_shadow_ram {
98 u16 eeprom_word;
99 bool modified;
100};
101
102
103typedef enum {
104 e1000_bus_type_unknown = 0,
105 e1000_bus_type_pci,
106 e1000_bus_type_pcix,
107 e1000_bus_type_reserved
108} e1000_bus_type;
109
110
111typedef enum {
112 e1000_bus_speed_unknown = 0,
113 e1000_bus_speed_33,
114 e1000_bus_speed_66,
115 e1000_bus_speed_100,
116 e1000_bus_speed_120,
117 e1000_bus_speed_133,
118 e1000_bus_speed_reserved
119} e1000_bus_speed;
120
121
122typedef enum {
123 e1000_bus_width_unknown = 0,
124 e1000_bus_width_32,
125 e1000_bus_width_64,
126 e1000_bus_width_reserved
127} e1000_bus_width;
128
129
130typedef enum {
131 e1000_cable_length_50 = 0,
132 e1000_cable_length_50_80,
133 e1000_cable_length_80_110,
134 e1000_cable_length_110_140,
135 e1000_cable_length_140,
136 e1000_cable_length_undefined = 0xFF
137} e1000_cable_length;
138
139typedef enum {
140 e1000_gg_cable_length_60 = 0,
141 e1000_gg_cable_length_60_115 = 1,
142 e1000_gg_cable_length_115_150 = 2,
143 e1000_gg_cable_length_150 = 4
144} e1000_gg_cable_length;
145
146typedef enum {
147 e1000_igp_cable_length_10 = 10,
148 e1000_igp_cable_length_20 = 20,
149 e1000_igp_cable_length_30 = 30,
150 e1000_igp_cable_length_40 = 40,
151 e1000_igp_cable_length_50 = 50,
152 e1000_igp_cable_length_60 = 60,
153 e1000_igp_cable_length_70 = 70,
154 e1000_igp_cable_length_80 = 80,
155 e1000_igp_cable_length_90 = 90,
156 e1000_igp_cable_length_100 = 100,
157 e1000_igp_cable_length_110 = 110,
158 e1000_igp_cable_length_115 = 115,
159 e1000_igp_cable_length_120 = 120,
160 e1000_igp_cable_length_130 = 130,
161 e1000_igp_cable_length_140 = 140,
162 e1000_igp_cable_length_150 = 150,
163 e1000_igp_cable_length_160 = 160,
164 e1000_igp_cable_length_170 = 170,
165 e1000_igp_cable_length_180 = 180
166} e1000_igp_cable_length;
167
168typedef enum {
169 e1000_10bt_ext_dist_enable_normal = 0,
170 e1000_10bt_ext_dist_enable_lower,
171 e1000_10bt_ext_dist_enable_undefined = 0xFF
172} e1000_10bt_ext_dist_enable;
173
174typedef enum {
175 e1000_rev_polarity_normal = 0,
176 e1000_rev_polarity_reversed,
177 e1000_rev_polarity_undefined = 0xFF
178} e1000_rev_polarity;
179
180typedef enum {
181 e1000_downshift_normal = 0,
182 e1000_downshift_activated,
183 e1000_downshift_undefined = 0xFF
184} e1000_downshift;
185
186typedef enum {
187 e1000_smart_speed_default = 0,
188 e1000_smart_speed_on,
189 e1000_smart_speed_off
190} e1000_smart_speed;
191
192typedef enum {
193 e1000_polarity_reversal_enabled = 0,
194 e1000_polarity_reversal_disabled,
195 e1000_polarity_reversal_undefined = 0xFF
196} e1000_polarity_reversal;
197
198typedef enum {
199 e1000_auto_x_mode_manual_mdi = 0,
200 e1000_auto_x_mode_manual_mdix,
201 e1000_auto_x_mode_auto1,
202 e1000_auto_x_mode_auto2,
203 e1000_auto_x_mode_undefined = 0xFF
204} e1000_auto_x_mode;
205
206typedef enum {
207 e1000_1000t_rx_status_not_ok = 0,
208 e1000_1000t_rx_status_ok,
209 e1000_1000t_rx_status_undefined = 0xFF
210} e1000_1000t_rx_status;
211
212typedef enum {
213 e1000_phy_m88 = 0,
214 e1000_phy_igp,
215 e1000_phy_8211,
216 e1000_phy_8201,
217 e1000_phy_undefined = 0xFF
218} e1000_phy_type;
219
220typedef enum {
221 e1000_ms_hw_default = 0,
222 e1000_ms_force_master,
223 e1000_ms_force_slave,
224 e1000_ms_auto
225} e1000_ms_type;
226
227typedef enum {
228 e1000_ffe_config_enabled = 0,
229 e1000_ffe_config_active,
230 e1000_ffe_config_blocked
231} e1000_ffe_config;
232
233typedef enum {
234 e1000_dsp_config_disabled = 0,
235 e1000_dsp_config_enabled,
236 e1000_dsp_config_activated,
237 e1000_dsp_config_undefined = 0xFF
238} e1000_dsp_config;
239
240struct e1000_phy_info {
241 e1000_cable_length cable_length;
242 e1000_10bt_ext_dist_enable extended_10bt_distance;
243 e1000_rev_polarity cable_polarity;
244 e1000_downshift downshift;
245 e1000_polarity_reversal polarity_correction;
246 e1000_auto_x_mode mdix_mode;
247 e1000_1000t_rx_status local_rx;
248 e1000_1000t_rx_status remote_rx;
249};
250
251struct e1000_phy_stats {
252 u32 idle_errors;
253 u32 receive_errors;
254};
255
256struct e1000_eeprom_info {
257 e1000_eeprom_type type;
258 u16 word_size;
259 u16 opcode_bits;
260 u16 address_bits;
261 u16 delay_usec;
262 u16 page_size;
263};
264
265
266#define E1000_HOST_IF_MAX_SIZE 2048
267
268typedef enum {
269 e1000_byte_align = 0,
270 e1000_word_align = 1,
271 e1000_dword_align = 2
272} e1000_align_type;
273
274
275#define E1000_SUCCESS 0
276#define E1000_ERR_EEPROM 1
277#define E1000_ERR_PHY 2
278#define E1000_ERR_CONFIG 3
279#define E1000_ERR_PARAM 4
280#define E1000_ERR_MAC_TYPE 5
281#define E1000_ERR_PHY_TYPE 6
282#define E1000_ERR_RESET 9
283#define E1000_ERR_MASTER_REQUESTS_PENDING 10
284#define E1000_ERR_HOST_INTERFACE_COMMAND 11
285#define E1000_BLK_PHY_RESET 12
286
287#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
288 (((_value) & 0xff00) >> 8))
289
290
291
292s32 e1000_reset_hw(struct e1000_hw *hw);
293s32 e1000_init_hw(struct e1000_hw *hw);
294s32 e1000_set_mac_type(struct e1000_hw *hw);
295void e1000_set_media_type(struct e1000_hw *hw);
296
297
298s32 e1000_setup_link(struct e1000_hw *hw);
299s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
300void e1000_config_collision_dist(struct e1000_hw *hw);
301s32 e1000_check_for_link(struct e1000_hw *hw);
302s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
303s32 e1000_force_mac_fc(struct e1000_hw *hw);
304
305
306s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
307s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
308s32 e1000_phy_hw_reset(struct e1000_hw *hw);
309s32 e1000_phy_reset(struct e1000_hw *hw);
310s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
311s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
312
313
314s32 e1000_init_eeprom_params(struct e1000_hw *hw);
315
316
317u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
318
319#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
320#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
321
322#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
323#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
324#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
325#define E1000_MNG_IAMT_MODE 0x3
326#define E1000_MNG_ICH_IAMT_MODE 0x2
327#define E1000_IAMT_SIGNATURE 0x544D4149
328
329#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1
330#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2
331#define E1000_VFTA_ENTRY_SHIFT 0x5
332#define E1000_VFTA_ENTRY_MASK 0x7F
333#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
334
335struct e1000_host_mng_command_header {
336 u8 command_id;
337 u8 checksum;
338 u16 reserved1;
339 u16 reserved2;
340 u16 command_length;
341};
342
343struct e1000_host_mng_command_info {
344 struct e1000_host_mng_command_header command_header;
345 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
346};
347#ifdef __BIG_ENDIAN
348struct e1000_host_mng_dhcp_cookie {
349 u32 signature;
350 u16 vlan_id;
351 u8 reserved0;
352 u8 status;
353 u32 reserved1;
354 u8 checksum;
355 u8 reserved3;
356 u16 reserved2;
357};
358#else
359struct e1000_host_mng_dhcp_cookie {
360 u32 signature;
361 u8 status;
362 u8 reserved0;
363 u16 vlan_id;
364 u32 reserved1;
365 u16 reserved2;
366 u8 reserved3;
367 u8 checksum;
368};
369#endif
370
371bool e1000_check_mng_mode(struct e1000_hw *hw);
372s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
373s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
374s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
375s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
376s32 e1000_read_mac_addr(struct e1000_hw *hw);
377
378
379u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
380void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
381void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);
382void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
383
384
385s32 e1000_setup_led(struct e1000_hw *hw);
386s32 e1000_cleanup_led(struct e1000_hw *hw);
387s32 e1000_led_on(struct e1000_hw *hw);
388s32 e1000_led_off(struct e1000_hw *hw);
389s32 e1000_blink_led_start(struct e1000_hw *hw);
390
391
392
393
394void e1000_reset_adaptive(struct e1000_hw *hw);
395void e1000_update_adaptive(struct e1000_hw *hw);
396void e1000_get_bus_info(struct e1000_hw *hw);
397void e1000_pci_set_mwi(struct e1000_hw *hw);
398void e1000_pci_clear_mwi(struct e1000_hw *hw);
399void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
400int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
401
402void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
403
404#define E1000_READ_REG_IO(a, reg) \
405 e1000_read_reg_io((a), E1000_##reg)
406#define E1000_WRITE_REG_IO(a, reg, val) \
407 e1000_write_reg_io((a), E1000_##reg, val)
408
409
410#define E1000_DEV_ID_82542 0x1000
411#define E1000_DEV_ID_82543GC_FIBER 0x1001
412#define E1000_DEV_ID_82543GC_COPPER 0x1004
413#define E1000_DEV_ID_82544EI_COPPER 0x1008
414#define E1000_DEV_ID_82544EI_FIBER 0x1009
415#define E1000_DEV_ID_82544GC_COPPER 0x100C
416#define E1000_DEV_ID_82544GC_LOM 0x100D
417#define E1000_DEV_ID_82540EM 0x100E
418#define E1000_DEV_ID_82540EM_LOM 0x1015
419#define E1000_DEV_ID_82540EP_LOM 0x1016
420#define E1000_DEV_ID_82540EP 0x1017
421#define E1000_DEV_ID_82540EP_LP 0x101E
422#define E1000_DEV_ID_82545EM_COPPER 0x100F
423#define E1000_DEV_ID_82545EM_FIBER 0x1011
424#define E1000_DEV_ID_82545GM_COPPER 0x1026
425#define E1000_DEV_ID_82545GM_FIBER 0x1027
426#define E1000_DEV_ID_82545GM_SERDES 0x1028
427#define E1000_DEV_ID_82546EB_COPPER 0x1010
428#define E1000_DEV_ID_82546EB_FIBER 0x1012
429#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
430#define E1000_DEV_ID_82541EI 0x1013
431#define E1000_DEV_ID_82541EI_MOBILE 0x1018
432#define E1000_DEV_ID_82541ER_LOM 0x1014
433#define E1000_DEV_ID_82541ER 0x1078
434#define E1000_DEV_ID_82547GI 0x1075
435#define E1000_DEV_ID_82541GI 0x1076
436#define E1000_DEV_ID_82541GI_MOBILE 0x1077
437#define E1000_DEV_ID_82541GI_LF 0x107C
438#define E1000_DEV_ID_82546GB_COPPER 0x1079
439#define E1000_DEV_ID_82546GB_FIBER 0x107A
440#define E1000_DEV_ID_82546GB_SERDES 0x107B
441#define E1000_DEV_ID_82546GB_PCIE 0x108A
442#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
443#define E1000_DEV_ID_82547EI 0x1019
444#define E1000_DEV_ID_82547EI_MOBILE 0x101A
445#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
446#define E1000_DEV_ID_INTEL_CE4100_GBE 0x2E6E
447
448#define NODE_ADDRESS_SIZE 6
449
450
451#define MAC_DECODE_SIZE (128 * 1024)
452
453#define E1000_82542_2_0_REV_ID 2
454#define E1000_82542_2_1_REV_ID 3
455#define E1000_REVISION_0 0
456#define E1000_REVISION_1 1
457#define E1000_REVISION_2 2
458#define E1000_REVISION_3 3
459
460#define SPEED_10 10
461#define SPEED_100 100
462#define SPEED_1000 1000
463#define HALF_DUPLEX 1
464#define FULL_DUPLEX 2
465
466
467#define ENET_HEADER_SIZE 14
468#define MINIMUM_ETHERNET_FRAME_SIZE 64
469#define ETHERNET_FCS_SIZE 4
470#define MINIMUM_ETHERNET_PACKET_SIZE \
471 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
472#define CRC_LENGTH ETHERNET_FCS_SIZE
473#define MAX_JUMBO_FRAME_SIZE 0x3F00
474
475
476#define VLAN_TAG_SIZE 4
477
478
479#define ETHERNET_IEEE_VLAN_TYPE 0x8100
480#define ETHERNET_IP_TYPE 0x0800
481#define ETHERNET_ARP_TYPE 0x0806
482
483
484#define IP_PROTOCOL_TCP 6
485#define IP_PROTOCOL_UDP 0x11
486
487
488
489
490
491
492#define POLL_IMS_ENABLE_MASK ( \
493 E1000_IMS_RXDMT0 | \
494 E1000_IMS_RXSEQ)
495
496
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502
503
504#define IMS_ENABLE_MASK ( \
505 E1000_IMS_RXT0 | \
506 E1000_IMS_TXDW | \
507 E1000_IMS_RXDMT0 | \
508 E1000_IMS_RXSEQ | \
509 E1000_IMS_LSC)
510
511
512
513
514
515
516#define E1000_RAR_ENTRIES 15
517
518#define MIN_NUMBER_OF_DESCRIPTORS 8
519#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
520
521
522struct e1000_rx_desc {
523 __le64 buffer_addr;
524 __le16 length;
525 __le16 csum;
526 u8 status;
527 u8 errors;
528 __le16 special;
529};
530
531
532union e1000_rx_desc_extended {
533 struct {
534 __le64 buffer_addr;
535 __le64 reserved;
536 } read;
537 struct {
538 struct {
539 __le32 mrq;
540 union {
541 __le32 rss;
542 struct {
543 __le16 ip_id;
544 __le16 csum;
545 } csum_ip;
546 } hi_dword;
547 } lower;
548 struct {
549 __le32 status_error;
550 __le16 length;
551 __le16 vlan;
552 } upper;
553 } wb;
554};
555
556#define MAX_PS_BUFFERS 4
557
558union e1000_rx_desc_packet_split {
559 struct {
560
561 __le64 buffer_addr[MAX_PS_BUFFERS];
562 } read;
563 struct {
564 struct {
565 __le32 mrq;
566 union {
567 __le32 rss;
568 struct {
569 __le16 ip_id;
570 __le16 csum;
571 } csum_ip;
572 } hi_dword;
573 } lower;
574 struct {
575 __le32 status_error;
576 __le16 length0;
577 __le16 vlan;
578 } middle;
579 struct {
580 __le16 header_status;
581 __le16 length[3];
582 } upper;
583 __le64 reserved;
584 } wb;
585};
586
587
588#define E1000_RXD_STAT_DD 0x01
589#define E1000_RXD_STAT_EOP 0x02
590#define E1000_RXD_STAT_IXSM 0x04
591#define E1000_RXD_STAT_VP 0x08
592#define E1000_RXD_STAT_UDPCS 0x10
593#define E1000_RXD_STAT_TCPCS 0x20
594#define E1000_RXD_STAT_IPCS 0x40
595#define E1000_RXD_STAT_PIF 0x80
596#define E1000_RXD_STAT_IPIDV 0x200
597#define E1000_RXD_STAT_UDPV 0x400
598#define E1000_RXD_STAT_ACK 0x8000
599#define E1000_RXD_ERR_CE 0x01
600#define E1000_RXD_ERR_SE 0x02
601#define E1000_RXD_ERR_SEQ 0x04
602#define E1000_RXD_ERR_CXE 0x10
603#define E1000_RXD_ERR_TCPE 0x20
604#define E1000_RXD_ERR_IPE 0x40
605#define E1000_RXD_ERR_RXE 0x80
606#define E1000_RXD_SPC_VLAN_MASK 0x0FFF
607#define E1000_RXD_SPC_PRI_MASK 0xE000
608#define E1000_RXD_SPC_PRI_SHIFT 13
609#define E1000_RXD_SPC_CFI_MASK 0x1000
610#define E1000_RXD_SPC_CFI_SHIFT 12
611
612#define E1000_RXDEXT_STATERR_CE 0x01000000
613#define E1000_RXDEXT_STATERR_SE 0x02000000
614#define E1000_RXDEXT_STATERR_SEQ 0x04000000
615#define E1000_RXDEXT_STATERR_CXE 0x10000000
616#define E1000_RXDEXT_STATERR_TCPE 0x20000000
617#define E1000_RXDEXT_STATERR_IPE 0x40000000
618#define E1000_RXDEXT_STATERR_RXE 0x80000000
619
620#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
621#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
622
623
624#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
625 E1000_RXD_ERR_CE | \
626 E1000_RXD_ERR_SE | \
627 E1000_RXD_ERR_SEQ | \
628 E1000_RXD_ERR_CXE | \
629 E1000_RXD_ERR_RXE)
630
631
632#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
633 E1000_RXDEXT_STATERR_CE | \
634 E1000_RXDEXT_STATERR_SE | \
635 E1000_RXDEXT_STATERR_SEQ | \
636 E1000_RXDEXT_STATERR_CXE | \
637 E1000_RXDEXT_STATERR_RXE)
638
639
640struct e1000_tx_desc {
641 __le64 buffer_addr;
642 union {
643 __le32 data;
644 struct {
645 __le16 length;
646 u8 cso;
647 u8 cmd;
648 } flags;
649 } lower;
650 union {
651 __le32 data;
652 struct {
653 u8 status;
654 u8 css;
655 __le16 special;
656 } fields;
657 } upper;
658};
659
660
661#define E1000_TXD_DTYP_D 0x00100000
662#define E1000_TXD_DTYP_C 0x00000000
663#define E1000_TXD_POPTS_IXSM 0x01
664#define E1000_TXD_POPTS_TXSM 0x02
665#define E1000_TXD_CMD_EOP 0x01000000
666#define E1000_TXD_CMD_IFCS 0x02000000
667#define E1000_TXD_CMD_IC 0x04000000
668#define E1000_TXD_CMD_RS 0x08000000
669#define E1000_TXD_CMD_RPS 0x10000000
670#define E1000_TXD_CMD_DEXT 0x20000000
671#define E1000_TXD_CMD_VLE 0x40000000
672#define E1000_TXD_CMD_IDE 0x80000000
673#define E1000_TXD_STAT_DD 0x00000001
674#define E1000_TXD_STAT_EC 0x00000002
675#define E1000_TXD_STAT_LC 0x00000004
676#define E1000_TXD_STAT_TU 0x00000008
677#define E1000_TXD_CMD_TCP 0x01000000
678#define E1000_TXD_CMD_IP 0x02000000
679#define E1000_TXD_CMD_TSE 0x04000000
680#define E1000_TXD_STAT_TC 0x00000004
681
682
683struct e1000_context_desc {
684 union {
685 __le32 ip_config;
686 struct {
687 u8 ipcss;
688 u8 ipcso;
689 __le16 ipcse;
690 } ip_fields;
691 } lower_setup;
692 union {
693 __le32 tcp_config;
694 struct {
695 u8 tucss;
696 u8 tucso;
697 __le16 tucse;
698 } tcp_fields;
699 } upper_setup;
700 __le32 cmd_and_length;
701 union {
702 __le32 data;
703 struct {
704 u8 status;
705 u8 hdr_len;
706 __le16 mss;
707 } fields;
708 } tcp_seg_setup;
709};
710
711
712struct e1000_data_desc {
713 __le64 buffer_addr;
714 union {
715 __le32 data;
716 struct {
717 __le16 length;
718 u8 typ_len_ext;
719 u8 cmd;
720 } flags;
721 } lower;
722 union {
723 __le32 data;
724 struct {
725 u8 status;
726 u8 popts;
727 __le16 special;
728 } fields;
729 } upper;
730};
731
732
733#define E1000_NUM_UNICAST 16
734#define E1000_MC_TBL_SIZE 128
735#define E1000_VLAN_FILTER_TBL_SIZE 128
736
737
738struct e1000_rar {
739 volatile __le32 low;
740 volatile __le32 high;
741};
742
743
744#define E1000_NUM_MTA_REGISTERS 128
745
746
747struct e1000_ipv4_at_entry {
748 volatile u32 ipv4_addr;
749 volatile u32 reserved;
750};
751
752
753#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
754#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
755#define E1000_IP6AT_SIZE 1
756
757
758struct e1000_ipv6_at_entry {
759 volatile u8 ipv6_addr[16];
760};
761
762
763struct e1000_fflt_entry {
764 volatile u32 length;
765 volatile u32 reserved;
766};
767
768
769struct e1000_ffmt_entry {
770 volatile u32 mask;
771 volatile u32 reserved;
772};
773
774
775struct e1000_ffvt_entry {
776 volatile u32 value;
777 volatile u32 reserved;
778};
779
780
781#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
782
783
784#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
785
786#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
787#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
788#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
789
790#define E1000_DISABLE_SERDES_LOOPBACK 0x0400
791
792
793
794
795
796
797
798
799
800
801
802
803
804#define E1000_CTRL 0x00000
805#define E1000_CTRL_DUP 0x00004
806#define E1000_STATUS 0x00008
807#define E1000_EECD 0x00010
808#define E1000_EERD 0x00014
809#define E1000_CTRL_EXT 0x00018
810#define E1000_FLA 0x0001C
811#define E1000_MDIC 0x00020
812
813#define INTEL_CE_GBE_MDIO_RCOMP_BASE (hw->ce4100_gbe_mdio_base_virt)
814#define E1000_MDIO_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0)
815#define E1000_MDIO_CMD (INTEL_CE_GBE_MDIO_RCOMP_BASE + 4)
816#define E1000_MDIO_DRV (INTEL_CE_GBE_MDIO_RCOMP_BASE + 8)
817#define E1000_MDC_CMD (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0xC)
818#define E1000_RCOMP_CTL (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x20)
819#define E1000_RCOMP_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x24)
820
821#define E1000_SCTL 0x00024
822#define E1000_FEXTNVM 0x00028
823#define E1000_FCAL 0x00028
824#define E1000_FCAH 0x0002C
825#define E1000_FCT 0x00030
826#define E1000_VET 0x00038
827#define E1000_ICR 0x000C0
828#define E1000_ITR 0x000C4
829#define E1000_ICS 0x000C8
830#define E1000_IMS 0x000D0
831#define E1000_IMC 0x000D8
832#define E1000_IAM 0x000E0
833
834
835
836
837
838#define E1000_CTL_AUX 0x000E0
839#define E1000_CTL_AUX_END_SEL_SHIFT 10
840#define E1000_CTL_AUX_ENDIANESS_SHIFT 8
841#define E1000_CTL_AUX_RGMII_RMII_SHIFT 0
842
843
844#define E1000_CTL_AUX_DES_PKT (0x0 << E1000_CTL_AUX_END_SEL_SHIFT)
845
846#define E1000_CTL_AUX_DES (0x1 << E1000_CTL_AUX_END_SEL_SHIFT)
847
848#define E1000_CTL_AUX_PKT (0x2 << E1000_CTL_AUX_END_SEL_SHIFT)
849
850#define E1000_CTL_AUX_ALL (0x3 << E1000_CTL_AUX_END_SEL_SHIFT)
851
852#define E1000_CTL_AUX_RGMII (0x0 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
853#define E1000_CTL_AUX_RMII (0x1 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
854
855
856#define E1000_CTL_AUX_LWLE_BBE (0x0 << E1000_CTL_AUX_ENDIANESS_SHIFT)
857#define E1000_CTL_AUX_LWLE_BLE (0x1 << E1000_CTL_AUX_ENDIANESS_SHIFT)
858#define E1000_CTL_AUX_LWBE_BBE (0x2 << E1000_CTL_AUX_ENDIANESS_SHIFT)
859#define E1000_CTL_AUX_LWBE_BLE (0x3 << E1000_CTL_AUX_ENDIANESS_SHIFT)
860
861#define E1000_RCTL 0x00100
862#define E1000_RDTR1 0x02820
863#define E1000_RDBAL1 0x02900
864#define E1000_RDBAH1 0x02904
865#define E1000_RDLEN1 0x02908
866#define E1000_RDH1 0x02910
867#define E1000_RDT1 0x02918
868#define E1000_FCTTV 0x00170
869#define E1000_TXCW 0x00178
870#define E1000_RXCW 0x00180
871#define E1000_TCTL 0x00400
872#define E1000_TCTL_EXT 0x00404
873#define E1000_TIPG 0x00410
874#define E1000_TBT 0x00448
875#define E1000_AIT 0x00458
876#define E1000_LEDCTL 0x00E00
877#define E1000_EXTCNF_CTRL 0x00F00
878#define E1000_EXTCNF_SIZE 0x00F08
879#define E1000_PHY_CTRL 0x00F10
880#define FEXTNVM_SW_CONFIG 0x0001
881#define E1000_PBA 0x01000
882#define E1000_PBS 0x01008
883#define E1000_EEMNGCTL 0x01010
884#define E1000_FLASH_UPDATES 1000
885#define E1000_EEARBC 0x01024
886#define E1000_FLASHT 0x01028
887#define E1000_EEWR 0x0102C
888#define E1000_FLSWCTL 0x01030
889#define E1000_FLSWDATA 0x01034
890#define E1000_FLSWCNT 0x01038
891#define E1000_FLOP 0x0103C
892#define E1000_ERT 0x02008
893#define E1000_FCRTL 0x02160
894#define E1000_FCRTH 0x02168
895#define E1000_PSRCTL 0x02170
896#define E1000_RDFH 0x02410
897#define E1000_RDFT 0x02418
898#define E1000_RDFHS 0x02420
899#define E1000_RDFTS 0x02428
900#define E1000_RDFPC 0x02430
901#define E1000_RDBAL 0x02800
902#define E1000_RDBAH 0x02804
903#define E1000_RDLEN 0x02808
904#define E1000_RDH 0x02810
905#define E1000_RDT 0x02818
906#define E1000_RDTR 0x02820
907#define E1000_RDBAL0 E1000_RDBAL
908#define E1000_RDBAH0 E1000_RDBAH
909#define E1000_RDLEN0 E1000_RDLEN
910#define E1000_RDH0 E1000_RDH
911#define E1000_RDT0 E1000_RDT
912#define E1000_RDTR0 E1000_RDTR
913#define E1000_RXDCTL 0x02828
914#define E1000_RXDCTL1 0x02928
915#define E1000_RADV 0x0282C
916#define E1000_RSRPD 0x02C00
917#define E1000_RAID 0x02C08
918#define E1000_TXDMAC 0x03000
919#define E1000_KABGTXD 0x03004
920#define E1000_TDFH 0x03410
921#define E1000_TDFT 0x03418
922#define E1000_TDFHS 0x03420
923#define E1000_TDFTS 0x03428
924#define E1000_TDFPC 0x03430
925#define E1000_TDBAL 0x03800
926#define E1000_TDBAH 0x03804
927#define E1000_TDLEN 0x03808
928#define E1000_TDH 0x03810
929#define E1000_TDT 0x03818
930#define E1000_TIDV 0x03820
931#define E1000_TXDCTL 0x03828
932#define E1000_TADV 0x0382C
933#define E1000_TSPMT 0x03830
934#define E1000_TARC0 0x03840
935#define E1000_TDBAL1 0x03900
936#define E1000_TDBAH1 0x03904
937#define E1000_TDLEN1 0x03908
938#define E1000_TDH1 0x03910
939#define E1000_TDT1 0x03918
940#define E1000_TXDCTL1 0x03928
941#define E1000_TARC1 0x03940
942#define E1000_CRCERRS 0x04000
943#define E1000_ALGNERRC 0x04004
944#define E1000_SYMERRS 0x04008
945#define E1000_RXERRC 0x0400C
946#define E1000_MPC 0x04010
947#define E1000_SCC 0x04014
948#define E1000_ECOL 0x04018
949#define E1000_MCC 0x0401C
950#define E1000_LATECOL 0x04020
951#define E1000_COLC 0x04028
952#define E1000_DC 0x04030
953#define E1000_TNCRS 0x04034
954#define E1000_SEC 0x04038
955#define E1000_CEXTERR 0x0403C
956#define E1000_RLEC 0x04040
957#define E1000_XONRXC 0x04048
958#define E1000_XONTXC 0x0404C
959#define E1000_XOFFRXC 0x04050
960#define E1000_XOFFTXC 0x04054
961#define E1000_FCRUC 0x04058
962#define E1000_PRC64 0x0405C
963#define E1000_PRC127 0x04060
964#define E1000_PRC255 0x04064
965#define E1000_PRC511 0x04068
966#define E1000_PRC1023 0x0406C
967#define E1000_PRC1522 0x04070
968#define E1000_GPRC 0x04074
969#define E1000_BPRC 0x04078
970#define E1000_MPRC 0x0407C
971#define E1000_GPTC 0x04080
972#define E1000_GORCL 0x04088
973#define E1000_GORCH 0x0408C
974#define E1000_GOTCL 0x04090
975#define E1000_GOTCH 0x04094
976#define E1000_RNBC 0x040A0
977#define E1000_RUC 0x040A4
978#define E1000_RFC 0x040A8
979#define E1000_ROC 0x040AC
980#define E1000_RJC 0x040B0
981#define E1000_MGTPRC 0x040B4
982#define E1000_MGTPDC 0x040B8
983#define E1000_MGTPTC 0x040BC
984#define E1000_TORL 0x040C0
985#define E1000_TORH 0x040C4
986#define E1000_TOTL 0x040C8
987#define E1000_TOTH 0x040CC
988#define E1000_TPR 0x040D0
989#define E1000_TPT 0x040D4
990#define E1000_PTC64 0x040D8
991#define E1000_PTC127 0x040DC
992#define E1000_PTC255 0x040E0
993#define E1000_PTC511 0x040E4
994#define E1000_PTC1023 0x040E8
995#define E1000_PTC1522 0x040EC
996#define E1000_MPTC 0x040F0
997#define E1000_BPTC 0x040F4
998#define E1000_TSCTC 0x040F8
999#define E1000_TSCTFC 0x040FC
1000#define E1000_IAC 0x04100
1001#define E1000_ICRXPTC 0x04104
1002#define E1000_ICRXATC 0x04108
1003#define E1000_ICTXPTC 0x0410C
1004#define E1000_ICTXATC 0x04110
1005#define E1000_ICTXQEC 0x04118
1006#define E1000_ICTXQMTC 0x0411C
1007#define E1000_ICRXDMTC 0x04120
1008#define E1000_ICRXOC 0x04124
1009#define E1000_RXCSUM 0x05000
1010#define E1000_RFCTL 0x05008
1011#define E1000_MTA 0x05200
1012#define E1000_RA 0x05400
1013#define E1000_VFTA 0x05600
1014#define E1000_WUC 0x05800
1015#define E1000_WUFC 0x05808
1016#define E1000_WUS 0x05810
1017#define E1000_MANC 0x05820
1018#define E1000_IPAV 0x05838
1019#define E1000_IP4AT 0x05840
1020#define E1000_IP6AT 0x05880
1021#define E1000_WUPL 0x05900
1022#define E1000_WUPM 0x05A00
1023#define E1000_FFLT 0x05F00
1024#define E1000_HOST_IF 0x08800
1025#define E1000_FFMT 0x09000
1026#define E1000_FFVT 0x09800
1027
1028#define E1000_KUMCTRLSTA 0x00034
1029#define E1000_MDPHYA 0x0003C
1030#define E1000_MANC2H 0x05860
1031#define E1000_SW_FW_SYNC 0x05B5C
1032
1033#define E1000_GCR 0x05B00
1034#define E1000_GSCL_1 0x05B10
1035#define E1000_GSCL_2 0x05B14
1036#define E1000_GSCL_3 0x05B18
1037#define E1000_GSCL_4 0x05B1C
1038#define E1000_FACTPS 0x05B30
1039#define E1000_SWSM 0x05B50
1040#define E1000_FWSM 0x05B54
1041#define E1000_FFLT_DBG 0x05F04
1042#define E1000_HICR 0x08F00
1043
1044
1045#define E1000_CPUVEC 0x02C10
1046#define E1000_MRQC 0x05818
1047#define E1000_RETA 0x05C00
1048#define E1000_RSSRK 0x05C80
1049#define E1000_RSSIM 0x05864
1050#define E1000_RSSIR 0x05868
1051
1052
1053
1054
1055
1056
1057#define E1000_82542_CTL_AUX E1000_CTL_AUX
1058#define E1000_82542_CTRL E1000_CTRL
1059#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1060#define E1000_82542_STATUS E1000_STATUS
1061#define E1000_82542_EECD E1000_EECD
1062#define E1000_82542_EERD E1000_EERD
1063#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1064#define E1000_82542_FLA E1000_FLA
1065#define E1000_82542_MDIC E1000_MDIC
1066#define E1000_82542_SCTL E1000_SCTL
1067#define E1000_82542_FEXTNVM E1000_FEXTNVM
1068#define E1000_82542_FCAL E1000_FCAL
1069#define E1000_82542_FCAH E1000_FCAH
1070#define E1000_82542_FCT E1000_FCT
1071#define E1000_82542_VET E1000_VET
1072#define E1000_82542_RA 0x00040
1073#define E1000_82542_ICR E1000_ICR
1074#define E1000_82542_ITR E1000_ITR
1075#define E1000_82542_ICS E1000_ICS
1076#define E1000_82542_IMS E1000_IMS
1077#define E1000_82542_IMC E1000_IMC
1078#define E1000_82542_RCTL E1000_RCTL
1079#define E1000_82542_RDTR 0x00108
1080#define E1000_82542_RDFH E1000_RDFH
1081#define E1000_82542_RDFT E1000_RDFT
1082#define E1000_82542_RDFHS E1000_RDFHS
1083#define E1000_82542_RDFTS E1000_RDFTS
1084#define E1000_82542_RDFPC E1000_RDFPC
1085#define E1000_82542_RDBAL 0x00110
1086#define E1000_82542_RDBAH 0x00114
1087#define E1000_82542_RDLEN 0x00118
1088#define E1000_82542_RDH 0x00120
1089#define E1000_82542_RDT 0x00128
1090#define E1000_82542_RDTR0 E1000_82542_RDTR
1091#define E1000_82542_RDBAL0 E1000_82542_RDBAL
1092#define E1000_82542_RDBAH0 E1000_82542_RDBAH
1093#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1094#define E1000_82542_RDH0 E1000_82542_RDH
1095#define E1000_82542_RDT0 E1000_82542_RDT
1096#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8))
1097
1098#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1099#define E1000_82542_RDBAH3 0x02B04
1100#define E1000_82542_RDBAL3 0x02B00
1101#define E1000_82542_RDLEN3 0x02B08
1102#define E1000_82542_RDH3 0x02B10
1103#define E1000_82542_RDT3 0x02B18
1104#define E1000_82542_RDBAL2 0x02A00
1105#define E1000_82542_RDBAH2 0x02A04
1106#define E1000_82542_RDLEN2 0x02A08
1107#define E1000_82542_RDH2 0x02A10
1108#define E1000_82542_RDT2 0x02A18
1109#define E1000_82542_RDTR1 0x00130
1110#define E1000_82542_RDBAL1 0x00138
1111#define E1000_82542_RDBAH1 0x0013C
1112#define E1000_82542_RDLEN1 0x00140
1113#define E1000_82542_RDH1 0x00148
1114#define E1000_82542_RDT1 0x00150
1115#define E1000_82542_FCRTH 0x00160
1116#define E1000_82542_FCRTL 0x00168
1117#define E1000_82542_FCTTV E1000_FCTTV
1118#define E1000_82542_TXCW E1000_TXCW
1119#define E1000_82542_RXCW E1000_RXCW
1120#define E1000_82542_MTA 0x00200
1121#define E1000_82542_TCTL E1000_TCTL
1122#define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1123#define E1000_82542_TIPG E1000_TIPG
1124#define E1000_82542_TDBAL 0x00420
1125#define E1000_82542_TDBAH 0x00424
1126#define E1000_82542_TDLEN 0x00428
1127#define E1000_82542_TDH 0x00430
1128#define E1000_82542_TDT 0x00438
1129#define E1000_82542_TIDV 0x00440
1130#define E1000_82542_TBT E1000_TBT
1131#define E1000_82542_AIT E1000_AIT
1132#define E1000_82542_VFTA 0x00600
1133#define E1000_82542_LEDCTL E1000_LEDCTL
1134#define E1000_82542_PBA E1000_PBA
1135#define E1000_82542_PBS E1000_PBS
1136#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1137#define E1000_82542_EEARBC E1000_EEARBC
1138#define E1000_82542_FLASHT E1000_FLASHT
1139#define E1000_82542_EEWR E1000_EEWR
1140#define E1000_82542_FLSWCTL E1000_FLSWCTL
1141#define E1000_82542_FLSWDATA E1000_FLSWDATA
1142#define E1000_82542_FLSWCNT E1000_FLSWCNT
1143#define E1000_82542_FLOP E1000_FLOP
1144#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1145#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1146#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1147#define E1000_82542_ERT E1000_ERT
1148#define E1000_82542_RXDCTL E1000_RXDCTL
1149#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1150#define E1000_82542_RADV E1000_RADV
1151#define E1000_82542_RSRPD E1000_RSRPD
1152#define E1000_82542_TXDMAC E1000_TXDMAC
1153#define E1000_82542_KABGTXD E1000_KABGTXD
1154#define E1000_82542_TDFHS E1000_TDFHS
1155#define E1000_82542_TDFTS E1000_TDFTS
1156#define E1000_82542_TDFPC E1000_TDFPC
1157#define E1000_82542_TXDCTL E1000_TXDCTL
1158#define E1000_82542_TADV E1000_TADV
1159#define E1000_82542_TSPMT E1000_TSPMT
1160#define E1000_82542_CRCERRS E1000_CRCERRS
1161#define E1000_82542_ALGNERRC E1000_ALGNERRC
1162#define E1000_82542_SYMERRS E1000_SYMERRS
1163#define E1000_82542_RXERRC E1000_RXERRC
1164#define E1000_82542_MPC E1000_MPC
1165#define E1000_82542_SCC E1000_SCC
1166#define E1000_82542_ECOL E1000_ECOL
1167#define E1000_82542_MCC E1000_MCC
1168#define E1000_82542_LATECOL E1000_LATECOL
1169#define E1000_82542_COLC E1000_COLC
1170#define E1000_82542_DC E1000_DC
1171#define E1000_82542_TNCRS E1000_TNCRS
1172#define E1000_82542_SEC E1000_SEC
1173#define E1000_82542_CEXTERR E1000_CEXTERR
1174#define E1000_82542_RLEC E1000_RLEC
1175#define E1000_82542_XONRXC E1000_XONRXC
1176#define E1000_82542_XONTXC E1000_XONTXC
1177#define E1000_82542_XOFFRXC E1000_XOFFRXC
1178#define E1000_82542_XOFFTXC E1000_XOFFTXC
1179#define E1000_82542_FCRUC E1000_FCRUC
1180#define E1000_82542_PRC64 E1000_PRC64
1181#define E1000_82542_PRC127 E1000_PRC127
1182#define E1000_82542_PRC255 E1000_PRC255
1183#define E1000_82542_PRC511 E1000_PRC511
1184#define E1000_82542_PRC1023 E1000_PRC1023
1185#define E1000_82542_PRC1522 E1000_PRC1522
1186#define E1000_82542_GPRC E1000_GPRC
1187#define E1000_82542_BPRC E1000_BPRC
1188#define E1000_82542_MPRC E1000_MPRC
1189#define E1000_82542_GPTC E1000_GPTC
1190#define E1000_82542_GORCL E1000_GORCL
1191#define E1000_82542_GORCH E1000_GORCH
1192#define E1000_82542_GOTCL E1000_GOTCL
1193#define E1000_82542_GOTCH E1000_GOTCH
1194#define E1000_82542_RNBC E1000_RNBC
1195#define E1000_82542_RUC E1000_RUC
1196#define E1000_82542_RFC E1000_RFC
1197#define E1000_82542_ROC E1000_ROC
1198#define E1000_82542_RJC E1000_RJC
1199#define E1000_82542_MGTPRC E1000_MGTPRC
1200#define E1000_82542_MGTPDC E1000_MGTPDC
1201#define E1000_82542_MGTPTC E1000_MGTPTC
1202#define E1000_82542_TORL E1000_TORL
1203#define E1000_82542_TORH E1000_TORH
1204#define E1000_82542_TOTL E1000_TOTL
1205#define E1000_82542_TOTH E1000_TOTH
1206#define E1000_82542_TPR E1000_TPR
1207#define E1000_82542_TPT E1000_TPT
1208#define E1000_82542_PTC64 E1000_PTC64
1209#define E1000_82542_PTC127 E1000_PTC127
1210#define E1000_82542_PTC255 E1000_PTC255
1211#define E1000_82542_PTC511 E1000_PTC511
1212#define E1000_82542_PTC1023 E1000_PTC1023
1213#define E1000_82542_PTC1522 E1000_PTC1522
1214#define E1000_82542_MPTC E1000_MPTC
1215#define E1000_82542_BPTC E1000_BPTC
1216#define E1000_82542_TSCTC E1000_TSCTC
1217#define E1000_82542_TSCTFC E1000_TSCTFC
1218#define E1000_82542_RXCSUM E1000_RXCSUM
1219#define E1000_82542_WUC E1000_WUC
1220#define E1000_82542_WUFC E1000_WUFC
1221#define E1000_82542_WUS E1000_WUS
1222#define E1000_82542_MANC E1000_MANC
1223#define E1000_82542_IPAV E1000_IPAV
1224#define E1000_82542_IP4AT E1000_IP4AT
1225#define E1000_82542_IP6AT E1000_IP6AT
1226#define E1000_82542_WUPL E1000_WUPL
1227#define E1000_82542_WUPM E1000_WUPM
1228#define E1000_82542_FFLT E1000_FFLT
1229#define E1000_82542_TDFH 0x08010
1230#define E1000_82542_TDFT 0x08018
1231#define E1000_82542_FFMT E1000_FFMT
1232#define E1000_82542_FFVT E1000_FFVT
1233#define E1000_82542_HOST_IF E1000_HOST_IF
1234#define E1000_82542_IAM E1000_IAM
1235#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1236#define E1000_82542_PSRCTL E1000_PSRCTL
1237#define E1000_82542_RAID E1000_RAID
1238#define E1000_82542_TARC0 E1000_TARC0
1239#define E1000_82542_TDBAL1 E1000_TDBAL1
1240#define E1000_82542_TDBAH1 E1000_TDBAH1
1241#define E1000_82542_TDLEN1 E1000_TDLEN1
1242#define E1000_82542_TDH1 E1000_TDH1
1243#define E1000_82542_TDT1 E1000_TDT1
1244#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1245#define E1000_82542_TARC1 E1000_TARC1
1246#define E1000_82542_RFCTL E1000_RFCTL
1247#define E1000_82542_GCR E1000_GCR
1248#define E1000_82542_GSCL_1 E1000_GSCL_1
1249#define E1000_82542_GSCL_2 E1000_GSCL_2
1250#define E1000_82542_GSCL_3 E1000_GSCL_3
1251#define E1000_82542_GSCL_4 E1000_GSCL_4
1252#define E1000_82542_FACTPS E1000_FACTPS
1253#define E1000_82542_SWSM E1000_SWSM
1254#define E1000_82542_FWSM E1000_FWSM
1255#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1256#define E1000_82542_IAC E1000_IAC
1257#define E1000_82542_ICRXPTC E1000_ICRXPTC
1258#define E1000_82542_ICRXATC E1000_ICRXATC
1259#define E1000_82542_ICTXPTC E1000_ICTXPTC
1260#define E1000_82542_ICTXATC E1000_ICTXATC
1261#define E1000_82542_ICTXQEC E1000_ICTXQEC
1262#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1263#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1264#define E1000_82542_ICRXOC E1000_ICRXOC
1265#define E1000_82542_HICR E1000_HICR
1266
1267#define E1000_82542_CPUVEC E1000_CPUVEC
1268#define E1000_82542_MRQC E1000_MRQC
1269#define E1000_82542_RETA E1000_RETA
1270#define E1000_82542_RSSRK E1000_RSSRK
1271#define E1000_82542_RSSIM E1000_RSSIM
1272#define E1000_82542_RSSIR E1000_RSSIR
1273#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1274#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
1275
1276
1277struct e1000_hw_stats {
1278 u64 crcerrs;
1279 u64 algnerrc;
1280 u64 symerrs;
1281 u64 rxerrc;
1282 u64 txerrc;
1283 u64 mpc;
1284 u64 scc;
1285 u64 ecol;
1286 u64 mcc;
1287 u64 latecol;
1288 u64 colc;
1289 u64 dc;
1290 u64 tncrs;
1291 u64 sec;
1292 u64 cexterr;
1293 u64 rlec;
1294 u64 xonrxc;
1295 u64 xontxc;
1296 u64 xoffrxc;
1297 u64 xofftxc;
1298 u64 fcruc;
1299 u64 prc64;
1300 u64 prc127;
1301 u64 prc255;
1302 u64 prc511;
1303 u64 prc1023;
1304 u64 prc1522;
1305 u64 gprc;
1306 u64 bprc;
1307 u64 mprc;
1308 u64 gptc;
1309 u64 gorcl;
1310 u64 gorch;
1311 u64 gotcl;
1312 u64 gotch;
1313 u64 rnbc;
1314 u64 ruc;
1315 u64 rfc;
1316 u64 roc;
1317 u64 rlerrc;
1318 u64 rjc;
1319 u64 mgprc;
1320 u64 mgpdc;
1321 u64 mgptc;
1322 u64 torl;
1323 u64 torh;
1324 u64 totl;
1325 u64 toth;
1326 u64 tpr;
1327 u64 tpt;
1328 u64 ptc64;
1329 u64 ptc127;
1330 u64 ptc255;
1331 u64 ptc511;
1332 u64 ptc1023;
1333 u64 ptc1522;
1334 u64 mptc;
1335 u64 bptc;
1336 u64 tsctc;
1337 u64 tsctfc;
1338 u64 iac;
1339 u64 icrxptc;
1340 u64 icrxatc;
1341 u64 ictxptc;
1342 u64 ictxatc;
1343 u64 ictxqec;
1344 u64 ictxqmtc;
1345 u64 icrxdmtc;
1346 u64 icrxoc;
1347};
1348
1349
1350struct e1000_hw {
1351 u8 __iomem *hw_addr;
1352 u8 __iomem *flash_address;
1353 void __iomem *ce4100_gbe_mdio_base_virt;
1354 e1000_mac_type mac_type;
1355 e1000_phy_type phy_type;
1356 u32 phy_init_script;
1357 e1000_media_type media_type;
1358 void *back;
1359 struct e1000_shadow_ram *eeprom_shadow_ram;
1360 u32 flash_bank_size;
1361 u32 flash_base_addr;
1362 e1000_fc_type fc;
1363 e1000_bus_speed bus_speed;
1364 e1000_bus_width bus_width;
1365 e1000_bus_type bus_type;
1366 struct e1000_eeprom_info eeprom;
1367 e1000_ms_type master_slave;
1368 e1000_ms_type original_master_slave;
1369 e1000_ffe_config ffe_config_state;
1370 u32 asf_firmware_present;
1371 u32 eeprom_semaphore_present;
1372 unsigned long io_base;
1373 u32 phy_id;
1374 u32 phy_revision;
1375 u32 phy_addr;
1376 u32 original_fc;
1377 u32 txcw;
1378 u32 autoneg_failed;
1379 u32 max_frame_size;
1380 u32 min_frame_size;
1381 u32 mc_filter_type;
1382 u32 num_mc_addrs;
1383 u32 collision_delta;
1384 u32 tx_packet_delta;
1385 u32 ledctl_default;
1386 u32 ledctl_mode1;
1387 u32 ledctl_mode2;
1388 bool tx_pkt_filtering;
1389 struct e1000_host_mng_dhcp_cookie mng_cookie;
1390 u16 phy_spd_default;
1391 u16 autoneg_advertised;
1392 u16 pci_cmd_word;
1393 u16 fc_high_water;
1394 u16 fc_low_water;
1395 u16 fc_pause_time;
1396 u16 current_ifs_val;
1397 u16 ifs_min_val;
1398 u16 ifs_max_val;
1399 u16 ifs_step_size;
1400 u16 ifs_ratio;
1401 u16 device_id;
1402 u16 vendor_id;
1403 u16 subsystem_id;
1404 u16 subsystem_vendor_id;
1405 u8 revision_id;
1406 u8 autoneg;
1407 u8 mdix;
1408 u8 forced_speed_duplex;
1409 u8 wait_autoneg_complete;
1410 u8 dma_fairness;
1411 u8 mac_addr[NODE_ADDRESS_SIZE];
1412 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1413 bool disable_polarity_correction;
1414 bool speed_downgraded;
1415 e1000_smart_speed smart_speed;
1416 e1000_dsp_config dsp_config_state;
1417 bool get_link_status;
1418 bool serdes_has_link;
1419 bool tbi_compatibility_en;
1420 bool tbi_compatibility_on;
1421 bool laa_is_present;
1422 bool phy_reset_disable;
1423 bool initialize_hw_bits_disable;
1424 bool fc_send_xon;
1425 bool fc_strict_ieee;
1426 bool report_tx_early;
1427 bool adaptive_ifs;
1428 bool ifs_params_forced;
1429 bool in_ifs_mode;
1430 bool mng_reg_access_disabled;
1431 bool leave_av_bit_off;
1432 bool bad_tx_carr_stats_fd;
1433 bool has_smbus;
1434};
1435
1436#define E1000_EEPROM_SWDPIN0 0x0001
1437#define E1000_EEPROM_LED_LOGIC 0x0020
1438#define E1000_EEPROM_RW_REG_DATA 16
1439#define E1000_EEPROM_RW_REG_DONE 2
1440#define E1000_EEPROM_RW_REG_START 1
1441#define E1000_EEPROM_RW_ADDR_SHIFT 2
1442#define E1000_EEPROM_POLL_WRITE 1
1443#define E1000_EEPROM_POLL_READ 0
1444
1445
1446#define E1000_CTRL_FD 0x00000001
1447#define E1000_CTRL_BEM 0x00000002
1448#define E1000_CTRL_PRIOR 0x00000004
1449#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
1450#define E1000_CTRL_LRST 0x00000008
1451#define E1000_CTRL_TME 0x00000010
1452#define E1000_CTRL_SLE 0x00000020
1453#define E1000_CTRL_ASDE 0x00000020
1454#define E1000_CTRL_SLU 0x00000040
1455#define E1000_CTRL_ILOS 0x00000080
1456#define E1000_CTRL_SPD_SEL 0x00000300
1457#define E1000_CTRL_SPD_10 0x00000000
1458#define E1000_CTRL_SPD_100 0x00000100
1459#define E1000_CTRL_SPD_1000 0x00000200
1460#define E1000_CTRL_BEM32 0x00000400
1461#define E1000_CTRL_FRCSPD 0x00000800
1462#define E1000_CTRL_FRCDPX 0x00001000
1463#define E1000_CTRL_D_UD_EN 0x00002000
1464#define E1000_CTRL_D_UD_POLARITY 0x00004000
1465#define E1000_CTRL_FORCE_PHY_RESET 0x00008000
1466#define E1000_CTRL_EXT_LINK_EN 0x00010000
1467#define E1000_CTRL_SWDPIN0 0x00040000
1468#define E1000_CTRL_SWDPIN1 0x00080000
1469#define E1000_CTRL_SWDPIN2 0x00100000
1470#define E1000_CTRL_SWDPIN3 0x00200000
1471#define E1000_CTRL_SWDPIO0 0x00400000
1472#define E1000_CTRL_SWDPIO1 0x00800000
1473#define E1000_CTRL_SWDPIO2 0x01000000
1474#define E1000_CTRL_SWDPIO3 0x02000000
1475#define E1000_CTRL_RST 0x04000000
1476#define E1000_CTRL_RFCE 0x08000000
1477#define E1000_CTRL_TFCE 0x10000000
1478#define E1000_CTRL_RTE 0x20000000
1479#define E1000_CTRL_VME 0x40000000
1480#define E1000_CTRL_PHY_RST 0x80000000
1481#define E1000_CTRL_SW2FW_INT 0x02000000
1482
1483
1484#define E1000_STATUS_FD 0x00000001
1485#define E1000_STATUS_LU 0x00000002
1486#define E1000_STATUS_FUNC_MASK 0x0000000C
1487#define E1000_STATUS_FUNC_SHIFT 2
1488#define E1000_STATUS_FUNC_0 0x00000000
1489#define E1000_STATUS_FUNC_1 0x00000004
1490#define E1000_STATUS_TXOFF 0x00000010
1491#define E1000_STATUS_TBIMODE 0x00000020
1492#define E1000_STATUS_SPEED_MASK 0x000000C0
1493#define E1000_STATUS_SPEED_10 0x00000000
1494#define E1000_STATUS_SPEED_100 0x00000040
1495#define E1000_STATUS_SPEED_1000 0x00000080
1496#define E1000_STATUS_LAN_INIT_DONE 0x00000200
1497
1498#define E1000_STATUS_ASDV 0x00000300
1499#define E1000_STATUS_DOCK_CI 0x00000800
1500#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
1501#define E1000_STATUS_MTXCKOK 0x00000400
1502#define E1000_STATUS_PCI66 0x00000800
1503#define E1000_STATUS_BUS64 0x00001000
1504#define E1000_STATUS_PCIX_MODE 0x00002000
1505#define E1000_STATUS_PCIX_SPEED 0x0000C000
1506#define E1000_STATUS_BMC_SKU_0 0x00100000
1507#define E1000_STATUS_BMC_SKU_1 0x00200000
1508#define E1000_STATUS_BMC_SKU_2 0x00400000
1509#define E1000_STATUS_BMC_CRYPTO 0x00800000
1510#define E1000_STATUS_BMC_LITE 0x01000000
1511#define E1000_STATUS_RGMII_ENABLE 0x02000000
1512#define E1000_STATUS_FUSE_8 0x04000000
1513#define E1000_STATUS_FUSE_9 0x08000000
1514#define E1000_STATUS_SERDES0_DIS 0x10000000
1515#define E1000_STATUS_SERDES1_DIS 0x20000000
1516
1517
1518#define E1000_STATUS_PCIX_SPEED_66 0x00000000
1519#define E1000_STATUS_PCIX_SPEED_100 0x00004000
1520#define E1000_STATUS_PCIX_SPEED_133 0x00008000
1521
1522
1523#define E1000_EECD_SK 0x00000001
1524#define E1000_EECD_CS 0x00000002
1525#define E1000_EECD_DI 0x00000004
1526#define E1000_EECD_DO 0x00000008
1527#define E1000_EECD_FWE_MASK 0x00000030
1528#define E1000_EECD_FWE_DIS 0x00000010
1529#define E1000_EECD_FWE_EN 0x00000020
1530#define E1000_EECD_FWE_SHIFT 4
1531#define E1000_EECD_REQ 0x00000040
1532#define E1000_EECD_GNT 0x00000080
1533#define E1000_EECD_PRES 0x00000100
1534#define E1000_EECD_SIZE 0x00000200
1535#define E1000_EECD_ADDR_BITS 0x00000400
1536
1537#define E1000_EECD_TYPE 0x00002000
1538#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1539#define E1000_EEPROM_GRANT_ATTEMPTS 1000
1540#endif
1541#define E1000_EECD_AUTO_RD 0x00000200
1542#define E1000_EECD_SIZE_EX_MASK 0x00007800
1543#define E1000_EECD_SIZE_EX_SHIFT 11
1544#define E1000_EECD_NVADDS 0x00018000
1545#define E1000_EECD_SELSHAD 0x00020000
1546#define E1000_EECD_INITSRAM 0x00040000
1547#define E1000_EECD_FLUPD 0x00080000
1548#define E1000_EECD_AUPDEN 0x00100000
1549#define E1000_EECD_SHADV 0x00200000
1550#define E1000_EECD_SEC1VAL 0x00400000
1551#define E1000_EECD_SECVAL_SHIFT 22
1552#define E1000_STM_OPCODE 0xDB00
1553#define E1000_HICR_FW_RESET 0xC0
1554
1555#define E1000_SHADOW_RAM_WORDS 2048
1556#define E1000_ICH_NVM_SIG_WORD 0x13
1557#define E1000_ICH_NVM_SIG_MASK 0xC0
1558
1559
1560#define E1000_EERD_START 0x00000001
1561#define E1000_EERD_DONE 0x00000010
1562#define E1000_EERD_ADDR_SHIFT 8
1563#define E1000_EERD_ADDR_MASK 0x0000FF00
1564#define E1000_EERD_DATA_SHIFT 16
1565#define E1000_EERD_DATA_MASK 0xFFFF0000
1566
1567
1568#define EEPROM_STATUS_RDY_SPI 0x01
1569#define EEPROM_STATUS_WEN_SPI 0x02
1570#define EEPROM_STATUS_BP0_SPI 0x04
1571#define EEPROM_STATUS_BP1_SPI 0x08
1572#define EEPROM_STATUS_WPEN_SPI 0x80
1573
1574
1575#define E1000_CTRL_EXT_GPI0_EN 0x00000001
1576#define E1000_CTRL_EXT_GPI1_EN 0x00000002
1577#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1578#define E1000_CTRL_EXT_GPI2_EN 0x00000004
1579#define E1000_CTRL_EXT_GPI3_EN 0x00000008
1580#define E1000_CTRL_EXT_SDP4_DATA 0x00000010
1581#define E1000_CTRL_EXT_SDP5_DATA 0x00000020
1582#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1583#define E1000_CTRL_EXT_SDP6_DATA 0x00000040
1584#define E1000_CTRL_EXT_SDP7_DATA 0x00000080
1585#define E1000_CTRL_EXT_SDP4_DIR 0x00000100
1586#define E1000_CTRL_EXT_SDP5_DIR 0x00000200
1587#define E1000_CTRL_EXT_SDP6_DIR 0x00000400
1588#define E1000_CTRL_EXT_SDP7_DIR 0x00000800
1589#define E1000_CTRL_EXT_ASDCHK 0x00001000
1590#define E1000_CTRL_EXT_EE_RST 0x00002000
1591#define E1000_CTRL_EXT_IPS 0x00004000
1592#define E1000_CTRL_EXT_SPD_BYPS 0x00008000
1593#define E1000_CTRL_EXT_RO_DIS 0x00020000
1594#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1595#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1596#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1597#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
1598#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
1599#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
1600#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1601#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1602#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1603#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1604#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1605#define E1000_CTRL_EXT_DRV_LOAD 0x10000000
1606#define E1000_CTRL_EXT_IAME 0x08000000
1607#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000
1608#define E1000_CRTL_EXT_PB_PAREN 0x01000000
1609#define E1000_CTRL_EXT_DF_PAREN 0x02000000
1610#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1611
1612
1613#define E1000_MDIC_DATA_MASK 0x0000FFFF
1614#define E1000_MDIC_REG_MASK 0x001F0000
1615#define E1000_MDIC_REG_SHIFT 16
1616#define E1000_MDIC_PHY_MASK 0x03E00000
1617#define E1000_MDIC_PHY_SHIFT 21
1618#define E1000_MDIC_OP_WRITE 0x04000000
1619#define E1000_MDIC_OP_READ 0x08000000
1620#define E1000_MDIC_READY 0x10000000
1621#define E1000_MDIC_INT_EN 0x20000000
1622#define E1000_MDIC_ERROR 0x40000000
1623
1624#define INTEL_CE_GBE_MDIC_OP_WRITE 0x04000000
1625#define INTEL_CE_GBE_MDIC_OP_READ 0x00000000
1626#define INTEL_CE_GBE_MDIC_GO 0x80000000
1627#define INTEL_CE_GBE_MDIC_READ_ERROR 0x80000000
1628
1629#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1630#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1631#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1632#define E1000_KUMCTRLSTA_REN 0x00200000
1633
1634#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1635#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1636#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1637#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1638#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1639#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1640#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1641#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1642#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1643
1644
1645#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1646#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1647
1648
1649#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1650#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1651
1652
1653#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1654#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1655
1656#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1657
1658#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1659#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1660
1661#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1662#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1663#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1664
1665#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1666
1667#define E1000_PHY_CTRL_SPD_EN 0x00000001
1668#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1669#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1670#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1671#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1672#define E1000_PHY_CTRL_B2B_EN 0x00000080
1673
1674
1675#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1676#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1677#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1678#define E1000_LEDCTL_LED0_IVRT 0x00000040
1679#define E1000_LEDCTL_LED0_BLINK 0x00000080
1680#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1681#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1682#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1683#define E1000_LEDCTL_LED1_IVRT 0x00004000
1684#define E1000_LEDCTL_LED1_BLINK 0x00008000
1685#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1686#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1687#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1688#define E1000_LEDCTL_LED2_IVRT 0x00400000
1689#define E1000_LEDCTL_LED2_BLINK 0x00800000
1690#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1691#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1692#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1693#define E1000_LEDCTL_LED3_IVRT 0x40000000
1694#define E1000_LEDCTL_LED3_BLINK 0x80000000
1695
1696#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1697#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1698#define E1000_LEDCTL_MODE_LINK_UP 0x2
1699#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1700#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1701#define E1000_LEDCTL_MODE_LINK_10 0x5
1702#define E1000_LEDCTL_MODE_LINK_100 0x6
1703#define E1000_LEDCTL_MODE_LINK_1000 0x7
1704#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1705#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1706#define E1000_LEDCTL_MODE_COLLISION 0xA
1707#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1708#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1709#define E1000_LEDCTL_MODE_PAUSED 0xD
1710#define E1000_LEDCTL_MODE_LED_ON 0xE
1711#define E1000_LEDCTL_MODE_LED_OFF 0xF
1712
1713
1714#define E1000_RAH_AV 0x80000000
1715
1716
1717#define E1000_ICR_TXDW 0x00000001
1718#define E1000_ICR_TXQE 0x00000002
1719#define E1000_ICR_LSC 0x00000004
1720#define E1000_ICR_RXSEQ 0x00000008
1721#define E1000_ICR_RXDMT0 0x00000010
1722#define E1000_ICR_RXO 0x00000040
1723#define E1000_ICR_RXT0 0x00000080
1724#define E1000_ICR_MDAC 0x00000200
1725#define E1000_ICR_RXCFG 0x00000400
1726#define E1000_ICR_GPI_EN0 0x00000800
1727#define E1000_ICR_GPI_EN1 0x00001000
1728#define E1000_ICR_GPI_EN2 0x00002000
1729#define E1000_ICR_GPI_EN3 0x00004000
1730#define E1000_ICR_TXD_LOW 0x00008000
1731#define E1000_ICR_SRPD 0x00010000
1732#define E1000_ICR_ACK 0x00020000
1733#define E1000_ICR_MNG 0x00040000
1734#define E1000_ICR_DOCK 0x00080000
1735#define E1000_ICR_INT_ASSERTED 0x80000000
1736#define E1000_ICR_RXD_FIFO_PAR0 0x00100000
1737#define E1000_ICR_TXD_FIFO_PAR0 0x00200000
1738#define E1000_ICR_HOST_ARB_PAR 0x00400000
1739#define E1000_ICR_PB_PAR 0x00800000
1740#define E1000_ICR_RXD_FIFO_PAR1 0x01000000
1741#define E1000_ICR_TXD_FIFO_PAR1 0x02000000
1742#define E1000_ICR_ALL_PARITY 0x03F00000
1743#define E1000_ICR_DSW 0x00000020
1744#define E1000_ICR_PHYINT 0x00001000
1745#define E1000_ICR_EPRST 0x00100000
1746
1747
1748#define E1000_ICS_TXDW E1000_ICR_TXDW
1749#define E1000_ICS_TXQE E1000_ICR_TXQE
1750#define E1000_ICS_LSC E1000_ICR_LSC
1751#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
1752#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
1753#define E1000_ICS_RXO E1000_ICR_RXO
1754#define E1000_ICS_RXT0 E1000_ICR_RXT0
1755#define E1000_ICS_MDAC E1000_ICR_MDAC
1756#define E1000_ICS_RXCFG E1000_ICR_RXCFG
1757#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0
1758#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1
1759#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2
1760#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3
1761#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1762#define E1000_ICS_SRPD E1000_ICR_SRPD
1763#define E1000_ICS_ACK E1000_ICR_ACK
1764#define E1000_ICS_MNG E1000_ICR_MNG
1765#define E1000_ICS_DOCK E1000_ICR_DOCK
1766#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
1767#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
1768#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
1769#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR
1770#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
1771#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
1772#define E1000_ICS_DSW E1000_ICR_DSW
1773#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1774#define E1000_ICS_EPRST E1000_ICR_EPRST
1775
1776
1777#define E1000_IMS_TXDW E1000_ICR_TXDW
1778#define E1000_IMS_TXQE E1000_ICR_TXQE
1779#define E1000_IMS_LSC E1000_ICR_LSC
1780#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
1781#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
1782#define E1000_IMS_RXO E1000_ICR_RXO
1783#define E1000_IMS_RXT0 E1000_ICR_RXT0
1784#define E1000_IMS_MDAC E1000_ICR_MDAC
1785#define E1000_IMS_RXCFG E1000_ICR_RXCFG
1786#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0
1787#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1
1788#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2
1789#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3
1790#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1791#define E1000_IMS_SRPD E1000_ICR_SRPD
1792#define E1000_IMS_ACK E1000_ICR_ACK
1793#define E1000_IMS_MNG E1000_ICR_MNG
1794#define E1000_IMS_DOCK E1000_ICR_DOCK
1795#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
1796#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
1797#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
1798#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR
1799#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
1800#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
1801#define E1000_IMS_DSW E1000_ICR_DSW
1802#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1803#define E1000_IMS_EPRST E1000_ICR_EPRST
1804
1805
1806#define E1000_IMC_TXDW E1000_ICR_TXDW
1807#define E1000_IMC_TXQE E1000_ICR_TXQE
1808#define E1000_IMC_LSC E1000_ICR_LSC
1809#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ
1810#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0
1811#define E1000_IMC_RXO E1000_ICR_RXO
1812#define E1000_IMC_RXT0 E1000_ICR_RXT0
1813#define E1000_IMC_MDAC E1000_ICR_MDAC
1814#define E1000_IMC_RXCFG E1000_ICR_RXCFG
1815#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0
1816#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1
1817#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2
1818#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3
1819#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1820#define E1000_IMC_SRPD E1000_ICR_SRPD
1821#define E1000_IMC_ACK E1000_ICR_ACK
1822#define E1000_IMC_MNG E1000_ICR_MNG
1823#define E1000_IMC_DOCK E1000_ICR_DOCK
1824#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
1825#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
1826#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
1827#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR
1828#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
1829#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
1830#define E1000_IMC_DSW E1000_ICR_DSW
1831#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1832#define E1000_IMC_EPRST E1000_ICR_EPRST
1833
1834
1835#define E1000_RCTL_RST 0x00000001
1836#define E1000_RCTL_EN 0x00000002
1837#define E1000_RCTL_SBP 0x00000004
1838#define E1000_RCTL_UPE 0x00000008
1839#define E1000_RCTL_MPE 0x00000010
1840#define E1000_RCTL_LPE 0x00000020
1841#define E1000_RCTL_LBM_NO 0x00000000
1842#define E1000_RCTL_LBM_MAC 0x00000040
1843#define E1000_RCTL_LBM_SLP 0x00000080
1844#define E1000_RCTL_LBM_TCVR 0x000000C0
1845#define E1000_RCTL_DTYP_MASK 0x00000C00
1846#define E1000_RCTL_DTYP_PS 0x00000400
1847#define E1000_RCTL_RDMTS_HALF 0x00000000
1848#define E1000_RCTL_RDMTS_QUAT 0x00000100
1849#define E1000_RCTL_RDMTS_EIGTH 0x00000200
1850#define E1000_RCTL_MO_SHIFT 12
1851#define E1000_RCTL_MO_0 0x00000000
1852#define E1000_RCTL_MO_1 0x00001000
1853#define E1000_RCTL_MO_2 0x00002000
1854#define E1000_RCTL_MO_3 0x00003000
1855#define E1000_RCTL_MDR 0x00004000
1856#define E1000_RCTL_BAM 0x00008000
1857
1858#define E1000_RCTL_SZ_2048 0x00000000
1859#define E1000_RCTL_SZ_1024 0x00010000
1860#define E1000_RCTL_SZ_512 0x00020000
1861#define E1000_RCTL_SZ_256 0x00030000
1862
1863#define E1000_RCTL_SZ_16384 0x00010000
1864#define E1000_RCTL_SZ_8192 0x00020000
1865#define E1000_RCTL_SZ_4096 0x00030000
1866#define E1000_RCTL_VFE 0x00040000
1867#define E1000_RCTL_CFIEN 0x00080000
1868#define E1000_RCTL_CFI 0x00100000
1869#define E1000_RCTL_DPF 0x00400000
1870#define E1000_RCTL_PMCF 0x00800000
1871#define E1000_RCTL_BSEX 0x02000000
1872#define E1000_RCTL_SECRC 0x04000000
1873#define E1000_RCTL_FLXBUF_MASK 0x78000000
1874#define E1000_RCTL_FLXBUF_SHIFT 27
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1893#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1894#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1895#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1896
1897#define E1000_PSRCTL_BSIZE0_SHIFT 7
1898#define E1000_PSRCTL_BSIZE1_SHIFT 2
1899#define E1000_PSRCTL_BSIZE2_SHIFT 6
1900#define E1000_PSRCTL_BSIZE3_SHIFT 14
1901
1902
1903#define E1000_SWFW_EEP_SM 0x0001
1904#define E1000_SWFW_PHY0_SM 0x0002
1905#define E1000_SWFW_PHY1_SM 0x0004
1906#define E1000_SWFW_MAC_CSR_SM 0x0008
1907
1908
1909#define E1000_RDT_DELAY 0x0000ffff
1910#define E1000_RDT_FPDB 0x80000000
1911#define E1000_RDLEN_LEN 0x0007ff80
1912#define E1000_RDH_RDH 0x0000ffff
1913#define E1000_RDT_RDT 0x0000ffff
1914
1915
1916#define E1000_FCRTH_RTH 0x0000FFF8
1917#define E1000_FCRTH_XFCE 0x80000000
1918#define E1000_FCRTL_RTL 0x0000FFF8
1919#define E1000_FCRTL_XONE 0x80000000
1920
1921
1922#define E1000_RFCTL_ISCSI_DIS 0x00000001
1923#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1924#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1925#define E1000_RFCTL_NFSW_DIS 0x00000040
1926#define E1000_RFCTL_NFSR_DIS 0x00000080
1927#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1928#define E1000_RFCTL_NFS_VER_SHIFT 8
1929#define E1000_RFCTL_IPV6_DIS 0x00000400
1930#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1931#define E1000_RFCTL_ACK_DIS 0x00001000
1932#define E1000_RFCTL_ACKD_DIS 0x00002000
1933#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1934#define E1000_RFCTL_EXTEN 0x00008000
1935#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1936#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1937
1938
1939#define E1000_RXDCTL_PTHRESH 0x0000003F
1940#define E1000_RXDCTL_HTHRESH 0x00003F00
1941#define E1000_RXDCTL_WTHRESH 0x003F0000
1942#define E1000_RXDCTL_GRAN 0x01000000
1943
1944
1945#define E1000_TXDCTL_PTHRESH 0x0000003F
1946#define E1000_TXDCTL_HTHRESH 0x00003F00
1947#define E1000_TXDCTL_WTHRESH 0x003F0000
1948#define E1000_TXDCTL_GRAN 0x01000000
1949#define E1000_TXDCTL_LWTHRESH 0xFE000000
1950#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
1951#define E1000_TXDCTL_COUNT_DESC 0x00400000
1952
1953
1954#define E1000_TXCW_FD 0x00000020
1955#define E1000_TXCW_HD 0x00000040
1956#define E1000_TXCW_PAUSE 0x00000080
1957#define E1000_TXCW_ASM_DIR 0x00000100
1958#define E1000_TXCW_PAUSE_MASK 0x00000180
1959#define E1000_TXCW_RF 0x00003000
1960#define E1000_TXCW_NP 0x00008000
1961#define E1000_TXCW_CW 0x0000ffff
1962#define E1000_TXCW_TXC 0x40000000
1963#define E1000_TXCW_ANE 0x80000000
1964
1965
1966#define E1000_RXCW_CW 0x0000ffff
1967#define E1000_RXCW_NC 0x04000000
1968#define E1000_RXCW_IV 0x08000000
1969#define E1000_RXCW_CC 0x10000000
1970#define E1000_RXCW_C 0x20000000
1971#define E1000_RXCW_SYNCH 0x40000000
1972#define E1000_RXCW_ANC 0x80000000
1973
1974
1975#define E1000_TCTL_RST 0x00000001
1976#define E1000_TCTL_EN 0x00000002
1977#define E1000_TCTL_BCE 0x00000004
1978#define E1000_TCTL_PSP 0x00000008
1979#define E1000_TCTL_CT 0x00000ff0
1980#define E1000_TCTL_COLD 0x003ff000
1981#define E1000_TCTL_SWXOFF 0x00400000
1982#define E1000_TCTL_PBE 0x00800000
1983#define E1000_TCTL_RTLC 0x01000000
1984#define E1000_TCTL_NRTU 0x02000000
1985#define E1000_TCTL_MULR 0x10000000
1986
1987#define E1000_TCTL_EXT_BST_MASK 0x000003FF
1988#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00
1989
1990
1991#define E1000_RXCSUM_PCSS_MASK 0x000000FF
1992#define E1000_RXCSUM_IPOFL 0x00000100
1993#define E1000_RXCSUM_TUOFL 0x00000200
1994#define E1000_RXCSUM_IPV6OFL 0x00000400
1995#define E1000_RXCSUM_IPPCSE 0x00001000
1996#define E1000_RXCSUM_PCSD 0x00002000
1997
1998
1999#define E1000_MRQC_ENABLE_MASK 0x00000003
2000#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
2001#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
2002#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
2003#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2004#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
2005#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
2006#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2007#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2008#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2009
2010
2011
2012#define E1000_WUC_APME 0x00000001
2013#define E1000_WUC_PME_EN 0x00000002
2014#define E1000_WUC_PME_STATUS 0x00000004
2015#define E1000_WUC_APMPME 0x00000008
2016#define E1000_WUC_SPM 0x80000000
2017
2018
2019#define E1000_WUFC_LNKC 0x00000001
2020#define E1000_WUFC_MAG 0x00000002
2021#define E1000_WUFC_EX 0x00000004
2022#define E1000_WUFC_MC 0x00000008
2023#define E1000_WUFC_BC 0x00000010
2024#define E1000_WUFC_ARP 0x00000020
2025#define E1000_WUFC_IPV4 0x00000040
2026#define E1000_WUFC_IPV6 0x00000080
2027#define E1000_WUFC_IGNORE_TCO 0x00008000
2028#define E1000_WUFC_FLX0 0x00010000
2029#define E1000_WUFC_FLX1 0x00020000
2030#define E1000_WUFC_FLX2 0x00040000
2031#define E1000_WUFC_FLX3 0x00080000
2032#define E1000_WUFC_ALL_FILTERS 0x000F00FF
2033#define E1000_WUFC_FLX_OFFSET 16
2034#define E1000_WUFC_FLX_FILTERS 0x000F0000
2035
2036
2037#define E1000_WUS_LNKC 0x00000001
2038#define E1000_WUS_MAG 0x00000002
2039#define E1000_WUS_EX 0x00000004
2040#define E1000_WUS_MC 0x00000008
2041#define E1000_WUS_BC 0x00000010
2042#define E1000_WUS_ARP 0x00000020
2043#define E1000_WUS_IPV4 0x00000040
2044#define E1000_WUS_IPV6 0x00000080
2045#define E1000_WUS_FLX0 0x00010000
2046#define E1000_WUS_FLX1 0x00020000
2047#define E1000_WUS_FLX2 0x00040000
2048#define E1000_WUS_FLX3 0x00080000
2049#define E1000_WUS_FLX_FILTERS 0x000F0000
2050
2051
2052#define E1000_MANC_SMBUS_EN 0x00000001
2053#define E1000_MANC_ASF_EN 0x00000002
2054#define E1000_MANC_R_ON_FORCE 0x00000004
2055#define E1000_MANC_RMCP_EN 0x00000100
2056#define E1000_MANC_0298_EN 0x00000200
2057#define E1000_MANC_IPV4_EN 0x00000400
2058#define E1000_MANC_IPV6_EN 0x00000800
2059#define E1000_MANC_SNAP_EN 0x00001000
2060#define E1000_MANC_ARP_EN 0x00002000
2061#define E1000_MANC_NEIGHBOR_EN 0x00004000
2062
2063#define E1000_MANC_ARP_RES_EN 0x00008000
2064#define E1000_MANC_TCO_RESET 0x00010000
2065#define E1000_MANC_RCV_TCO_EN 0x00020000
2066#define E1000_MANC_REPORT_STATUS 0x00040000
2067#define E1000_MANC_RCV_ALL 0x00080000
2068#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
2069#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
2070
2071#define E1000_MANC_EN_MNG2HOST 0x00200000
2072
2073#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
2074
2075#define E1000_MANC_EN_XSUM_FILTER 0x00800000
2076#define E1000_MANC_BR_EN 0x01000000
2077#define E1000_MANC_SMB_REQ 0x01000000
2078#define E1000_MANC_SMB_GNT 0x02000000
2079#define E1000_MANC_SMB_CLK_IN 0x04000000
2080#define E1000_MANC_SMB_DATA_IN 0x08000000
2081#define E1000_MANC_SMB_DATA_OUT 0x10000000
2082#define E1000_MANC_SMB_CLK_OUT 0x20000000
2083
2084#define E1000_MANC_SMB_DATA_OUT_SHIFT 28
2085#define E1000_MANC_SMB_CLK_OUT_SHIFT 29
2086
2087
2088#define E1000_SWSM_SMBI 0x00000001
2089#define E1000_SWSM_SWESMBI 0x00000002
2090#define E1000_SWSM_WMNG 0x00000004
2091#define E1000_SWSM_DRV_LOAD 0x00000008
2092
2093
2094#define E1000_FWSM_MODE_MASK 0x0000000E
2095#define E1000_FWSM_MODE_SHIFT 1
2096#define E1000_FWSM_FW_VALID 0x00008000
2097
2098#define E1000_FWSM_RSPCIPHY 0x00000040
2099#define E1000_FWSM_DISSW 0x10000000
2100#define E1000_FWSM_SKUSEL_MASK 0x60000000
2101#define E1000_FWSM_SKUEL_SHIFT 29
2102#define E1000_FWSM_SKUSEL_EMB 0x0
2103#define E1000_FWSM_SKUSEL_CONS 0x1
2104#define E1000_FWSM_SKUSEL_PERF_100 0x2
2105#define E1000_FWSM_SKUSEL_PERF_GBE 0x3
2106
2107
2108#define E1000_FFLT_DBG_INVC 0x00100000
2109
2110typedef enum {
2111 e1000_mng_mode_none = 0,
2112 e1000_mng_mode_asf,
2113 e1000_mng_mode_pt,
2114 e1000_mng_mode_ipmi,
2115 e1000_mng_mode_host_interface_only
2116} e1000_mng_mode;
2117
2118
2119#define E1000_HICR_EN 0x00000001
2120#define E1000_HICR_C 0x00000002
2121
2122#define E1000_HICR_SV 0x00000004
2123#define E1000_HICR_FWR 0x00000080
2124
2125
2126#define E1000_HI_MAX_DATA_LENGTH 252
2127#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792
2128#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448
2129#define E1000_HI_COMMAND_TIMEOUT 500
2130
2131struct e1000_host_command_header {
2132 u8 command_id;
2133 u8 command_length;
2134 u8 command_options;
2135 u8 checksum;
2136};
2137struct e1000_host_command_info {
2138 struct e1000_host_command_header command_header;
2139 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
2140};
2141
2142
2143#define E1000_HSMC0R_CLKIN 0x00000001
2144#define E1000_HSMC0R_DATAIN 0x00000002
2145#define E1000_HSMC0R_DATAOUT 0x00000004
2146#define E1000_HSMC0R_CLKOUT 0x00000008
2147
2148
2149#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2150#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2151#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2152#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2153
2154
2155#define E1000_FWSTS_FWS_MASK 0x000000FF
2156
2157
2158#define E1000_WUPL_LENGTH_MASK 0x0FFF
2159
2160#define E1000_MDALIGN 4096
2161
2162
2163
2164
2165#define E1000_GCR_RXD_NO_SNOOP 0x00000001
2166#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2167#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2168#define E1000_GCR_TXD_NO_SNOOP 0x00000008
2169#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2170#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2171
2172#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2173 E1000_GCR_RXDSCW_NO_SNOOP | \
2174 E1000_GCR_RXDSCR_NO_SNOOP | \
2175 E1000_GCR_TXD_NO_SNOOP | \
2176 E1000_GCR_TXDSCW_NO_SNOOP | \
2177 E1000_GCR_TXDSCR_NO_SNOOP)
2178
2179#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2180
2181#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2182
2183#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2184#define E1000_FACTPS_LAN0_VALID 0x00000004
2185#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2186#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2187#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2188#define E1000_FACTPS_LAN1_VALID 0x00000100
2189#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2190#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2191#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2192#define E1000_FACTPS_IDE_ENABLE 0x00004000
2193#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2194#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2195#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2196#define E1000_FACTPS_SP_ENABLE 0x00100000
2197#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2198#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2199#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2200#define E1000_FACTPS_IPMI_ENABLE 0x04000000
2201#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2202#define E1000_FACTPS_MNGCG 0x20000000
2203#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2204#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2205
2206
2207#define PCI_EX_LINK_STATUS 0x12
2208#define PCI_EX_LINK_WIDTH_MASK 0x3F0
2209#define PCI_EX_LINK_WIDTH_SHIFT 4
2210
2211
2212#define EEPROM_READ_OPCODE_MICROWIRE 0x6
2213#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5
2214#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7
2215#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13
2216#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10
2217
2218
2219#define EEPROM_MAX_RETRY_SPI 5000
2220#define EEPROM_READ_OPCODE_SPI 0x03
2221#define EEPROM_WRITE_OPCODE_SPI 0x02
2222#define EEPROM_A8_OPCODE_SPI 0x08
2223#define EEPROM_WREN_OPCODE_SPI 0x06
2224#define EEPROM_WRDI_OPCODE_SPI 0x04
2225#define EEPROM_RDSR_OPCODE_SPI 0x05
2226#define EEPROM_WRSR_OPCODE_SPI 0x01
2227#define EEPROM_ERASE4K_OPCODE_SPI 0x20
2228#define EEPROM_ERASE64K_OPCODE_SPI 0xD8
2229#define EEPROM_ERASE256_OPCODE_SPI 0xDB
2230
2231
2232#define EEPROM_WORD_SIZE_SHIFT 6
2233#define EEPROM_SIZE_SHIFT 10
2234#define EEPROM_SIZE_MASK 0x1C00
2235
2236
2237#define EEPROM_COMPAT 0x0003
2238#define EEPROM_ID_LED_SETTINGS 0x0004
2239#define EEPROM_VERSION 0x0005
2240#define EEPROM_SERDES_AMPLITUDE 0x0006
2241#define EEPROM_PHY_CLASS_WORD 0x0007
2242#define EEPROM_INIT_CONTROL1_REG 0x000A
2243#define EEPROM_INIT_CONTROL2_REG 0x000F
2244#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2245#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2246#define EEPROM_INIT_3GIO_3 0x001A
2247#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2248#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2249#define EEPROM_CFG 0x0012
2250#define EEPROM_FLASH_VERSION 0x0032
2251#define EEPROM_CHECKSUM_REG 0x003F
2252
2253#define E1000_EEPROM_CFG_DONE 0x00040000
2254#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000
2255
2256
2257#define ID_LED_RESERVED_0000 0x0000
2258#define ID_LED_RESERVED_FFFF 0xFFFF
2259#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2260 (ID_LED_OFF1_OFF2 << 8) | \
2261 (ID_LED_DEF1_DEF2 << 4) | \
2262 (ID_LED_DEF1_DEF2))
2263#define ID_LED_DEF1_DEF2 0x1
2264#define ID_LED_DEF1_ON2 0x2
2265#define ID_LED_DEF1_OFF2 0x3
2266#define ID_LED_ON1_DEF2 0x4
2267#define ID_LED_ON1_ON2 0x5
2268#define ID_LED_ON1_OFF2 0x6
2269#define ID_LED_OFF1_DEF2 0x7
2270#define ID_LED_OFF1_ON2 0x8
2271#define ID_LED_OFF1_OFF2 0x9
2272
2273#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2274#define IGP_ACTIVITY_LED_ENABLE 0x0300
2275#define IGP_LED3_MODE 0x07000000
2276
2277
2278#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2279
2280
2281#define EEPROM_PHY_CLASS_A 0x8000
2282
2283
2284#define EEPROM_WORD0A_ILOS 0x0010
2285#define EEPROM_WORD0A_SWDPIO 0x01E0
2286#define EEPROM_WORD0A_LRST 0x0200
2287#define EEPROM_WORD0A_FD 0x0400
2288#define EEPROM_WORD0A_66MHZ 0x0800
2289
2290
2291#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2292#define EEPROM_WORD0F_PAUSE 0x1000
2293#define EEPROM_WORD0F_ASM_DIR 0x2000
2294#define EEPROM_WORD0F_ANE 0x0800
2295#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2296#define EEPROM_WORD0F_LPLU 0x0001
2297
2298
2299#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2300#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2301
2302
2303#define EEPROM_WORD1A_ASPM_MASK 0x000C
2304
2305
2306#define EEPROM_SUM 0xBABA
2307
2308
2309#define EEPROM_NODE_ADDRESS_BYTE_0 0
2310#define EEPROM_PBA_BYTE_1 8
2311
2312#define EEPROM_RESERVED_WORD 0xFFFF
2313
2314
2315#define PBA_SIZE 4
2316
2317
2318#define E1000_COLLISION_THRESHOLD 15
2319#define E1000_CT_SHIFT 4
2320
2321
2322#define E1000_COLLISION_DISTANCE 63
2323#define E1000_COLLISION_DISTANCE_82542 64
2324#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2325#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2326#define E1000_COLD_SHIFT 12
2327
2328
2329#define REQ_TX_DESCRIPTOR_MULTIPLE 8
2330#define REQ_RX_DESCRIPTOR_MULTIPLE 8
2331
2332
2333#define DEFAULT_82542_TIPG_IPGT 10
2334#define DEFAULT_82543_TIPG_IPGT_FIBER 9
2335#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2336
2337#define E1000_TIPG_IPGT_MASK 0x000003FF
2338#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2339#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2340
2341#define DEFAULT_82542_TIPG_IPGR1 2
2342#define DEFAULT_82543_TIPG_IPGR1 8
2343#define E1000_TIPG_IPGR1_SHIFT 10
2344
2345#define DEFAULT_82542_TIPG_IPGR2 10
2346#define DEFAULT_82543_TIPG_IPGR2 6
2347#define E1000_TIPG_IPGR2_SHIFT 20
2348
2349#define E1000_TXDMAC_DPP 0x00000001
2350
2351
2352#define TX_THRESHOLD_START 8
2353#define TX_THRESHOLD_INCREMENT 10
2354#define TX_THRESHOLD_DECREMENT 1
2355#define TX_THRESHOLD_STOP 190
2356#define TX_THRESHOLD_DISABLE 0
2357#define TX_THRESHOLD_TIMER_MS 10000
2358#define MIN_NUM_XMITS 1000
2359#define IFS_MAX 80
2360#define IFS_STEP 10
2361#define IFS_MIN 40
2362#define IFS_RATIO 4
2363
2364
2365#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2366#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2367#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2368#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2369#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2370#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2371#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2372#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2373
2374#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2375#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2376#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2377#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2378#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2379
2380
2381#define E1000_PBA_8K 0x0008
2382#define E1000_PBA_12K 0x000C
2383#define E1000_PBA_16K 0x0010
2384#define E1000_PBA_20K 0x0014
2385#define E1000_PBA_22K 0x0016
2386#define E1000_PBA_24K 0x0018
2387#define E1000_PBA_30K 0x001E
2388#define E1000_PBA_32K 0x0020
2389#define E1000_PBA_34K 0x0022
2390#define E1000_PBA_38K 0x0026
2391#define E1000_PBA_40K 0x0028
2392#define E1000_PBA_48K 0x0030
2393
2394#define E1000_PBS_16K E1000_PBA_16K
2395
2396
2397#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2398#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2399#define FLOW_CONTROL_TYPE 0x8808
2400
2401
2402#define FC_DEFAULT_HI_THRESH (0x8000)
2403#define FC_DEFAULT_LO_THRESH (0x4000)
2404#define FC_DEFAULT_TX_TIMER (0x100)
2405
2406
2407#define PCIX_COMMAND_REGISTER 0xE6
2408#define PCIX_STATUS_REGISTER_LO 0xE8
2409#define PCIX_STATUS_REGISTER_HI 0xEA
2410
2411#define PCIX_COMMAND_MMRBC_MASK 0x000C
2412#define PCIX_COMMAND_MMRBC_SHIFT 0x2
2413#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2414#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2415#define PCIX_STATUS_HI_MMRBC_4K 0x3
2416#define PCIX_STATUS_HI_MMRBC_2K 0x2
2417
2418
2419
2420
2421#define PAUSE_SHIFT 5
2422
2423
2424
2425
2426#define SWDPIO_SHIFT 17
2427
2428
2429
2430
2431#define SWDPIO__EXT_SHIFT 4
2432
2433
2434
2435
2436#define ILOS_SHIFT 3
2437
2438#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2439
2440
2441#define LINK_UP_TIMEOUT 500
2442
2443
2444#define AUTO_READ_DONE_TIMEOUT 10
2445
2446#define PHY_CFG_TIMEOUT 100
2447
2448#define E1000_TX_BUFFER_SIZE ((u32)1514)
2449
2450
2451#define CARRIER_EXTENSION 0x0F
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2481 ((adapter)->tbi_compatibility_on && \
2482 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2483 ((last_byte) == CARRIER_EXTENSION) && \
2484 (((status) & E1000_RXD_STAT_VP) ? \
2485 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2486 ((length) <= ((adapter)->max_frame_size + 1))) : \
2487 (((length) > (adapter)->min_frame_size) && \
2488 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2489
2490
2491
2492
2493
2494
2495#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2496#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2497#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2498#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2499#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2500#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2501#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2502#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2503
2504
2505
2506#define PHY_CTRL 0x00
2507#define PHY_STATUS 0x01
2508#define PHY_ID1 0x02
2509#define PHY_ID2 0x03
2510#define PHY_AUTONEG_ADV 0x04
2511#define PHY_LP_ABILITY 0x05
2512#define PHY_AUTONEG_EXP 0x06
2513#define PHY_NEXT_PAGE_TX 0x07
2514#define PHY_LP_NEXT_PAGE 0x08
2515#define PHY_1000T_CTRL 0x09
2516#define PHY_1000T_STATUS 0x0A
2517#define PHY_EXT_STATUS 0x0F
2518
2519#define MAX_PHY_REG_ADDRESS 0x1F
2520#define MAX_PHY_MULTI_PAGE_REG 0xF
2521
2522
2523#define M88E1000_PHY_SPEC_CTRL 0x10
2524#define M88E1000_PHY_SPEC_STATUS 0x11
2525#define M88E1000_INT_ENABLE 0x12
2526#define M88E1000_INT_STATUS 0x13
2527#define M88E1000_EXT_PHY_SPEC_CTRL 0x14
2528#define M88E1000_RX_ERR_CNTR 0x15
2529
2530#define M88E1000_PHY_EXT_CTRL 0x1A
2531#define M88E1000_PHY_PAGE_SELECT 0x1D
2532#define M88E1000_PHY_GEN_CONTROL 0x1E
2533#define M88E1000_PHY_VCO_REG_BIT8 0x100
2534#define M88E1000_PHY_VCO_REG_BIT11 0x800
2535
2536#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2537#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2538#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2539
2540
2541#define IGP01E1000_PHY_PORT_CONFIG 0x10
2542#define IGP01E1000_PHY_PORT_STATUS 0x11
2543#define IGP01E1000_PHY_PORT_CTRL 0x12
2544#define IGP01E1000_PHY_LINK_HEALTH 0x13
2545#define IGP01E1000_GMII_FIFO 0x14
2546#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15
2547#define IGP02E1000_PHY_POWER_MGMT 0x19
2548#define IGP01E1000_PHY_PAGE_SELECT 0x1F
2549
2550
2551#define IGP01E1000_PHY_AGC_A 0x1172
2552#define IGP01E1000_PHY_AGC_B 0x1272
2553#define IGP01E1000_PHY_AGC_C 0x1472
2554#define IGP01E1000_PHY_AGC_D 0x1872
2555
2556
2557#define IGP02E1000_PHY_AGC_A 0x11B1
2558#define IGP02E1000_PHY_AGC_B 0x12B1
2559#define IGP02E1000_PHY_AGC_C 0x14B1
2560#define IGP02E1000_PHY_AGC_D 0x18B1
2561
2562
2563#define IGP01E1000_PHY_DSP_RESET 0x1F33
2564#define IGP01E1000_PHY_DSP_SET 0x1F71
2565#define IGP01E1000_PHY_DSP_FFE 0x1F35
2566
2567#define IGP01E1000_PHY_CHANNEL_NUM 4
2568#define IGP02E1000_PHY_CHANNEL_NUM 4
2569
2570#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2571#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2572#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2573#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2574
2575#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2576#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2577
2578#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2579#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2580#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2581#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2582
2583#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2584
2585
2586#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2587#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2588
2589#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2590
2591
2592#define MII_CR_SPEED_SELECT_MSB 0x0040
2593#define MII_CR_COLL_TEST_ENABLE 0x0080
2594#define MII_CR_FULL_DUPLEX 0x0100
2595#define MII_CR_RESTART_AUTO_NEG 0x0200
2596#define MII_CR_ISOLATE 0x0400
2597#define MII_CR_POWER_DOWN 0x0800
2598#define MII_CR_AUTO_NEG_EN 0x1000
2599#define MII_CR_SPEED_SELECT_LSB 0x2000
2600#define MII_CR_LOOPBACK 0x4000
2601#define MII_CR_RESET 0x8000
2602
2603
2604#define MII_SR_EXTENDED_CAPS 0x0001
2605#define MII_SR_JABBER_DETECT 0x0002
2606#define MII_SR_LINK_STATUS 0x0004
2607#define MII_SR_AUTONEG_CAPS 0x0008
2608#define MII_SR_REMOTE_FAULT 0x0010
2609#define MII_SR_AUTONEG_COMPLETE 0x0020
2610#define MII_SR_PREAMBLE_SUPPRESS 0x0040
2611#define MII_SR_EXTENDED_STATUS 0x0100
2612#define MII_SR_100T2_HD_CAPS 0x0200
2613#define MII_SR_100T2_FD_CAPS 0x0400
2614#define MII_SR_10T_HD_CAPS 0x0800
2615#define MII_SR_10T_FD_CAPS 0x1000
2616#define MII_SR_100X_HD_CAPS 0x2000
2617#define MII_SR_100X_FD_CAPS 0x4000
2618#define MII_SR_100T4_CAPS 0x8000
2619
2620
2621#define NWAY_AR_SELECTOR_FIELD 0x0001
2622#define NWAY_AR_10T_HD_CAPS 0x0020
2623#define NWAY_AR_10T_FD_CAPS 0x0040
2624#define NWAY_AR_100TX_HD_CAPS 0x0080
2625#define NWAY_AR_100TX_FD_CAPS 0x0100
2626#define NWAY_AR_100T4_CAPS 0x0200
2627#define NWAY_AR_PAUSE 0x0400
2628#define NWAY_AR_ASM_DIR 0x0800
2629#define NWAY_AR_REMOTE_FAULT 0x2000
2630#define NWAY_AR_NEXT_PAGE 0x8000
2631
2632
2633#define NWAY_LPAR_SELECTOR_FIELD 0x0000
2634#define NWAY_LPAR_10T_HD_CAPS 0x0020
2635#define NWAY_LPAR_10T_FD_CAPS 0x0040
2636#define NWAY_LPAR_100TX_HD_CAPS 0x0080
2637#define NWAY_LPAR_100TX_FD_CAPS 0x0100
2638#define NWAY_LPAR_100T4_CAPS 0x0200
2639#define NWAY_LPAR_PAUSE 0x0400
2640#define NWAY_LPAR_ASM_DIR 0x0800
2641#define NWAY_LPAR_REMOTE_FAULT 0x2000
2642#define NWAY_LPAR_ACKNOWLEDGE 0x4000
2643#define NWAY_LPAR_NEXT_PAGE 0x8000
2644
2645
2646#define NWAY_ER_LP_NWAY_CAPS 0x0001
2647#define NWAY_ER_PAGE_RXD 0x0002
2648#define NWAY_ER_NEXT_PAGE_CAPS 0x0004
2649#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008
2650#define NWAY_ER_PAR_DETECT_FAULT 0x0010
2651
2652
2653#define NPTX_MSG_CODE_FIELD 0x0001
2654#define NPTX_TOGGLE 0x0800
2655
2656
2657#define NPTX_ACKNOWLDGE2 0x1000
2658
2659
2660#define NPTX_MSG_PAGE 0x2000
2661#define NPTX_NEXT_PAGE 0x8000
2662
2663
2664
2665
2666#define LP_RNPR_MSG_CODE_FIELD 0x0001
2667#define LP_RNPR_TOGGLE 0x0800
2668
2669
2670#define LP_RNPR_ACKNOWLDGE2 0x1000
2671
2672
2673#define LP_RNPR_MSG_PAGE 0x2000
2674#define LP_RNPR_ACKNOWLDGE 0x4000
2675#define LP_RNPR_NEXT_PAGE 0x8000
2676
2677
2678
2679
2680#define CR_1000T_ASYM_PAUSE 0x0080
2681#define CR_1000T_HD_CAPS 0x0100
2682#define CR_1000T_FD_CAPS 0x0200
2683#define CR_1000T_REPEATER_DTE 0x0400
2684
2685#define CR_1000T_MS_VALUE 0x0800
2686
2687#define CR_1000T_MS_ENABLE 0x1000
2688
2689#define CR_1000T_TEST_MODE_NORMAL 0x0000
2690#define CR_1000T_TEST_MODE_1 0x2000
2691#define CR_1000T_TEST_MODE_2 0x4000
2692#define CR_1000T_TEST_MODE_3 0x6000
2693#define CR_1000T_TEST_MODE_4 0x8000
2694
2695
2696#define SR_1000T_IDLE_ERROR_CNT 0x00FF
2697#define SR_1000T_ASYM_PAUSE_DIR 0x0100
2698#define SR_1000T_LP_HD_CAPS 0x0400
2699#define SR_1000T_LP_FD_CAPS 0x0800
2700#define SR_1000T_REMOTE_RX_STATUS 0x1000
2701#define SR_1000T_LOCAL_RX_STATUS 0x2000
2702#define SR_1000T_MS_CONFIG_RES 0x4000
2703#define SR_1000T_MS_CONFIG_FAULT 0x8000
2704#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2705#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2706#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2707#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2708#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2709
2710
2711#define IEEE_ESR_1000T_HD_CAPS 0x1000
2712#define IEEE_ESR_1000T_FD_CAPS 0x2000
2713#define IEEE_ESR_1000X_HD_CAPS 0x4000
2714#define IEEE_ESR_1000X_FD_CAPS 0x8000
2715
2716#define PHY_TX_POLARITY_MASK 0x0100
2717#define PHY_TX_NORMAL_POLARITY 0
2718
2719#define AUTO_POLARITY_DISABLE 0x0010
2720
2721
2722
2723#define M88E1000_PSCR_JABBER_DISABLE 0x0001
2724#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
2725#define M88E1000_PSCR_SQE_TEST 0x0004
2726#define M88E1000_PSCR_CLK125_DISABLE 0x0010
2727
2728
2729#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
2730
2731#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
2732#define M88E1000_PSCR_AUTO_X_1000T 0x0040
2733
2734
2735
2736#define M88E1000_PSCR_AUTO_X_MODE 0x0060
2737
2738
2739#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2740
2741
2742
2743#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2744
2745
2746#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200
2747#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400
2748#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
2749
2750#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2751#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2752#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2753
2754
2755#define M88E1000_PSSR_JABBER 0x0001
2756#define M88E1000_PSSR_REV_POLARITY 0x0002
2757#define M88E1000_PSSR_DOWNSHIFT 0x0020
2758#define M88E1000_PSSR_MDIX 0x0040
2759#define M88E1000_PSSR_CABLE_LENGTH 0x0380
2760
2761#define M88E1000_PSSR_LINK 0x0400
2762#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800
2763#define M88E1000_PSSR_PAGE_RCVD 0x1000
2764#define M88E1000_PSSR_DPLX 0x2000
2765#define M88E1000_PSSR_SPEED 0xC000
2766#define M88E1000_PSSR_10MBS 0x0000
2767#define M88E1000_PSSR_100MBS 0x4000
2768#define M88E1000_PSSR_1000MBS 0x8000
2769
2770#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2771#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2772#define M88E1000_PSSR_MDIX_SHIFT 6
2773#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2774
2775
2776#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000
2777#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
2778
2779
2780
2781
2782
2783
2784#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2785#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2786#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2787#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2788#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2789
2790
2791#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2792#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2793#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2794#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2795#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2796#define M88E1000_EPSCR_TX_CLK_2_5 0x0060
2797#define M88E1000_EPSCR_TX_CLK_25 0x0070
2798#define M88E1000_EPSCR_TX_CLK_0 0x0000
2799
2800
2801#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2802#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2803#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2804#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2805#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2806#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2807#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2808#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2809#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2810
2811
2812#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2813#define IGP01E1000_PSCFR_PRE_EN 0x0020
2814#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2815#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2816#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2817#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2818
2819
2820#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001
2821#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2822#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2823#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2824#define IGP01E1000_PSSR_LINK_UP 0x0400
2825#define IGP01E1000_PSSR_MDIX 0x0800
2826#define IGP01E1000_PSSR_SPEED_MASK 0xC000
2827#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2828#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2829#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2830#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002
2831#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B
2832
2833
2834#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2835#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2836#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2837#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2838#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2839#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000
2840
2841
2842#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2843#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2844#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2845#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2846#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800
2847#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400
2848#define IGP01E1000_PLHR_DATA_ERR_1 0x0200
2849#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2850#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2851#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2852#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2853#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2854#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2855#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2856
2857
2858#define IGP01E1000_MSE_CHANNEL_D 0x000F
2859#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2860#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2861#define IGP01E1000_MSE_CHANNEL_A 0xF000
2862
2863#define IGP02E1000_PM_SPD 0x0001
2864#define IGP02E1000_PM_D3_LPLU 0x0004
2865#define IGP02E1000_PM_D0_LPLU 0x0002
2866
2867
2868#define DSP_RESET_ENABLE 0x0
2869#define DSP_RESET_DISABLE 0x2
2870#define E1000_MAX_DSP_RESETS 10
2871
2872
2873
2874#define IGP01E1000_AGC_LENGTH_SHIFT 7
2875#define IGP02E1000_AGC_LENGTH_SHIFT 9
2876
2877
2878#define IGP02E1000_AGC_LENGTH_MASK 0x7F
2879
2880
2881#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2882#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
2883
2884
2885#define IGP01E1000_AGC_RANGE 10
2886#define IGP02E1000_AGC_RANGE 15
2887
2888
2889
2890#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2891
2892
2893#define IGP01E1000_GMII_FLEX_SPD 0x10
2894
2895#define IGP01E1000_GMII_SPD 0x20
2896
2897
2898#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2899#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2900#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2901#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2902
2903#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2904#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2905#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2906#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2907#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2908
2909#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2910#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2911#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2912#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2913
2914
2915
2916
2917
2918#define M88_VENDOR 0x0141
2919#define M88E1000_E_PHY_ID 0x01410C50
2920#define M88E1000_I_PHY_ID 0x01410C30
2921#define M88E1011_I_PHY_ID 0x01410C20
2922#define IGP01E1000_I_PHY_ID 0x02A80380
2923#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2924#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2925#define M88E1011_I_REV_4 0x04
2926#define M88E1111_I_PHY_ID 0x01410CC0
2927#define M88E1118_E_PHY_ID 0x01410E40
2928#define L1LXT971A_PHY_ID 0x001378E0
2929
2930#define RTL8211B_PHY_ID 0x001CC910
2931#define RTL8201N_PHY_ID 0x8200
2932#define RTL_PHY_CTRL_FD 0x0100
2933#define RTL_PHY_CTRL_SPD_100 0x200000
2934
2935
2936
2937
2938
2939#define PHY_PAGE_SHIFT 5
2940#define PHY_REG(page, reg) \
2941 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2942
2943#define IGP3_PHY_PORT_CTRL \
2944 PHY_REG(769, 17)
2945#define IGP3_PHY_RATE_ADAPT_CTRL \
2946 PHY_REG(769, 25)
2947
2948#define IGP3_KMRN_FIFO_CTRL_STATS \
2949 PHY_REG(770, 16)
2950#define IGP3_KMRN_POWER_MNG_CTRL \
2951 PHY_REG(770, 17)
2952#define IGP3_KMRN_INBAND_CTRL \
2953 PHY_REG(770, 18)
2954#define IGP3_KMRN_DIAG \
2955 PHY_REG(770, 19)
2956#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
2957#define IGP3_KMRN_ACK_TIMEOUT \
2958 PHY_REG(770, 20)
2959
2960#define IGP3_VR_CTRL \
2961 PHY_REG(776, 18)
2962#define IGP3_VR_CTRL_MODE_SHUT 0x0200
2963#define IGP3_VR_CTRL_MODE_MASK 0x0300
2964
2965#define IGP3_CAPABILITY \
2966 PHY_REG(776, 19)
2967
2968
2969#define IGP3_CAP_INITIATE_TEAM 0x0001
2970#define IGP3_CAP_WFM 0x0002
2971#define IGP3_CAP_ASF 0x0004
2972#define IGP3_CAP_LPLU 0x0008
2973#define IGP3_CAP_DC_AUTO_SPEED 0x0010
2974#define IGP3_CAP_SPD 0x0020
2975#define IGP3_CAP_MULT_QUEUE 0x0040
2976#define IGP3_CAP_RSS 0x0080
2977#define IGP3_CAP_8021PQ 0x0100
2978#define IGP3_CAP_AMT_CB 0x0200
2979
2980#define IGP3_PPC_JORDAN_EN 0x0001
2981#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
2982
2983#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
2984#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
2985#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
2986#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
2987
2988#define IGP3E1000_PHY_MISC_CTRL 0x1B
2989#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000
2990
2991#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
2992#define IGP3_KMRN_EC_DIS_INBAND 0x0080
2993
2994#define IGP03E1000_E_PHY_ID 0x02A80390
2995#define IFE_E_PHY_ID 0x02A80330
2996#define IFE_PLUS_E_PHY_ID 0x02A80320
2997#define IFE_C_E_PHY_ID 0x02A80310
2998
2999#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
3000#define IFE_PHY_SPECIAL_CONTROL 0x11
3001#define IFE_PHY_RCV_FALSE_CARRIER 0x13
3002#define IFE_PHY_RCV_DISCONNECT 0x14
3003#define IFE_PHY_RCV_ERROT_FRAME 0x15
3004#define IFE_PHY_RCV_SYMBOL_ERR 0x16
3005#define IFE_PHY_PREM_EOF_ERR 0x17
3006#define IFE_PHY_RCV_EOF_ERR 0x18
3007#define IFE_PHY_TX_JABBER_DETECT 0x19
3008#define IFE_PHY_EQUALIZER 0x1A
3009#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B
3010#define IFE_PHY_MDIX_CONTROL 0x1C
3011#define IFE_PHY_HWI_CONTROL 0x1D
3012
3013#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000
3014#define IFE_PESC_100BTX_POWER_DOWN 0x0400
3015#define IFE_PESC_10BTX_POWER_DOWN 0x0200
3016#define IFE_PESC_POLARITY_REVERSED 0x0100
3017#define IFE_PESC_PHY_ADDR_MASK 0x007C
3018#define IFE_PESC_SPEED 0x0002
3019#define IFE_PESC_DUPLEX 0x0001
3020#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3021
3022#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
3023#define IFE_PSC_FORCE_POLARITY 0x0020
3024#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
3025#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001
3026#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3027#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3028
3029#define IFE_PMC_AUTO_MDIX 0x0080
3030#define IFE_PMC_FORCE_MDIX 0x0040
3031#define IFE_PMC_MDIX_STATUS 0x0020
3032#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010
3033#define IFE_PMC_MDIX_MODE_SHIFT 6
3034#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000
3035
3036#define IFE_PHC_HWI_ENABLE 0x8000
3037#define IFE_PHC_ABILITY_CHECK 0x4000
3038#define IFE_PHC_TEST_EXEC 0x2000
3039#define IFE_PHC_HIGHZ 0x0200
3040#define IFE_PHC_LOWZ 0x0400
3041#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600
3042#define IFE_PHC_DISTANCE_MASK 0x01FF
3043#define IFE_PHC_RESET_ALL_MASK 0x0000
3044#define IFE_PSCL_PROBE_MODE 0x0020
3045#define IFE_PSCL_PROBE_LEDS_OFF 0x0006
3046#define IFE_PSCL_PROBE_LEDS_ON 0x0007
3047
3048#define ICH_FLASH_COMMAND_TIMEOUT 5000
3049#define ICH_FLASH_ERASE_TIMEOUT 3000000
3050#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
3051#define ICH_FLASH_SEG_SIZE_256 256
3052#define ICH_FLASH_SEG_SIZE_4K 4096
3053#define ICH_FLASH_SEG_SIZE_64K 65536
3054
3055#define ICH_CYCLE_READ 0x0
3056#define ICH_CYCLE_RESERVED 0x1
3057#define ICH_CYCLE_WRITE 0x2
3058#define ICH_CYCLE_ERASE 0x3
3059
3060#define ICH_FLASH_GFPREG 0x0000
3061#define ICH_FLASH_HSFSTS 0x0004
3062#define ICH_FLASH_HSFCTL 0x0006
3063#define ICH_FLASH_FADDR 0x0008
3064#define ICH_FLASH_FDATA0 0x0010
3065#define ICH_FLASH_FRACC 0x0050
3066#define ICH_FLASH_FREG0 0x0054
3067#define ICH_FLASH_FREG1 0x0058
3068#define ICH_FLASH_FREG2 0x005C
3069#define ICH_FLASH_FREG3 0x0060
3070#define ICH_FLASH_FPR0 0x0074
3071#define ICH_FLASH_FPR1 0x0078
3072#define ICH_FLASH_SSFSTS 0x0090
3073#define ICH_FLASH_SSFCTL 0x0092
3074#define ICH_FLASH_PREOP 0x0094
3075#define ICH_FLASH_OPTYPE 0x0096
3076#define ICH_FLASH_OPMENU 0x0098
3077
3078#define ICH_FLASH_REG_MAPSIZE 0x00A0
3079#define ICH_FLASH_SECTOR_SIZE 4096
3080#define ICH_GFPREG_BASE_MASK 0x1FFF
3081#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3082
3083
3084#define PHY_PREAMBLE 0xFFFFFFFF
3085#define PHY_SOF 0x01
3086#define PHY_OP_READ 0x02
3087#define PHY_OP_WRITE 0x01
3088#define PHY_TURNAROUND 0x02
3089#define PHY_PREAMBLE_SIZE 32
3090#define MII_CR_SPEED_1000 0x0040
3091#define MII_CR_SPEED_100 0x2000
3092#define MII_CR_SPEED_10 0x0000
3093#define E1000_PHY_ADDRESS 0x01
3094#define PHY_AUTO_NEG_TIME 45
3095#define PHY_FORCE_TIME 20
3096#define PHY_REVISION_MASK 0xFFFFFFF0
3097#define DEVICE_SPEED_MASK 0x00000300
3098#define REG4_SPEED_MASK 0x01E0
3099#define REG9_SPEED_MASK 0x0300
3100#define ADVERTISE_10_HALF 0x0001
3101#define ADVERTISE_10_FULL 0x0002
3102#define ADVERTISE_100_HALF 0x0004
3103#define ADVERTISE_100_FULL 0x0008
3104#define ADVERTISE_1000_HALF 0x0010
3105#define ADVERTISE_1000_FULL 0x0020
3106#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F
3107#define AUTONEG_ADVERTISE_10_100_ALL 0x000F
3108#define AUTONEG_ADVERTISE_10_ALL 0x0003
3109
3110#endif
3111