LXR linux/drivers/net/wan/hd64570.c

   1/*
   2 * Hitachi SCA HD64570 driver for Linux
   3 *
   4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * Source of information: Hitachi HD64570 SCA User's Manual
  11 *
  12 * We use the following SCA memory map:
  13 *
  14 * Packet buffer descriptor rings - starting from winbase or win0base:
  15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
  16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
  17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
  18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
  19 *
  20 * Packet data buffers - starting from winbase + buff_offset:
  21 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers
  22 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers
  23 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers (if used)
  24 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers (if used)
  25 */
  26
  27#include <linux/bitops.h>
  28#include <linux/errno.h>
  29#include <linux/fcntl.h>
  30#include <linux/hdlc.h>
  31#include <linux/in.h>
  32#include <linux/interrupt.h>
  33#include <linux/ioport.h>
  34#include <linux/jiffies.h>
  35#include <linux/kernel.h>
  36#include <linux/module.h>
  37#include <linux/netdevice.h>
  38#include <linux/skbuff.h>
  39#include <linux/string.h>
  40#include <linux/types.h>
  41#include <asm/io.h>
  42#include <linux/uaccess.h>
  43#include "hd64570.h"
  44
  45#define get_msci(port)    (phy_node(port) ?   MSCI1_OFFSET :   MSCI0_OFFSET)
  46#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
  47#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
  48
  49#define SCA_INTR_MSCI(node)    (node ? 0x10 : 0x01)
  50#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
  51#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
  52
  53
  54static inline struct net_device *port_to_dev(port_t *port)
  55{
  56        return port->dev;
  57}
  58
  59static inline int sca_intr_status(card_t *card)
  60{
  61        u8 result = 0;
  62        u8 isr0 = sca_in(ISR0, card);
  63        u8 isr1 = sca_in(ISR1, card);
  64
  65        if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
  66        if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
  67        if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
  68        if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
  69        if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
  70        if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
  71
  72        if (!(result & SCA_INTR_DMAC_TX(0)))
  73                if (sca_in(DSR_TX(0), card) & DSR_EOM)
  74                        result |= SCA_INTR_DMAC_TX(0);
  75        if (!(result & SCA_INTR_DMAC_TX(1)))
  76                if (sca_in(DSR_TX(1), card) & DSR_EOM)
  77                        result |= SCA_INTR_DMAC_TX(1);
  78
  79        return result;
  80}
  81
  82static inline port_t* dev_to_port(struct net_device *dev)
  83{
  84        return dev_to_hdlc(dev)->priv;
  85}
  86
  87static inline u16 next_desc(port_t *port, u16 desc, int transmit)
  88{
  89        return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
  90                             : port_to_card(port)->rx_ring_buffers);
  91}
  92
  93
  94static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
  95{
  96        u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
  97        u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
  98
  99        desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
 100        return log_node(port) * (rx_buffs + tx_buffs) +
 101                transmit * rx_buffs + desc;
 102}
 103
 104
 105static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
 106{
 107        /* Descriptor offset always fits in 16 bits */
 108        return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
 109}
 110
 111
 112static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
 113                                             int transmit)
 114{
 115#ifdef PAGE0_ALWAYS_MAPPED
 116        return (pkt_desc __iomem *)(win0base(port_to_card(port))
 117                                    + desc_offset(port, desc, transmit));
 118#else
 119        return (pkt_desc __iomem *)(winbase(port_to_card(port))
 120                                    + desc_offset(port, desc, transmit));
 121#endif
 122}
 123
 124
 125static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
 126{
 127        return port_to_card(port)->buff_offset +
 128                desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
 129}
 130
 131
 132static inline void sca_set_carrier(port_t *port)
 133{
 134        if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
 135#ifdef DEBUG_LINK
 136                printk(KERN_DEBUG "%s: sca_set_carrier on\n",
 137                       port_to_dev(port)->name);
 138#endif
 139                netif_carrier_on(port_to_dev(port));
 140        } else {
 141#ifdef DEBUG_LINK
 142                printk(KERN_DEBUG "%s: sca_set_carrier off\n",
 143                       port_to_dev(port)->name);
 144#endif
 145                netif_carrier_off(port_to_dev(port));
 146        }
 147}
 148
 149
 150static void sca_init_port(port_t *port)
 151{
 152        card_t *card = port_to_card(port);
 153        int transmit, i;
 154
 155        port->rxin = 0;
 156        port->txin = 0;
 157        port->txlast = 0;
 158
 159#ifndef PAGE0_ALWAYS_MAPPED
 160        openwin(card, 0);
 161#endif
 162
 163        for (transmit = 0; transmit < 2; transmit++) {
 164                u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
 165                u16 buffs = transmit ? card->tx_ring_buffers
 166                        : card->rx_ring_buffers;
 167
 168                for (i = 0; i < buffs; i++) {
 169                        pkt_desc __iomem *desc = desc_address(port, i, transmit);
 170                        u16 chain_off = desc_offset(port, i + 1, transmit);
 171                        u32 buff_off = buffer_offset(port, i, transmit);
 172
 173                        writew(chain_off, &desc->cp);
 174                        writel(buff_off, &desc->bp);
 175                        writew(0, &desc->len);
 176                        writeb(0, &desc->stat);
 177                }
 178
 179                /* DMA disable - to halt state */
 180                sca_out(0, transmit ? DSR_TX(phy_node(port)) :
 181                        DSR_RX(phy_node(port)), card);
 182                /* software ABORT - to initial state */
 183                sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
 184                        DCR_RX(phy_node(port)), card);
 185
 186                /* current desc addr */
 187                sca_out(0, dmac + CPB, card); /* pointer base */
 188                sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
 189                if (!transmit)
 190                        sca_outw(desc_offset(port, buffs - 1, transmit),
 191                                 dmac + EDAL, card);
 192                else
 193                        sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
 194                                 card);
 195
 196                /* clear frame end interrupt counter */
 197                sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
 198                        DCR_RX(phy_node(port)), card);
 199
 200                if (!transmit) { /* Receive */
 201                        /* set buffer length */
 202                        sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
 203                        /* Chain mode, Multi-frame */
 204                        sca_out(0x14, DMR_RX(phy_node(port)), card);
 205                        sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
 206                                card);
 207                        /* DMA enable */
 208                        sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
 209                } else {        /* Transmit */
 210                        /* Chain mode, Multi-frame */
 211                        sca_out(0x14, DMR_TX(phy_node(port)), card);
 212                        /* enable underflow interrupts */
 213                        sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
 214                }
 215        }
 216        sca_set_carrier(port);
 217}
 218
 219
 220#ifdef NEED_SCA_MSCI_INTR
 221/* MSCI interrupt service */
 222static inline void sca_msci_intr(port_t *port)
 223{
 224        u16 msci = get_msci(port);
 225        card_t* card = port_to_card(port);
 226        u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
 227
 228        /* Reset MSCI TX underrun and CDCD status bit */
 229        sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
 230
 231        if (stat & ST1_UDRN) {
 232                /* TX Underrun error detected */
 233                port_to_dev(port)->stats.tx_errors++;
 234                port_to_dev(port)->stats.tx_fifo_errors++;
 235        }
 236
 237        if (stat & ST1_CDCD)
 238                sca_set_carrier(port);
 239}
 240#endif
 241
 242
 243static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
 244                          u16 rxin)
 245{
 246        struct net_device *dev = port_to_dev(port);
 247        struct sk_buff *skb;
 248        u16 len;
 249        u32 buff;
 250        u32 maxlen;
 251        u8 page;
 252
 253        len = readw(&desc->len);
 254        skb = dev_alloc_skb(len);
 255        if (!skb) {
 256                dev->stats.rx_dropped++;
 257                return;
 258        }
 259
 260        buff = buffer_offset(port, rxin, 0);
 261        page = buff / winsize(card);
 262        buff = buff % winsize(card);
 263        maxlen = winsize(card) - buff;
 264
 265        openwin(card, page);
 266
 267        if (len > maxlen) {
 268                memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
 269                openwin(card, page + 1);
 270                memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
 271        } else
 272                memcpy_fromio(skb->data, winbase(card) + buff, len);
 273
 274#ifndef PAGE0_ALWAYS_MAPPED
 275        openwin(card, 0);       /* select pkt_desc table page back */
 276#endif
 277        skb_put(skb, len);
 278#ifdef DEBUG_PKT
 279        printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
 280        debug_frame(skb);
 281#endif
 282        dev->stats.rx_packets++;
 283        dev->stats.rx_bytes += skb->len;
 284        skb->protocol = hdlc_type_trans(skb, dev);
 285        netif_rx(skb);
 286}
 287
 288
 289/* Receive DMA interrupt service */
 290static inline void sca_rx_intr(port_t *port)
 291{
 292        struct net_device *dev = port_to_dev(port);
 293        u16 dmac = get_dmac_rx(port);
 294        card_t *card = port_to_card(port);
 295        u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
 296
 297        /* Reset DSR status bits */
 298        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 299                DSR_RX(phy_node(port)), card);
 300
 301        if (stat & DSR_BOF)
 302                /* Dropped one or more frames */
 303                dev->stats.rx_over_errors++;
 304
 305        while (1) {
 306                u32 desc_off = desc_offset(port, port->rxin, 0);
 307                pkt_desc __iomem *desc;
 308                u32 cda = sca_inw(dmac + CDAL, card);
 309
 310                if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
 311                        break;  /* No frame received */
 312
 313                desc = desc_address(port, port->rxin, 0);
 314                stat = readb(&desc->stat);
 315                if (!(stat & ST_RX_EOM))
 316                        port->rxpart = 1; /* partial frame received */
 317                else if ((stat & ST_ERROR_MASK) || port->rxpart) {
 318                        dev->stats.rx_errors++;
 319                        if (stat & ST_RX_OVERRUN)
 320                                dev->stats.rx_fifo_errors++;
 321                        else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
 322                                          ST_RX_RESBIT)) || port->rxpart)
 323                                dev->stats.rx_frame_errors++;
 324                        else if (stat & ST_RX_CRC)
 325                                dev->stats.rx_crc_errors++;
 326                        if (stat & ST_RX_EOM)
 327                                port->rxpart = 0; /* received last fragment */
 328                } else
 329                        sca_rx(card, port, desc, port->rxin);
 330
 331                /* Set new error descriptor address */
 332                sca_outw(desc_off, dmac + EDAL, card);
 333                port->rxin = next_desc(port, port->rxin, 0);
 334        }
 335
 336        /* make sure RX DMA is enabled */
 337        sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
 338}
 339
 340
 341/* Transmit DMA interrupt service */
 342static inline void sca_tx_intr(port_t *port)
 343{
 344        struct net_device *dev = port_to_dev(port);
 345        u16 dmac = get_dmac_tx(port);
 346        card_t* card = port_to_card(port);
 347        u8 stat;
 348
 349        spin_lock(&port->lock);
 350
 351        stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
 352
 353        /* Reset DSR status bits */
 354        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 355                DSR_TX(phy_node(port)), card);
 356
 357        while (1) {
 358                pkt_desc __iomem *desc;
 359
 360                u32 desc_off = desc_offset(port, port->txlast, 1);
 361                u32 cda = sca_inw(dmac + CDAL, card);
 362                if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
 363                        break;  /* Transmitter is/will_be sending this frame */
 364
 365                desc = desc_address(port, port->txlast, 1);
 366                dev->stats.tx_packets++;
 367                dev->stats.tx_bytes += readw(&desc->len);
 368                writeb(0, &desc->stat); /* Free descriptor */
 369                port->txlast = next_desc(port, port->txlast, 1);
 370        }
 371
 372        netif_wake_queue(dev);
 373        spin_unlock(&port->lock);
 374}
 375
 376
 377static irqreturn_t sca_intr(int irq, void* dev_id)
 378{
 379        card_t *card = dev_id;
 380        int i;
 381        u8 stat;
 382        int handled = 0;
 383        u8 page = sca_get_page(card);
 384
 385        while((stat = sca_intr_status(card)) != 0) {
 386                handled = 1;
 387                for (i = 0; i < 2; i++) {
 388                        port_t *port = get_port(card, i);
 389                        if (port) {
 390                                if (stat & SCA_INTR_MSCI(i))
 391                                        sca_msci_intr(port);
 392
 393                                if (stat & SCA_INTR_DMAC_RX(i))
 394                                        sca_rx_intr(port);
 395
 396                                if (stat & SCA_INTR_DMAC_TX(i))
 397                                        sca_tx_intr(port);
 398                        }
 399                }
 400        }
 401
 402        openwin(card, page);            /* Restore original page */
 403        return IRQ_RETVAL(handled);
 404}
 405
 406
 407static void sca_set_port(port_t *port)
 408{
 409        card_t* card = port_to_card(port);
 410        u16 msci = get_msci(port);
 411        u8 md2 = sca_in(msci + MD2, card);
 412        unsigned int tmc, br = 10, brv = 1024;
 413
 414
 415        if (port->settings.clock_rate > 0) {
 416                /* Try lower br for better accuracy*/
 417                do {
 418                        br--;
 419                        brv >>= 1; /* brv = 2^9 = 512 max in specs */
 420
 421                        /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
 422                        tmc = CLOCK_BASE / brv / port->settings.clock_rate;
 423                }while (br > 1 && tmc <= 128);
 424
 425                if (tmc < 1) {
 426                        tmc = 1;
 427                        br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
 428                        brv = 1;
 429                } else if (tmc > 255)
 430                        tmc = 256; /* tmc=0 means 256 - low baud rates */
 431
 432                port->settings.clock_rate = CLOCK_BASE / brv / tmc;
 433        } else {
 434                br = 9; /* Minimum clock rate */
 435                tmc = 256;      /* 8bit = 0 */
 436                port->settings.clock_rate = CLOCK_BASE / (256 * 512);
 437        }
 438
 439        port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
 440        port->txs = (port->txs & ~CLK_BRG_MASK) | br;
 441        port->tmc = tmc;
 442
 443        /* baud divisor - time constant*/
 444        sca_out(port->tmc, msci + TMC, card);
 445
 446        /* Set BRG bits */
 447        sca_out(port->rxs, msci + RXS, card);
 448        sca_out(port->txs, msci + TXS, card);
 449
 450        if (port->settings.loopback)
 451                md2 |= MD2_LOOPBACK;
 452        else
 453                md2 &= ~MD2_LOOPBACK;
 454
 455        sca_out(md2, msci + MD2, card);
 456
 457}
 458
 459
 460static void sca_open(struct net_device *dev)
 461{
 462        port_t *port = dev_to_port(dev);
 463        card_t* card = port_to_card(port);
 464        u16 msci = get_msci(port);
 465        u8 md0, md2;
 466
 467        switch(port->encoding) {
 468        case ENCODING_NRZ:      md2 = MD2_NRZ;          break;
 469        case ENCODING_NRZI:     md2 = MD2_NRZI;         break;
 470        case ENCODING_FM_MARK:  md2 = MD2_FM_MARK;      break;
 471        case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE;     break;
 472        default:                md2 = MD2_MANCHESTER;
 473        }
 474
 475        if (port->settings.loopback)
 476                md2 |= MD2_LOOPBACK;
 477
 478        switch(port->parity) {
 479        case PARITY_CRC16_PR0:       md0 = MD0_HDLC | MD0_CRC_16_0;  break;
 480        case PARITY_CRC16_PR1:       md0 = MD0_HDLC | MD0_CRC_16;    break;
 481        case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
 482        case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU;   break;
 483        default:                     md0 = MD0_HDLC | MD0_CRC_NONE;
 484        }
 485
 486        sca_out(CMD_RESET, msci + CMD, card);
 487        sca_out(md0, msci + MD0, card);
 488        sca_out(0x00, msci + MD1, card); /* no address field check */
 489        sca_out(md2, msci + MD2, card);
 490        sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
 491        sca_out(CTL_IDLE, msci + CTL, card);
 492
 493        /* Allow at least 8 bytes before requesting RX DMA operation */
 494        /* TX with higher priority and possibly with shorter transfers */
 495        sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
 496        sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
 497        sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
 498
 499/* We're using the following interrupts:
 500   - TXINT (DMAC completed all transmisions, underrun or DCD change)
 501   - all DMA interrupts
 502*/
 503        sca_set_carrier(port);
 504
 505        /* MSCI TX INT and RX INT A IRQ enable */
 506        sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
 507        sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
 508        sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
 509                IER0, card); /* TXINT and RXINT */
 510        /* enable DMA IRQ */
 511        sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
 512                IER1, card);
 513
 514        sca_out(port->tmc, msci + TMC, card); /* Restore registers */
 515        sca_out(port->rxs, msci + RXS, card);
 516        sca_out(port->txs, msci + TXS, card);
 517        sca_out(CMD_TX_ENABLE, msci + CMD, card);
 518        sca_out(CMD_RX_ENABLE, msci + CMD, card);
 519
 520        netif_start_queue(dev);
 521}
 522
 523
 524static void sca_close(struct net_device *dev)
 525{
 526        port_t *port = dev_to_port(dev);
 527        card_t* card = port_to_card(port);
 528
 529        /* reset channel */
 530        sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
 531        /* disable MSCI interrupts */
 532        sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
 533                IER0, card);
 534        /* disable DMA interrupts */
 535        sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
 536                IER1, card);
 537
 538        netif_stop_queue(dev);
 539}
 540
 541
 542static int sca_attach(struct net_device *dev, unsigned short encoding,
 543                      unsigned short parity)
 544{
 545        if (encoding != ENCODING_NRZ &&
 546            encoding != ENCODING_NRZI &&
 547            encoding != ENCODING_FM_MARK &&
 548            encoding != ENCODING_FM_SPACE &&
 549            encoding != ENCODING_MANCHESTER)
 550                return -EINVAL;
 551
 552        if (parity != PARITY_NONE &&
 553            parity != PARITY_CRC16_PR0 &&
 554            parity != PARITY_CRC16_PR1 &&
 555            parity != PARITY_CRC16_PR0_CCITT &&
 556            parity != PARITY_CRC16_PR1_CCITT)
 557                return -EINVAL;
 558
 559        dev_to_port(dev)->encoding = encoding;
 560        dev_to_port(dev)->parity = parity;
 561        return 0;
 562}
 563
 564
 565#ifdef DEBUG_RINGS
 566static void sca_dump_rings(struct net_device *dev)
 567{
 568        port_t *port = dev_to_port(dev);
 569        card_t *card = port_to_card(port);
 570        u16 cnt;
 571#ifndef PAGE0_ALWAYS_MAPPED
 572        u8 page = sca_get_page(card);
 573
 574        openwin(card, 0);
 575#endif
 576
 577        printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
 578               sca_inw(get_dmac_rx(port) + CDAL, card),
 579               sca_inw(get_dmac_rx(port) + EDAL, card),
 580               sca_in(DSR_RX(phy_node(port)), card), port->rxin,
 581               sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
 582        for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
 583                pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
 584        pr_cont("\n");
 585
 586        printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
 587               "last=%u %sactive",
 588               sca_inw(get_dmac_tx(port) + CDAL, card),
 589               sca_inw(get_dmac_tx(port) + EDAL, card),
 590               sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
 591               sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
 592
 593        for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
 594                pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
 595        pr_cont("\n");
 596
 597        printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x,"
 598               " FST: %02x CST: %02x %02x\n",
 599               sca_in(get_msci(port) + MD0, card),
 600               sca_in(get_msci(port) + MD1, card),
 601               sca_in(get_msci(port) + MD2, card),
 602               sca_in(get_msci(port) + ST0, card),
 603               sca_in(get_msci(port) + ST1, card),
 604               sca_in(get_msci(port) + ST2, card),
 605               sca_in(get_msci(port) + ST3, card),
 606               sca_in(get_msci(port) + FST, card),
 607               sca_in(get_msci(port) + CST0, card),
 608               sca_in(get_msci(port) + CST1, card));
 609
 610        printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
 611               sca_in(ISR1, card), sca_in(ISR2, card));
 612
 613#ifndef PAGE0_ALWAYS_MAPPED
 614        openwin(card, page); /* Restore original page */
 615#endif
 616}
 617#endif /* DEBUG_RINGS */
 618
 619
 620static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
 621{
 622        port_t *port = dev_to_port(dev);
 623        card_t *card = port_to_card(port);
 624        pkt_desc __iomem *desc;
 625        u32 buff, len;
 626        u8 page;
 627        u32 maxlen;
 628
 629        spin_lock_irq(&port->lock);
 630
 631        desc = desc_address(port, port->txin + 1, 1);
 632        BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
 633
 634#ifdef DEBUG_PKT
 635        printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
 636        debug_frame(skb);
 637#endif
 638
 639        desc = desc_address(port, port->txin, 1);
 640        buff = buffer_offset(port, port->txin, 1);
 641        len = skb->len;
 642        page = buff / winsize(card);
 643        buff = buff % winsize(card);
 644        maxlen = winsize(card) - buff;
 645
 646        openwin(card, page);
 647        if (len > maxlen) {
 648                memcpy_toio(winbase(card) + buff, skb->data, maxlen);
 649                openwin(card, page + 1);
 650                memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
 651        } else
 652                memcpy_toio(winbase(card) + buff, skb->data, len);
 653
 654#ifndef PAGE0_ALWAYS_MAPPED
 655        openwin(card, 0);       /* select pkt_desc table page back */
 656#endif
 657        writew(len, &desc->len);
 658        writeb(ST_TX_EOM, &desc->stat);
 659
 660        port->txin = next_desc(port, port->txin, 1);
 661        sca_outw(desc_offset(port, port->txin, 1),
 662                 get_dmac_tx(port) + EDAL, card);
 663
 664        sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
 665
 666        desc = desc_address(port, port->txin + 1, 1);
 667        if (readb(&desc->stat)) /* allow 1 packet gap */
 668                netif_stop_queue(dev);
 669
 670        spin_unlock_irq(&port->lock);
 671
 672        dev_kfree_skb(skb);
 673        return NETDEV_TX_OK;
 674}
 675
 676
 677#ifdef NEED_DETECT_RAM
 678static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
 679{
 680        /* Round RAM size to 32 bits, fill from end to start */
 681        u32 i = ramsize &= ~3;
 682        u32 size = winsize(card);
 683
 684        openwin(card, (i - 4) / size); /* select last window */
 685
 686        do {
 687                i -= 4;
 688                if ((i + 4) % size == 0)
 689                        openwin(card, i / size);
 690                writel(i ^ 0x12345678, rambase + i % size);
 691        } while (i > 0);
 692
 693        for (i = 0; i < ramsize ; i += 4) {
 694                if (i % size == 0)
 695                        openwin(card, i / size);
 696
 697                if (readl(rambase + i % size) != (i ^ 0x12345678))
 698                        break;
 699        }
 700
 701        return i;
 702}
 703#endif /* NEED_DETECT_RAM */
 704
 705
 706static void sca_init(card_t *card, int wait_states)
 707{
 708        sca_out(wait_states, WCRL, card); /* Wait Control */
 709        sca_out(wait_states, WCRM, card);
 710        sca_out(wait_states, WCRH, card);
 711
 712        sca_out(0, DMER, card); /* DMA Master disable */
 713        sca_out(0x03, PCR, card); /* DMA priority */
 714        sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
 715        sca_out(0, DSR_TX(0), card);
 716        sca_out(0, DSR_RX(1), card);
 717        sca_out(0, DSR_TX(1), card);
 718        sca_out(DMER_DME, DMER, card); /* DMA Master enable */
 719}
 720