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42#include "hw.h"
43#include "ar9002_phy.h"
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66static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
67{
68 u16 bMode, fracMode, aModeRefSel = 0;
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70 struct chan_centers centers;
71 u32 refDivA = 24;
72
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
74 freq = centers.synth_center;
75
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
77 reg32 &= 0xc0000000;
78
79 if (freq < 4800) {
80 u32 txctl;
81 int regWrites = 0;
82
83 bMode = 1;
84 fracMode = 1;
85 aModeRefSel = 0;
86 channelSel = CHANSEL_2G(freq);
87
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
89 if (freq == 2484) {
90
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
92 1, regWrites);
93 } else {
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
95 1, regWrites);
96 }
97 } else {
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
99 if (freq == 2484) {
100
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
102 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
103 } else {
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
105 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
106 }
107 }
108 } else {
109 bMode = 0;
110 fracMode = 0;
111
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
113 case 0:
114 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
115 aModeRefSel = 0;
116 else if ((freq % 20) == 0)
117 aModeRefSel = 3;
118 else if ((freq % 10) == 0)
119 aModeRefSel = 2;
120 if (aModeRefSel)
121 break;
122 case 1:
123 default:
124 aModeRefSel = 0;
125
126
127
128
129 fracMode = 1;
130 refDivA = 1;
131 channelSel = CHANSEL_5G(freq);
132
133
134 ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9,
135 AR_AN_SYNTH9_REFDIVA,
136 AR_AN_SYNTH9_REFDIVA_S, refDivA);
137
138 }
139
140 if (!fracMode) {
141 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
142 channelSel = ndiv & 0x1ff;
143 channelFrac = (ndiv & 0xfffffe00) * 2;
144 channelSel = (channelSel << 17) | channelFrac;
145 }
146 }
147
148 reg32 = reg32 |
149 (bMode << 29) |
150 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
151
152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
153
154 ah->curchan = chan;
155
156 return 0;
157}
158
159
160
161
162
163
164
165
166
167static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
168 struct ath9k_channel *chan)
169{
170 int bb_spur = AR_NO_SPUR;
171 int freq;
172 int bin;
173 int bb_spur_off, spur_subchannel_sd;
174 int spur_freq_sd;
175 int spur_delta_phase;
176 int denominator;
177 int tmp, newVal;
178 int i;
179 struct chan_centers centers;
180
181 int cur_bb_spur;
182 bool is2GHz = IS_CHAN_2GHZ(chan);
183
184 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
185 freq = centers.synth_center;
186
187 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
188 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
189
190 if (AR_NO_SPUR == cur_bb_spur)
191 break;
192
193 if (is2GHz)
194 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
195 else
196 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
197
198 cur_bb_spur = cur_bb_spur - freq;
199
200 if (IS_CHAN_HT40(chan)) {
201 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
202 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
203 bb_spur = cur_bb_spur;
204 break;
205 }
206 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
207 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
208 bb_spur = cur_bb_spur;
209 break;
210 }
211 }
212
213 if (AR_NO_SPUR == bb_spur) {
214 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
215 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
216 return;
217 } else {
218 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
219 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
220 }
221
222 bin = bb_spur * 320;
223
224 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
225
226 ENABLE_REGWRITE_BUFFER(ah);
227
228 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
229 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
230 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
231 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
232 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
233
234 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
235 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
236 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
237 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
238 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
239 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
240
241 if (IS_CHAN_HT40(chan)) {
242 if (bb_spur < 0) {
243 spur_subchannel_sd = 1;
244 bb_spur_off = bb_spur + 10;
245 } else {
246 spur_subchannel_sd = 0;
247 bb_spur_off = bb_spur - 10;
248 }
249 } else {
250 spur_subchannel_sd = 0;
251 bb_spur_off = bb_spur;
252 }
253
254 if (IS_CHAN_HT40(chan))
255 spur_delta_phase =
256 ((bb_spur * 262144) /
257 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
258 else
259 spur_delta_phase =
260 ((bb_spur * 524288) /
261 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
262
263 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
264 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
265
266 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
267 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
268 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
269 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
270
271 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
272 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
273
274 ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
275
276 REGWRITE_BUFFER_FLUSH(ah);
277}
278
279static void ar9002_olc_init(struct ath_hw *ah)
280{
281 u32 i;
282
283 if (!OLC_FOR_AR9280_20_LATER)
284 return;
285
286 if (OLC_FOR_AR9287_10_LATER) {
287 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
288 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
289 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
290 AR9287_AN_TXPC0_TXPCMODE,
291 AR9287_AN_TXPC0_TXPCMODE_S,
292 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
293 udelay(100);
294 } else {
295 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
296 ah->originalGain[i] =
297 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
298 AR_PHY_TX_GAIN);
299 ah->PDADCdelta = 0;
300 }
301}
302
303static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
304 struct ath9k_channel *chan)
305{
306 int ref_div = 5;
307 int pll_div = 0x2c;
308 u32 pll;
309
310 if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
311 if (AR_SREV_9280_20(ah)) {
312 ref_div = 10;
313 pll_div = 0x50;
314 } else {
315 pll_div = 0x28;
316 }
317 }
318
319 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
320 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
321
322 if (chan && IS_CHAN_HALF_RATE(chan))
323 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
324 else if (chan && IS_CHAN_QUARTER_RATE(chan))
325 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
326
327 return pll;
328}
329
330static void ar9002_hw_do_getnf(struct ath_hw *ah,
331 int16_t nfarray[NUM_NF_READINGS])
332{
333 int16_t nf;
334
335 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
336 nfarray[0] = sign_extend32(nf, 8);
337
338 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
339 if (IS_CHAN_HT40(ah->curchan))
340 nfarray[3] = sign_extend32(nf, 8);
341
342 if (!(ah->rxchainmask & BIT(1)))
343 return;
344
345 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
346 nfarray[1] = sign_extend32(nf, 8);
347
348 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
349 if (IS_CHAN_HT40(ah->curchan))
350 nfarray[4] = sign_extend32(nf, 8);
351}
352
353static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
354{
355 if (AR_SREV_9285(ah)) {
356 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
357 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
358 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
359 } else if (AR_SREV_9287(ah)) {
360 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
361 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
362 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
363 } else if (AR_SREV_9271(ah)) {
364 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
365 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
366 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
367 } else {
368 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
369 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
370 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
371 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
372 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
373 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
374 }
375}
376
377static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
378 struct ath_hw_antcomb_conf *antconf)
379{
380 u32 regval;
381
382 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
383 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
384 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
385 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
386 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
387 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
388 AR_PHY_9285_FAST_DIV_BIAS_S;
389 antconf->lna1_lna2_switch_delta = -1;
390 antconf->lna1_lna2_delta = -3;
391 antconf->div_group = 0;
392}
393
394static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
395 struct ath_hw_antcomb_conf *antconf)
396{
397 u32 regval;
398
399 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
400 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
401 AR_PHY_9285_ANT_DIV_ALT_LNACONF |
402 AR_PHY_9285_FAST_DIV_BIAS);
403 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
404 & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
405 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
406 & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
407 regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
408 & AR_PHY_9285_FAST_DIV_BIAS);
409
410 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
411}
412
413#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
414
415static void ar9002_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
416{
417 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
418 u8 antdiv_ctrl1, antdiv_ctrl2;
419 u32 regval;
420
421 if (enable) {
422 antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_ENABLE;
423 antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_ENABLE;
424
425
426
427
428 btcoex->bt_coex_mode2 &= (~(AR_BT_DISABLE_BT_ANT));
429 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
430
431 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM);
432 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);
433 } else {
434
435
436
437 antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_FIXED_A;
438 antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_FIXED_A;
439
440
441
442
443 btcoex->bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
444 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
445
446
447
448
449
450 REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);
451 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);
452 }
453
454 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
455 regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
456
457
458
459
460 regval &= (~(AR_PHY_9285_FAST_DIV_BIAS));
461 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL);
462 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
463 regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
464 regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);
465 regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
466 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
467
468 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
469 regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
470 regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
471 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
472}
473
474#endif
475
476static void ar9002_hw_spectral_scan_config(struct ath_hw *ah,
477 struct ath_spec_scan *param)
478{
479 u32 repeat_bit;
480 u8 count;
481
482 if (!param->enabled) {
483 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
484 AR_PHY_SPECTRAL_SCAN_ENABLE);
485 return;
486 }
487 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
488 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
489
490 if (AR_SREV_9280(ah))
491 repeat_bit = AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
492 else
493 repeat_bit = AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI;
494
495 if (param->short_repeat)
496 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
497 else
498 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
499
500
501
502
503
504 count = param->count;
505 if (param->endless) {
506 if (AR_SREV_9280(ah))
507 count = 0x80;
508 else
509 count = 0;
510 } else if (count & 0x80)
511 count = 0x7f;
512 else if (!count)
513 count = 1;
514
515 if (AR_SREV_9280(ah)) {
516 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
517 AR_PHY_SPECTRAL_SCAN_COUNT, count);
518 } else {
519 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
520 AR_PHY_SPECTRAL_SCAN_COUNT_KIWI, count);
521 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
522 AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT);
523 }
524
525 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
526 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
527 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
528 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
529
530 return;
531}
532
533static void ar9002_hw_spectral_scan_trigger(struct ath_hw *ah)
534{
535 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
536
537 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
538 AR_PHY_SPECTRAL_SCAN_ACTIVE);
539}
540
541static void ar9002_hw_spectral_scan_wait(struct ath_hw *ah)
542{
543 struct ath_common *common = ath9k_hw_common(ah);
544
545
546 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
547 AR_PHY_SPECTRAL_SCAN_ACTIVE,
548 0, AH_WAIT_TIMEOUT)) {
549 ath_err(common, "spectral scan wait failed\n");
550 return;
551 }
552}
553
554static void ar9002_hw_tx99_start(struct ath_hw *ah, u32 qnum)
555{
556 REG_SET_BIT(ah, 0x9864, 0x7f000);
557 REG_SET_BIT(ah, 0x9924, 0x7f00fe);
558 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
559 REG_WRITE(ah, AR_CR, AR_CR_RXD);
560 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
561 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20);
562 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
563 REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);
564 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
565 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
566 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
567}
568
569static void ar9002_hw_tx99_stop(struct ath_hw *ah)
570{
571 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
572}
573
574void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
575{
576 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
577 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
578
579 priv_ops->set_rf_regs = NULL;
580 priv_ops->rf_set_freq = ar9002_hw_set_channel;
581 priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
582 priv_ops->olc_init = ar9002_olc_init;
583 priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
584 priv_ops->do_getnf = ar9002_hw_do_getnf;
585
586 ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
587 ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;
588 ops->spectral_scan_config = ar9002_hw_spectral_scan_config;
589 ops->spectral_scan_trigger = ar9002_hw_spectral_scan_trigger;
590 ops->spectral_scan_wait = ar9002_hw_spectral_scan_wait;
591
592#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
593 ops->set_bt_ant_diversity = ar9002_hw_set_bt_ant_diversity;
594#endif
595 ops->tx99_start = ar9002_hw_tx99_start;
596 ops->tx99_stop = ar9002_hw_tx99_stop;
597
598 ar9002_hw_set_nf_limits(ah);
599}
600
